TWI497616B - 半導體封裝件之製法 - Google Patents

半導體封裝件之製法 Download PDF

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TWI497616B
TWI497616B TW101141515A TW101141515A TWI497616B TW I497616 B TWI497616 B TW I497616B TW 101141515 A TW101141515 A TW 101141515A TW 101141515 A TW101141515 A TW 101141515A TW I497616 B TWI497616 B TW I497616B
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interposer
carrier
semiconductor package
fabricating
conductive
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TW201419428A (zh
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莊冠緯
林畯棠
賴顗喆
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矽品精密工業股份有限公司
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Priority to TW101141515A priority Critical patent/TWI497616B/zh
Priority to CN201210459941.2A priority patent/CN103811363A/zh
Priority to US13/730,051 priority patent/US20140127864A1/en
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Description

半導體封裝件之製法
本發明係有關於一種半導體封裝件之製法，尤指一種能提升可靠度的半導體封裝件之製法。
於覆晶封裝製程中，隨著積體電路之積集度的增加，因晶片與封裝基板之間的熱膨脹係數(thermal expansion coefficient,CTE)不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的可靠度(reliability)下降，並造成信賴性測試失敗。為了解決上述問題，遂發展出以半導體基材作為中介結構的三維(3D)晶片堆疊技術，係於一封裝基板與一半導體晶片之間增設一矽中介板(Silicon interposer)，藉由該矽中介板與該半導體晶片的材質接近，而能有效避免熱膨脹係數不匹配所產生的問題。
一般習知三維晶片堆疊之製法係先將一矽中介板藉由複數導電凸塊結合至一封裝基板上，並形成底膠包覆該些導電凸塊，再進行烘烤製程，之後將一半導體晶片設於該矽中介板上。然而，因該矽中介板與封裝基板之熱膨脹係數(CTE)不同，故於進行烘烤製程時，易造成翹曲現象，致使該矽中介板與該封裝基板間之導電凸塊破裂，導致產品之可靠度不佳。
為解決此問題，遂發展出另一種半導體封裝件1之製 法，如第1A至1E圖所示。
如第1A及1B圖所示，提供一具有相對第一表面10a及第二表面10b之矽中介板10及一具有一膠層120之矽材承載件12。該矽中介板10中具有連通第一與第二表面10a,10b之複數導電矽穿孔(Through silicon via,TSV)100，且該矽中介板10之第一表面10a上具有複數銲球11，又該矽中介板10之第二表面10b上係形成有一電性連接該導電矽穿孔100之線路重佈結構(redistribution layer,RDL)102。
接著，將該矽中介板10以其第一表面10a壓合於該承載件12上，使該些銲球11壓入該膠層120中。然後，進行烘烤製程。因該承載件12與矽中介板10之熱膨脹係數(CTE)相近且具有剛性，故於進行烘烤製程時，可避免發生翹曲，因而該些銲球11不會破裂。
如第1C圖所示，將一半導體晶片13藉由複數導電凸塊130結合於該矽中介板10之第二表面10b上並電性連接該線路重佈結構102，再形成底膠131於該半導體晶片13與該線路重佈結構102之間，以包覆該些導電凸塊130。
如第1D及1E圖所示，移除該承載件12及該膠層120，以形成複數個半導體結構1’。之後，該半導體結構1’藉由該些銲球11結合至一封裝基板14上，並形成封裝膠體15於該半導體結構1’與該封裝基板14間以包覆該些銲球11，以形成半導體封裝件1。
惟，習知半導體封裝件1之製法中，該膠層120需具 有一定厚之厚度w(如第1A圖所示，其大於100um)以供該些銲球11壓入，致使形成該膠層120時，不易使該膠層120之厚度w分佈呈一致，即該膠層120之厚度w的一致性較差，故當該矽中介板10之第一表面10a壓平該膠層120以令該矽中介板10與該承載件12保持平行時(如第1B圖所示)，於該膠層120中之該些銲球11容易受該矽中介板10向下壓迫而位移，以致於造成該些銲球11與該導電矽穿孔100間之電性斷路或電性耦合不佳的現象，因而導致產品之可靠度不佳。
因此，如何克服習知技術中之問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：提供具有相對第一表面及第二表面的至少一中介板，該中介板之第一表面上具有複數導電元件；設置該中介板於一承載件上，該承載件具有複數凹部，以令該些導電元件對應收納於各該凹部中，而使該中介板卡合於該承載件上；結合半導體元件於該中介板之第二表面上；以及移除該承載件。
前述之製法中，係先提供一整版面基材，經切割該整版面基材後，使該中介板係為複數個，俾供設置該些中介板於該承載件上。
前述之製法中，該中介板係為一個時，復包括於移除該承載件之後，進行切割製程。
前述之製法中，於移除該承載件之後，結合封裝基板於該些導電元件上。
前述之製法中，該中介板之第一表面與該些導電元件上復具有離型膜，以令該離型膜結合於該承載件與各該凹部上。於移除該承載件之後，移除該離型膜。
前述之製法中，該些凹部係經蝕刻該承載件而形成者。例如，該承載件具有一絕緣層，係蝕刻該絕緣層以形成該些凹部。
前述之製法中，該中介板係為含矽基板，且該中介板具有連通其第一與第二表面之複數導電穿孔，該中介板上並具有電性連接該導電穿孔之線路重佈結構，而該半導體元件係結合並電性連接該至該線路重佈結構。
另外，前述之製法中，該凹部之深度係大於該導電元件之高度。
由上可知，本發明半導體封裝件之製法係藉由卡合方式使該中介板設於該承載件上，使該些導電元件因不會受壓迫而不會發生位移，故相較於習知壓合方式，本發明之製法可避免該些導電元件與該中介板間之電性斷路或電性耦合不佳的現象。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之半導體封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一由複數中介板20構成之整版面基材20’，該中介板20具有相對第一表面20a及第二表面20b，且該中介板20之第一表面20a上具有複數導電元件21。
於本實施例中，該中介板20中形成有連通其第一與第二表面20a,20b之複數導電穿孔200，且形成一離型膜201,201’於該中介板20之第一表面20a與該些導電元件21上，而該中介板20之第二表面20b上係形成有一電性連接該導電穿孔200之線路重佈結構(redistribution layer,RDL)202。
再者，該中介板20係為晶圓或其它含矽基板，且該導電穿孔200係為導電矽穿孔(Through silicon via, TSV)，而該導電元件21係例如為銲球或其它種類，並不限於此。
又，該中介板20之第一表面20a上可依需求形成有電性連接該導電穿孔200之另一線路重佈結構(圖略)，使該些導電元件21形成於該另一線路重佈結構之墊部(圖略)上，並使該離型膜201,201’覆設於該另一線路重佈結構與該些導電元件21上。
另外，有關前述線路重佈結構202與離型膜201,201’之態樣繁多，可依需求製作，故不詳述。
如第2B圖所示，沿預定之切割路徑L切割該整版面基材20’，以取得複數個該中介板20。
如第2C及2D圖所示，提供一具有一絕緣層22a之承載件22，且該絕緣層22a上具有複數凹部220。接著，該中介板20以其第一表面20a設置於該承載件22之絕緣層22a上，令該些導電元件21對應收納於各該凹部220中，使該中介板20卡合於該承載件22上，且該離型膜201,201’結合於該承載件22與各該凹部220之絕緣層22a上。接著，進行烘烤製程。
於本實施例中，形成該承載件22之材質係為低翹曲材質，例如，玻璃、金屬、矽或其它材質，且形成該絕緣層22a之材質係為膠材或其它材質，並以蝕刻方式於該絕緣層22a上形成該些凹部220。於其它實施例中，如第2C’圖所示，亦可不形成該絕緣層22a，而直接蝕刻該承載件22’以形成該些凹部220。另外，有關形成凹部220之方式 繁多，並不限於上述。
再者，該些凹部220之深度d僅需能卡合該導電元件21即可；較佳地，該凹部220之深度d係大於該導電元件21凸出該離型膜201之高度h。於其它實施例中，若無該離型膜201，則該凹部220之深度d需大於該導電元件21之高度。
如第2E圖所示，結合半導體元件23於該中介板20之第二表面20b上。於本實施例中，該半導體元件23藉由複數導電凸塊230結合並電性連接該線路重佈結構202，再形成底膠231於該半導體元件23與線路重佈結構202間以包覆該些導電凸塊230。
如第2F及2G圖所示，移除該承載件22及其絕緣層22a。接著，移除該離型膜201,201’，以製成所需之半導體結構2’。
如第2H圖所示，該半導體結構2’藉由該些導電元件21結合至一封裝基板24上，並形成封裝膠體25於該半導體結構2與該封裝基板24之間以包覆該些導電元件21，以形成半導體封裝件2。
本發明之半導體封裝件2之製法中，係藉由該承載件22之凹部220之設計，令該些導電元件21對應收納於各該凹部220中，使該中介板20卡合該承載件22上，因而無須將該些導電元件21壓入該凹部220中，故相較於習知技術，該些導電元件21不會發生位移，因而能避免該些導電元件21與該導電穿孔200間之電性斷路或電性耦合不佳 的現象。
再者，製作該些凹部220，易使其深度d呈一致性(例如同時蝕刻出該些凹部220)，故當該些導電元件21卡入該凹部220時，該中介板20與該承載件22(或該絕緣層22a)間不會相對傾斜，即該中介板20能平整設於該承載件22(或該絕緣層22a)上。
第3A至3D圖係為本發明之半導體封裝件2之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於整版面基材20’之切割步驟，其它相關製程大致相同，故以下僅詳述相異處，而不再詳述相同處。
如第3A圖所示，將一具有複數中介板單元30’之大尺寸中介板30(即該整版面基材20’)以其導電元件21卡合於該承載件22之凹部220中，且該離型膜201,201’結合於該承載件22之絕緣層22a上。
如第3B圖所示，結合半導體元件23於該中介板30之第二表面20b上並電性連接該線路重佈結構202。
如第3C圖所示，移除該承載件22及該離型膜201,201’。
如第3D圖所示，以該中介板單元30’之邊緣作切割路徑L(如第3C圖所示)，切割該中介板30(整版面基材20’)及其上之結構，使該中介板單元30’成為小尺寸之中介板20，再藉由該些導電元件21結合至一封裝基板24上，並形成封裝膠體25，以形成半導體封裝件2。
於另一切割流程中，如第3C’圖所示，係於移除該承 載件22及該離型膜201,201’之後，可先將一整版面封裝板34(由複數個封裝基板24所構成，令各該封裝基板24對應各該中介板單元30’)結合至該些導電元件21上，並形成封裝膠體25，再以該中介板單元30’之邊緣作切割路徑L進行切割，以形成複數個半導體封裝件2。
綜上所述，本發明之半導體封裝件之製法，主要藉由該承載件之凹部之設計，而以卡合方式將該中介板設於該承載件上，故該些導電元件不會發生位移，因而能避免發生該些導電元件之電性不良的現象，以有效提升產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧半導體封裝件
1’,2’‧‧‧半導體結構
10‧‧‧矽中介板
10a,20a‧‧‧第一表面
10b,20b‧‧‧第二表面
100‧‧‧導電矽穿孔
102,202‧‧‧線路重佈結構
11‧‧‧銲球
12,22,22’‧‧‧承載件
120‧‧‧膠層
13‧‧‧半導體晶片
130,230‧‧‧導電凸塊
131,231‧‧‧底膠
14,24‧‧‧封裝基板
15,25‧‧‧封裝膠體
20,30‧‧‧中介板
20’‧‧‧整版面基材
200‧‧‧導電穿孔
201,201’‧‧‧離型膜
21‧‧‧導電元件
22a‧‧‧絕緣層
220‧‧‧凹部
23‧‧‧半導體元件
30’‧‧‧中介板單元
34‧‧‧整版面封裝板
d‧‧‧深度
h‧‧‧高度
L‧‧‧切割路徑
w‧‧‧厚度
第1A至1E圖係為習知半導體封裝件之製法的剖視示意圖；第2A至2H圖係為本發明半導體封裝件之製法之第一實施例的剖面示意圖；其中，第2C’圖係為第2C圖之另一實施態樣；以及第3A至3D圖係為本發明半導體封裝件之製法之第二實施例的剖面示意圖；其中，第3C’圖係為第3C圖之另一實施態樣。
20‧‧‧中介板
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧導電穿孔
201,201’‧‧‧離型膜
202‧‧‧線路重佈結構
21‧‧‧導電元件
22‧‧‧承載件
22a‧‧‧絕緣層
220‧‧‧凹部
d‧‧‧深度
h‧‧‧高度

Claims (12)

  1. 一種半導體封裝件之製法，係包括：提供具有相對之第一表面及第二表面的至少一中介板，該中介板之第一表面上具有複數導電元件；設置該中介板於一承載件上，該承載件具有複數凹部，以令該些導電元件對應收納於各該凹部中，而使該中介板卡合於該承載件上；結合半導體元件於該中介板之第二表面上；以及移除該承載件。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，係包括先提供一整版面基材，經切割該整版面基材後，使該中介板係為複數個，俾供設置該些中介板於該承載件上。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括於移除該承載件之後，結合封裝基板於該些導電元件上。
  4. 如申請專利範圍第1或3項所述之半導體封裝件之製法，其中，該中介板係為一個時，該製法復包括於移除該承載件之後，進行切割製程。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該中介板之第一表面與該些導電元件上復具有離型膜，以令該離型膜結合於該承載件與各該凹部上。
  6. 如申請專利範圍第5項所述之半導體封裝件之製法，其中，於移除該承載件之後，移除該離型膜。
  7. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該中介板具有連通其第一與第二表面之複數導電穿孔。
  8. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該中介板上具有電性連接該導電穿孔之線路重佈結構，且該半導體元件係結合並電性連接至該線路重佈結構。
  9. 如申請專利範圍第1或7項所述之半導體封裝件之製法，其中，該中介板係為含矽基板。
  10. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該些凹部係經蝕刻該承載件而形成者。
  11. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該承載件具有一絕緣層，係蝕刻該絕緣層以形成該些凹部。
  12. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該凹部之深度係大於該導電元件之高度。
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