TWI541954B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI541954B
TWI541954B TW102128808A TW102128808A TWI541954B TW I541954 B TWI541954 B TW I541954B TW 102128808 A TW102128808 A TW 102128808A TW 102128808 A TW102128808 A TW 102128808A TW I541954 B TWI541954 B TW I541954B
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semiconductor
semiconductor package
insulating layer
fabricating
line portion
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TW102128808A
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TW201507075A (zh
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張宏達
賴顗喆
邱啓新
邱世冠
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矽品精密工業股份有限公司
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Priority to TW102128808A priority Critical patent/TWI541954B/zh
Priority to CN201310367493.8A priority patent/CN104377170B/zh
Priority to US14/074,148 priority patent/US9520304B2/en
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具晶圓級線路之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1A圖係為習知半導體封裝件1之剖面示意圖，該半導體封裝件1係於一封裝基板14與半導體晶片12之間設置一矽中介板(Through Silicon interposer,TSI)10，該矽中介板10具有導電矽穿孔(Through-silicon via,TSV)100及設於該導電矽穿孔100上之線路重佈結構(Redistribution layer,RDL)101，令該線路重佈結構101藉由複數導電元件18電性結合間距較大之封裝基板14之銲墊140，並形成底膠13包覆該些導電元件18，而間距較 小之半導體晶片12之電極墊120係藉由複數銲錫凸塊121電性結合該導電矽穿孔100。之後，再形成底膠13包覆該些銲錫凸塊121。
若該半導體晶片12直接結合至該封裝基板14上，因該半導體晶片12與該封裝基板14兩者的熱膨脹係數的差異甚大，故該半導體晶片12外圍的銲錫凸塊121不易與該封裝基板14上對應的銲墊140形成良好的接合，致使該銲錫凸塊121易自該封裝基板14上剝離。另一方面，因該半導體晶片12與該封裝基板14之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，致使該半導體晶片12與該封裝基板14之間的電性連接可靠度(reliability)下降，且將造成信賴性測試的失敗。
因此，藉由半導體基材製作之矽中介板10之設計，其與該半導體晶片12的材質接近，故可有效避免上述所產生的問題。
惟，前述習知半導體封裝件1之製法中，於製作該矽中介板10時，需形成該導電矽穿孔100，而該導電矽穿孔100之製程係需於該矽中介板10上挖孔及金屬填孔，致使該導電矽穿孔100之整體製程占整個該矽中介板10之製作成本達約40~50%(以12吋晶圓為例，不含人工成本)，以致於最終產品之成本及價格難以降低。
再者，該矽中介板10之製作技術難度高，致使該半導體封裝件1之生產量相對降低，且製作良率降低。
於是，業界遂發展出一種無需製作矽中介板之半導體封裝件1’，如第1B圖所示，其為複數半導體晶片12藉由銲錫凸塊121結合於一承載件(圖略)上之線路部11上，且形成底膠13於該線路部11與各該半導體晶片12之間，再形成封裝膠體16於該線路部11上以包覆各該半導體晶片12，藉以保護該些半導體晶片12，並增加該半導體封裝件1’之剛性。之後，移除該線路部11下側之承載件(圖略)，再形成一絕緣保護層17於該線路部11下側，且該絕緣保護層17外露該線路部11，以供結合如銲球之導電元件18。
惟，習知半導體封裝件1’中，各該半導體晶片12間之間隙極小，當移除該線路部11下側之承載件時，因該半導體晶片12、該線路部11之內金屬介電層(inter-metal dielectric,IMD)與封裝膠體16間的熱膨脹係數不匹配(mismatch)，致使使該線路部11之內金屬介電層因應力變化過大而破裂，進而造成該些銲錫凸塊121碎裂(crack)(如第1B圖所示之破裂處k)。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：線路部，係具有相對之第一側與第二側；複數半導體元件，係設於該線路部之第一側；壓合件，係設於該些半導體元件上；以及絕緣層，係設於該線 路部之第一側，以包覆該些半導體元件。
前述之半導體封裝件中，該絕緣層復包覆該壓合件，例如，該壓合件係外露於該絕緣層表面。
前述之半導體封裝件中，該絕緣層之側面與該壓合件之側面齊平。
前述之半導體封裝件中，復包括黏著材，可為晶片黏著層或熱介面材料，係設於該些半導體元件與該壓合件之間，例如，該黏著材復設於該絕緣層與該壓合件之間。
前述之半導體封裝件中，該絕緣層復設於該壓合件與該些半導體元件之間。
本發明復提供一種半導體封裝件之製法，係包括：提供一半導體結構，該半導體結構包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；結合壓合件於該些半導體元件上；形成絕緣層於該線路部上以包覆該些半導體元件；以及移除該承載件。
前述之製法中，該絕緣層復包覆該壓合件，例如，於形成該絕緣層後，令該壓合件外露於該絕緣層表面。
本發明又提供一種半導體封裝件之製法，係包括：提供一半導體結構，該半導體結構包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；形成絕緣層於該線路部上以包覆該些半導體元件；結合壓合件於該些半導體元件與該絕緣層上；以及移除該承載件。
前述之兩種製法中，該壓合件係藉由黏著材結合於該 些半導體元件(及該絕緣層上)上，例如，該黏著材係為晶片黏著層或熱介面材料。
本發明另提供一種半導體封裝件之製法，係包括：提供一半導體結構，該半導體結構包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；提供一具有絕緣層之壓合件，令該壓合件藉該絕緣層結合於該線路部上，且該絕緣層包覆該些半導體元件；以及移除該承載件。
前述之製法中，該絕緣層形成於該壓合件與該半導體元件之間。
前述之三種製法中，該承載件係為含矽之板體。
前述之半導體封裝件及三種製法中，該半導體結構復包含形成於該線路部與各該半導體元件之間的底膠。
前述之半導體封裝件及三種製法中，該絕緣層復形成於該線路部與各該半導體元件之間。
前述之半導體封裝件及三種製法中，該壓合件係為半導體擋片。
另外，前述之半導體封裝件及三種製法中，復包括於移除該承載件後，外露該線路部，俾供形成複數導電元件於該線路部上。
由上可知，本發明之半導體封裝件及其製法，主要藉由該壓合件之設計，以增加相鄰兩半導體元件間的強度，故當移除該承載件時，能避免該半導體元件與絕緣層間的熱膨脹係數不匹配所造成之碎裂問題。
1,1’,2,2’,3,3’,4,4’‧‧‧半導體封裝件
10‧‧‧矽中介板
100‧‧‧導電矽穿孔
101‧‧‧線路重佈結構
11,21‧‧‧線路部
12‧‧‧半導體晶片
120‧‧‧電極墊
121‧‧‧銲錫凸塊
13,23‧‧‧底膠
14‧‧‧封裝基板
140‧‧‧銲墊
16‧‧‧封裝膠體
17,27‧‧‧絕緣保護層
18,28‧‧‧導電元件
2a‧‧‧半導體結構
20‧‧‧承載件
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧介電層
211‧‧‧線路層
212‧‧‧電性接觸墊
22‧‧‧半導體元件
221‧‧‧導電凸塊
24,34‧‧‧黏著材
25,35,35’,45,45’‧‧‧壓合件
26,36,46‧‧‧絕緣層
270‧‧‧開孔
35a,36a,45a,46a‧‧‧側面
k‧‧‧破裂處
S‧‧‧切割路徑
第1A圖係為習知半導體封裝件之剖面示意圖；第1B圖係為習知半導體封裝件之剖面示意圖；第2A至2E圖係本發明之半導體封裝件之製法之第一實施例的剖面示意圖；其中，第2E’圖係第2E圖之其它實施例；第3A至3D圖係本發明之半導體封裝件之製法之第二實施例的剖面示意圖；其中，第3D’圖係第3D圖之其它實施例；以及第4A至4D圖係本發明之半導體封裝件之製法之第三實施例的剖面示意圖；其中，第4D’圖係第4D圖之其它實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述 之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之半導體封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一半導體結構2a，該半導體結構2a包含一承載件20、形成於該承載件20上之一線路部21、結合於該線路部21上之複數半導體元件22、及形成於該線路部21與各該半導體元件22之間的底膠23。
於本實施例中，該承載件20係為含矽之板體。
再者，該線路部21係包含相疊之複數介電層210與複數線路層211，並具有相對之第一側21a與第二側21b，該線路部21之第二側21b結合至該承載件20上，且該些半導體元件22結合於該線路部21之第一側21a。
又，各該半導體元件22藉由複數導電凸塊221覆晶結合該線路部21之線路層211，且該底膠23係包覆該些導電凸塊221。
另外，該線路層211係為晶圓級線路，而非封裝基板級線路。目前封裝基板最小之線寬與線距為12μm，而半導體製程能製作出3μm以下之線寬與線距。
如第2B圖所示，形成黏著材24於各該半導體元件22上。於本實施例中，該黏著材24係為晶片黏著層(die attach film,DAF)或熱介面材料(Thermal Interface Material,TIM)，如散熱膠。
如第2C圖所示，形成一壓合件25於該黏著材24上，以增加各該半導體元件22間的強度。
於本實施例中，該壓合件25係為半導體擋片(dummy die)，且該半導體擋片係由一晶圓經切單後所得之單一擋片。
再者，於其它實施例中，亦可先形成該黏著材24於該壓合件25上，再將該壓合件25以其上之黏著材24結合於各該半導體元件22上。
如第2D圖所示，形成一絕緣層26於該線路部21之第一側21a以包覆各該半導體元件22。
於本實施例中，該絕緣層26復包覆該壓合件25，且該壓合件25係外露於該絕緣層26表面；於其它實施例中，該壓合件25亦可未外露於該絕緣層26表面。
再者，該絕緣層26可為封裝膠體、壓合膜或塗佈方式形成之層等。
如第2E圖所示，移除該承載件20，以外露該線路部21之第二側21b，俾供形成複數導電元件28於該線路部21之第二側21b。之後，沿如第2D圖所示之切割路徑S進行切單製程，以獲得複數半導體封裝件2。
於本實施例中，係先形成複數電性連接該線路層211之電性接觸墊212於該線路部21之第二側21b，再形成一絕緣保護層27於該線路部21之第二側21b，且該絕緣保護層27形成有複數開孔270，令該些電性接觸墊212外露於各該開孔270，以供結合如銲球之導電元件28。
再者，於其它實施例中，亦可先進行切單製程，再形成電性接觸墊212、絕緣保護層27與導電元件28。
另外，於其它實施例中，可不形成該底膠23，而是形成該絕緣層26於該線路部21與各該半導體元件22之間，以包覆該些導電凸塊221，如第2E’圖所示。
第3A至3D圖係為本發明之半導體封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於壓合件與絕緣層之製作順序，其它步驟之製程大致相同，故不再贅述相同處。
如第3A圖所示，提供一如第2A圖所示之半導體結構2a。
如第3B圖所示，形成絕緣層36於該線路部21之第一側21a，以包覆各該半導體元件22，且令各該半導體元件22外露於該絕緣層36表面。
如第3C圖所示，形成一壓合件35於各該半導體元件22與該絕緣層36上。
於本實施例中，該壓合件35係藉由黏著材34結合於各該半導體元件22與該絕緣層36上。
再者，該壓合件35係為尚未切單之晶圓型態半導體擋片(dummy die)。
如第3D圖所示，移除該承載件20，以外露該線路部21之第二側21b，俾供形成複數導電元件28於該線路部21之第二側21b。之後，沿如第3C圖所示之切割路徑S進行切單製程，以獲得複數半導體封裝件3，且該絕緣層 36之側面36a與該壓合件35之側面35a齊平。
再者，於其它實施例中，如第3D’圖所示，於形成該些導電元件28後，可先薄化該壓合件35，以令該壓合件35’之厚度減少，再進行切單製程。
第4A至4D圖係為本發明之半導體封裝件4之製法之第三實施例的剖面示意圖。本實施例與第二實施例之差異在於壓合件之結合方式，其它步驟之製程大致相同，故不再贅述相同處。
如第4A圖所示，提供一如第2A圖所示之半導體結構2a。
如第4B圖所示，提供一具有絕緣層46之壓合件45，且該壓合件45係為尚未切單之晶圓型態半導體擋片(dummy die)。
如第4C圖所示，該壓合件45係藉由該絕緣層46結合於該線路部21之第一側21a，且該絕緣層46包覆各該半導體元件22。
於本實施例中，該絕緣層46係形成於該壓合件45與各該半導體元件22之間，以固定該壓合件45於各該半導體元件22上。
如第4D圖所示，移除該承載件20，以外露該線路部21之第二側21b，俾供形成複數導電元件28於該線路部21之第二側21b。之後，沿如第4C圖所示之切割路徑S進行切單製程，以獲得複數半導體封裝件4，且該絕緣層46之側面46a與該壓合件45之側面45a齊平。
再者，於其它實施例中，如第4D’圖所示，於形成該些導電元件28後，可先薄化該壓合件45，以令該壓合件45’之厚度減少，再進行切單製程。
本發明之製法係藉由該壓合件25,35,35’,45,45’結合於相鄰兩半導體元件22上，以增加相鄰兩半導體元件22間的強度，當移除該承載件20時，能避免因該半導體元件22與絕緣層26,36,46間的熱膨脹係數不匹配(mismatch)而造成之導電凸塊221碎裂(crack)之問題發生，故能避免該線路部21之介電層210破裂。
本發明係提供一種半導體封裝件2,2’,3,3’,4,4’，係包括：一線路部21、複數半導體元件22、一壓合件25,35,35’,45,45’以及絕緣層26,36,46。
所述之線路部21係具有相對之第一側21a與第二側21b。
所述之半導體元件22係設於該線路部21之第一側2la。
所述之壓合件25,35,35’,45,45’係設於該些半導體元件22上，且該壓合件25,35,35’,45,45’係為半導體擋片。
所述之絕緣層26,36,46係設於該線路部21之第一側21a，以包覆該些半導體元件22。
於一實施例中，該絕緣層26復包覆該壓合件25，且該壓合件25係外露於該絕緣層26表面。
於一實施例中，所述之半導體封裝件2復包括底膠23，其設於該線路部21之第一側21a與各該半導體元件 22之間。
於一實施例中，該絕緣層26復設於該線路部21之第一側21a與各該半導體元件22之間。
於一實施例中，所述之半導體封裝件2,2’,3,3’復包括黏著材24,34，例如晶片黏著層或熱介面材料，其設於各該半導體元件22與該壓合件25,35,35’之間。於一態樣中，該黏著材34復設於該絕緣層36與該壓合件35,35’之間。
於一實施例中，該絕緣層36,46之側面36a,46a與該壓合件35,45之側面35a,45a齊平。
於一實施例中，該絕緣層46復設於該壓合件45,45’與各該半導體元件22之間。
於一實施例中，所述之半導體封裝件2,2’,3,3’,4,4’復包括複數導電元件28，係設於該線路部21之第二側21b。
關於前述第一至第三實施例之半導體封裝件結構，較佳係形成底膠23於半導體元件22與線路部21之間；但亦可於半導體元件22與線路部21之間直接填充絕緣層26,36,46。
綜上所述，本發明之半導體封裝件及其製法，係藉由該壓合件結合於相鄰兩半導體元件上，以增加相鄰兩半導體元件間的強度，以避免該半導體元件之導電凸塊發生碎裂。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
21‧‧‧線路部
21a‧‧‧第一側
21b‧‧‧第二側
212‧‧‧電性接觸墊
22‧‧‧半導體元件
221‧‧‧導電凸塊
23‧‧‧底膠
24‧‧‧黏著材
25‧‧‧壓合件
26‧‧‧絕緣層
27‧‧‧絕緣保護層
270‧‧‧開孔
28‧‧‧導電元件

Claims (38)

  1. 一種半導體封裝件，係包括：線路部，係具有相對之第一側與第二側；複數半導體元件，係具有相對之第一表面及第二表面，且該些半導體元件係以該第一表面而設於該線路部之第一側；黏著材，係直接設於該些半導體元件之第二表面上；壓合件，係藉由該黏著材而直接結合於該些半導體元件之第二表面上；以及絕緣層，係設於該線路部之第一側，以包覆該些半導體元件。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該絕緣層復包覆該壓合件。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該壓合件係外露於該絕緣層表面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該黏著材復設於該絕緣層與該壓合件之間。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中，該黏著材係為晶片黏著層或熱介面材料。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該絕緣層復設於該線路部與各該半導體元件之間。
  7. 一種半導體封裝件，係包括：線路部，係具有相對之第一側與第二側； 複數半導體元件，係設於該線路部之第一側；壓合件，係設於該些半導體元件上，用以增加該些半導體元件之間的強度；以及絕緣層，係設於該線路部之第一側，以包覆該些半導體元件；其中，該壓合件與該絕緣層之間不具有黏著材。
  8. 如申請專利範圍第1或7項所述之半導體封裝件，其中，該壓合件係為半導體擋片。
  9. 如申請專利範圍第1或7項所述之半導體封裝件，其中，該絕緣層之側面與該壓合件之側面齊平。
  10. 如申請專利範圍第1或7項所述之半導體封裝件，其中，該絕緣層復設於該壓合件與該些半導體元件之間。
  11. 如申請專利範圍第1或7項所述之半導體封裝件，復包括複數導電元件，係設於該線路部之第二側。
  12. 如申請專利範圍第1或7項所述之半導體封裝件，復包括底膠，係設於該線路部與各該半導體元件之間。
  13. 一種半導體封裝件之製法，係包括：提供一半導體結構，係包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；結合壓合件於該些半導體元件上；形成絕緣層於該線路部上以包覆該些半導體元件；以及移除該承載件。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該承載件係為含矽之板體。
  15. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該半導體結構復包含形成於該線路部與各該半導體元件之間的底膠。
  16. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該絕緣層復形成於該線路部與各該半導體元件之間。
  17. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該壓合件係為半導體擋片。
  18. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該壓合件係藉由黏著材結合於該些半導體元件上。
  19. 如申請專利範圍第18項所述之半導體封裝件之製法，其中，該黏著材係為晶片黏著層或熱介面材料。
  20. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該絕緣層復包覆該壓合件。
  21. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括於形成該絕緣層後，令該壓合件外露於該絕緣層表面。
  22. 如申請專利範圍第13項所述之半導體封裝件之製法，復包括於移除該承載件後，係外露該線路部，俾供形成複數導電元件於該線路部上。
  23. 一種半導體封裝件之製法，係包括： 提供一半導體結構，係包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；形成絕緣層於該線路部上以包覆該些半導體元件；同時結合壓合件於該些半導體元件與該絕緣層之表面上；以及移除該承載件。
  24. 如申請專利範圍第23項所述之半導體封裝件之製法，其中，該承載件係為含矽之板體。
  25. 如申請專利範圍第23項所述之半導體封裝件之製法，其中，該半導體結構復包含形成於該線路部與各該半導體元件之間的底膠。
  26. 如申請專利範圍第23項所述之半導體封裝件之製法，其中，該絕緣層復形成於該線路部與各該半導體元件之間。
  27. 如申請專利範圍第23項所述之半導體封裝件之製法，復包括於結合該壓合件前，令該些半導體元件外露於該絕緣層表面。
  28. 如申請專利範圍第27項所述之半導體封裝件之製法，其中，該壓合件係藉由黏著材結合於該些半導體元件與該絕緣層上。
  29. 如申請專利範圍第28項所述之半導體封裝件之製法，其中，該黏著材係為晶片黏著層或熱介面材料。
  30. 如申請專利範圍第23項所述之半導體封裝件之製法，其中，該壓合件係為半導體擋片。
  31. 如申請專利範圍第23項所述之半導體封裝件之製法，復包括於移除該承載件後，外露該線路部，俾供形成複數導電元件於該線路部上。
  32. 一種半導體封裝件之製法，係包括：提供一半導體結構，係包含承載件、形成於該承載件上之線路部、及結合於該線路部上之複數半導體元件；提供一具有絕緣層之壓合件，令該壓合件藉該絕緣層結合於該線路部上，且該絕緣層包覆該些半導體元件；以及移除該承載件。
  33. 如申請專利範圍第32項所述之半導體封裝件之製法，其中，該承載件係為含矽之板體。
  34. 如申請專利範圍第32項所述之半導體封裝件之製法，其中，該半導體結構復包含形成於該線路部與各該半導體元件之間的底膠。
  35. 如申請專利範圍第32項所述之半導體封裝件之製法，其中，該絕緣層復形成於該線路部與各該半導體元件之間。
  36. 如申請專利範圍第32項所述之半導體封裝件之製法，其中，該絕緣層形成於該壓合件與該半導體元件之間。
  37. 如申請專利範圍第32項所述之半導體封裝件之製法， 其中，該壓合件係為半導體擋片。
  38. 如申請專利範圍第32項所述之半導體封裝件之製法，復包括於移除該承載件後，係外露該線路部，俾供形成複數導電元件於該線路部上。
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