TW201742167A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201742167A
TW201742167A TW105115286A TW105115286A TW201742167A TW 201742167 A TW201742167 A TW 201742167A TW 105115286 A TW105115286 A TW 105115286A TW 105115286 A TW105115286 A TW 105115286A TW 201742167 A TW201742167 A TW 201742167A
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Taiwan
Prior art keywords
layer
circuit
electronic package
conductive pillars
electronic
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TW105115286A
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English (en)
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TWI574333B (zh
Inventor
程呂義
李宏元
賴杰隆
彭仕良
呂長倫
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105115286A priority Critical patent/TWI574333B/zh
Priority to CN201610382592.7A priority patent/CN107403785B/zh
Priority to US15/258,441 priority patent/US10128178B2/en
Application granted granted Critical
Publication of TWI574333B publication Critical patent/TWI574333B/zh
Publication of TW201742167A publication Critical patent/TW201742167A/zh
Priority to US16/157,430 priority patent/US10403570B2/en

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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種電子封裝件，係包括：具有相對之第一表面及第二表面之線路結構、設於該第一表面上之金屬層、設於該金屬層上之電子元件、包覆該電子元件之封裝層、設於該第二表面上之複數導電柱、以及包覆該些導電柱之絕緣層。藉由於該線路結構之表面上形成導電柱，並以絕緣層包覆該導電柱，故能依深寬比需求製作各種尺寸之導電柱，使終端產品達到輕、薄、短、小之需求。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件，尤指一種具輕薄短小化之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢，其中應用於晶片封裝領域之技術包含有：晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D IC)晶片堆疊之半導體封裝件1之剖面示意圖，其包含有一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該轉接側10b上具有複數線路重佈層(Redistribution layer，簡稱RDL)101，以將間距較小之半導體晶片19之 電極墊190係藉由複數銲錫凸塊102電性結合至該置晶側10a上，再以底膠192包覆該些銲錫凸塊102，且形成封裝膠體18於該矽中介板10上，以覆蓋該半導體晶片19，另於該線路重佈層101上藉由複數如凸塊之導電元件103電性結合間距較大之封裝基板17之銲墊170，並以底膠172包覆該些導電元件103。
再者，製作該半導體封裝件1時，係先將該半導體晶片19置放於該矽中介板10上，再將該矽中介板10以該些導電元件103接置於該封裝基板17上，之後形成該封裝膠體18。
此外，於後續應用該半導體封裝件1之組裝製程時，該半導體封裝件1係藉由該封裝基板17下側結合至一電路板(圖略)上，以利用該些導電矽穿孔100作為該半導體晶片19與該電路板之間訊號傳遞的介質。
惟，習知半導體封裝件1之製法中，使用該矽中介板10作為該半導體晶片19與該封裝基板17之間訊號傳遞的介質，因需具備一定深寬比之控制(即該導電矽穿孔100之深寬比為100um/10um)，才能製作出適用的矽中介板10，因而往往需耗費大量製程時間及化學藥劑之成本，進而提高製程難度及製作成本。
再者，該封裝基板17具有含玻纖材料之核心層，致使該封裝基板17厚度相當厚，因而不利於產品之輕薄短小化。
又，該些銲錫凸塊102與導電元件103接置該矽中介 板10時已進行回銲(reflow)，故當形成該封裝膠體18時，該矽中介板10容易因多次加熱製程而造成其溫度變化過大，致使該矽中介板10發生翹曲現象。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面結合有第一線路層，該第二表面結合有第二線路層；金屬層，係形成於該線路結構之第一表面上且電性連接該第一線路層；電子元件，係設於該線路結構之第一表面上且電性連接該金屬層；封裝層，係形成於該線路結構之第一表面上，以包覆該電子元件；複數導電柱，係設於該線路結構之第二表面上且電性連接該第二線路層；以及絕緣層，係形成於該線路結構之第二表面上，以包覆該些導電柱，且令該些導電柱之部分表面外露於該絕緣層。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之線路結構，且該線路結構之第一表面結合有第一線路層，該第二表面結合有第二線路層；形成複數導電柱於該線路結構之第二表面上，且該些導電柱電性連接該第二線路層；形成絕緣層於該線路結構之第二表面上，以令該絕緣層包覆該些導電柱；形成金屬層於該線路結構之第一表面上，且該金屬層電性連 接該第一線路層；設置電子元件於該線路結構之第一表面上，且該電子元件電性連接該金屬層；形成封裝層於該線路結構之第一表面上，以包覆該電子元件；以及移除部分該絕緣層，以外露該導電柱之部分表面。
前述之電子封裝件及其製法中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。
前述之電子封裝件及其製法中，該金屬層係為圖案化線路層。
前述之電子封裝件及其製法中，該封裝層之材質與該絕緣層之材質係為相同或不相同。
前述之電子封裝件及其製法中，該封裝層可延伸至該線路結構之側面。
前述之電子封裝件及其製法中，該封裝層接觸該絕緣層。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該些導電柱上。
前述之電子封裝件及其製法中，復包括接置於該些導電柱上之電子組件。
由上可知，本發明之電子封裝件及其製法，主要藉由於該線路結構上直接長出該些導電柱，且以絕緣層包覆該些導電柱，因而不需形成如習知矽穿孔，故能依深寬比需求製作各種尺寸之導電柱，使終端產品達到輕、薄、短、小之需求，且能提高產量並節省化學藥劑費用支出。
再者，本發明之製法係以該絕緣層取代習知矽中介 板，並利用該些導電柱作為該電子元件與電路板之間訊號傳遞的介質，故相較於習知技術，本發明之製法無需製作TSV，因而大幅降低製程難度及製作成本。
又，相較於習知技術，本發明之製法無需使用矽中介板，故不會發生習知矽中介板因加熱而發生翹曲之問題。
另外，藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板及一具TSV之矽中介板，故可減少該電子封裝件之厚度。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧置晶側
10b‧‧‧轉接側
100‧‧‧導電矽穿孔
101‧‧‧線路重佈層
102,230‧‧‧銲錫凸塊
103,25‧‧‧導電元件
17‧‧‧封裝基板
170‧‧‧銲墊
172,192‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧半導體晶片
190‧‧‧電極墊
2,2’‧‧‧電子封裝件
20‧‧‧承載件
200‧‧‧分隔層
21‧‧‧線路結構
21’‧‧‧第一線路部
21”‧‧‧第二線路部
21a‧‧‧第一表面
21b‧‧‧第二表面
21c‧‧‧側面
210‧‧‧介電層
210’‧‧‧絕緣隔層
211‧‧‧內部線路層
211’‧‧‧第一線路層
211”‧‧‧第二線路層
212‧‧‧凸塊底下金屬層
22‧‧‧金屬層
23‧‧‧電子元件
24,24’‧‧‧封裝層
26‧‧‧導電柱
27‧‧‧絕緣層
28‧‧‧電子組件
30‧‧‧整版面基板
300‧‧‧切割道
9‧‧‧電路板
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2G圖係為本發明之電子封裝件之製法的剖面示意圖；第2H圖係為本發明之電子封裝件後續應用之剖面示意圖；以及第3A至3C圖係為本發明之電子封裝件之另一實施例之製法的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一具有一分隔層200之承載件20，再形成一線路結構21於該承載件20之分隔層200上。接著，形成複數導電柱26於該線路結構21上。
於本實施例中，該承載件20係為半導體板體，例如虛設矽晶圓(dummy Si wafer)、玻璃或高分子板材，且該分隔層200係例如熱化二氧化矽層(thermal SiO2 layer)或黏著層(較佳為有機黏著層)。
再者，該線路結構21可利用線路重佈層(Redistribution layer，簡稱RDL)製程形成，且該線路結構21係具有相對之第一表面21a與第二表面21b，並以該第一表面21a結合於該分隔層200上。
具體地，該線路結構21係具有複數介電層210、形成於該介電層210中之內部線路層211、形成於該第一表面21a之介電層210上之第一線路層211’、及形成於該第二表面21b之介電層210上之第二線路層211”，其中，該 第一線路層211’之最小線路寬度係小於該第二線路層211”之最小線路寬度，且該第二線路層211”上形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)212，以結合該些導電柱26。
又，考量線路之線寬變化，需於該承載件20上先形成細線寬之線路層(如0.7um)，再形成中線寬之線路層(如5um)，接著形成寬線寬之線路層(10um)，之後再做更寬的線路層，以此類推。此乃由於細線路層及其上之介電層平整度較平，如此往上作寬線路時，可符合上層線路層平整度要求。反之，若於該承載件20之表面依序往上形成寬、中、細之線路層，由於底部之寬線路層平整度不夠平整，會產生線路層之可靠度問題，故往上無法依序製作出中、細之線路層。
因此，較佳地，當所需之線路的線寬太小時(如小於或等於1um以下時)，可先以晶圓製程完成第一線路部21’之佈線(含絕緣隔層210’)，再送至後端封裝製程進行第二線路部21”之佈線，使該線路結構21包含相疊之第一線路部21’與第二線路部21”，且該第一線路部21’係結合該分隔層200。
然而，本發明之第一線路部21’係可包括但不限於一定要用晶圓製程完成(如大於或等於1um以上時)。例如，由於晶圓製程之線路層用之介電層需以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽，其成本較高，故可採用一般非晶圓製程方式形成線 路，即採用成本較低之高分子介電層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)以塗佈方式形成於線路之間進行絕緣。
另外，係以圖案化方式(如電鍍金屬、沉積金屬或蝕刻金屬等)形成該導電柱26，以於該線路結構21之第二表面21b上形成如銅柱之金屬柱。
如第2B圖所示，形成一絕緣層27於該線路結構21之第二表面21b上，以包覆該些導電柱26。
於本實施例中，形成該絕緣層27之材質係為係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第2C圖所示，移除該承載件20，且使該分隔層200保留於該線路結構21上。
於本實施例中，當該承載件20係為矽晶圓材質時，先研磨移除該承載件20之大部分材質，再利用蝕刻方式清除剩餘該承載件20之材質，以保留該分隔層200，其中該分隔層200係作為蝕刻停止層。當該承載件20係為玻璃材質時，係以加熱方式或照光方式(如UV光)，使該分隔層200失去部分黏性，以移除該承載件20而保留該分隔層200，其中，該分隔層200係作為黏著層使用。
如第2D圖所示，形成一金屬層22於該分隔層200上，且該金屬層22電性連接該線路結構21之第一線路層211’。接著，選擇性地對該金屬層22與該線路結構21進行電性測試。
於本實施例中，該金屬層22係例如以電鍍方式製作，故會先形成導電層(圖略)於該分隔層200上，且該金屬層22係為圖案化線路層，其包含電性接觸墊(pad)與導電跡線(trace)。然而，有關線路製程之方式繁多，如RDL製程，故於此不再贅述。
再者，先進行線路測試，待確認線路結構21與金屬層22正常後，再接置良好晶粒(Known Good Die，簡稱KGD)，即後述之電子元件23，以防止最終封裝件因線路結構21與金屬層22製作瑕疵，發生良率不佳之問題。
如第2E圖所示，設置複數電子元件23於該線路結構21之第一表面21a上。接著，形成一封裝層24於該線路結構21之第一表面21a上，以包覆該些電子元件23。
於本實施例中，該電子元件23係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，該電子元件23係以覆晶方式電性連接該線路結構21。例如，該電子元件23藉由複數銲錫凸塊230電性結合至該金屬層22上。另外，該電子元件23亦可以打線方式電性連接該金屬層22。
又，形成該封裝層24之材質係為聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材，且該封裝層24與該絕緣層27之材質可為相同或不相同。
如第2F圖所示，移除部分該絕緣層27，以外露該導電柱26之部分表面。
於本實施例中，於該絕緣層27上進行整平製程，如研磨方式，使該導電柱26之外露表面齊平該絕緣層27之表面。於其它實施例中，可於該絕緣層27上進行開孔製程，使該導電柱26之表面外露於該絕緣層27之開孔。
再者，應可理解地，亦可於該封裝層24上進行整平製程或開孔製程，使該電子元件23之部分表面外露於該封裝層24之表面。
又，可將該金屬層22、導電柱26、絕緣層27與線路結構21視為一封裝基板。
如第2G圖所示，形成複數導電元件25於各該導電柱26上。
於本實施例中，該導電元件25係為銲球、金屬凸塊或金屬針等，其結合於各該導電柱26上以電性連接該第二線路層211”。
再者，該線路結構21之第二表面21b、該第二線路層211”與該導電柱26作為植球側，使該電子封裝件2可藉由該些導電元件25直接電性連接至一電路板9(如第2H圖所示)，而無需再藉由額外之矽中介板，故可降低製作成本，且可降低終端產品之整體厚度。
又，如第3C圖所示之電子封裝件2’，該封裝層24’可延伸至該線路結構21之側面21c以接觸該絕緣層27，使該封裝層24’與該絕緣層27完整地包覆該線路結構21。具體地，如第3A圖所示，於第2D圖之製程，係提供一由複數線路結構21所組成之整版面基板30，且藉由切 除(die saw)製程以於該線路結構21之第一表面21a上形成複數切割道300，由於該些切割道300位在該線路結構21四周，故於切割時順便移除該線路結構21邊緣，但未移除該絕緣層27；接著，如第3B圖所示，進行如第2E圖之製程，且令該封裝層24’填入該些切割道300中，以包覆該線路結構21之側面21c；最後，沿各該切割道300進行切單製程，以得到如第3C圖所示之電子封裝件2’。
另外，於該些導電柱26上亦可利用該導電元件25接置至少一電子組件28，且該電子組件28係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。具體地，於第2G’圖中，該電子組件28係以被動元件為例。因此，該電子封裝件2’形成有第一與第二線路層211’,211”，故於該電子封裝件2’之上、下兩側皆可接置電子零組件，因而能提升其電性功能。
應可理解地，於量產時，第2A圖之製程會採用由複數線路結構21所組成之整版面基板，以於形成複數導電元件25後，進行切單製程，而得到如第2G或2G’圖所示之電子封裝件2,2’。
本發明之製法中係藉由於該線路結構21上形成該導電柱26，且以絕緣層27包覆該些導電柱26，因而不需形成孔洞，故能依深寬比需求製作各種尺寸(如深寬比小)之導電柱26，使終端產品達到輕、薄、短、小之需求，且能提高產量(Throughput)並節省化學藥劑費用支出。
再者，本發明之製法係以該絕緣層27取代習知矽中介板，並利用該些導電柱26作為該電路板9與該電子元件23之間訊號傳遞的介質，故相較於習知技術，本發明之製法無需製作TSV，因而大幅降低製程難度及製作成本。
又，相較於習知技術，本發明之製法無需使用矽中介板，故不會發生習知矽中介板因加熱而發生翹曲之問題。
另外，本發明之製法係直接將高I/O功能之電子元件23接置於該線路結構21之第一線路層211’上，因而不需使用一含核心層之封裝基板及一具有TSV之矽中介板，故可減少該電子封裝件2,2’之厚度。
本發明復提供一種電子封裝件2,2’，係包括：一線路結構21、一金屬層22、複數電子元件23、一封裝層24,24’、複數導電柱26以及一絕緣層27。
所述之線路結構21係具有相對之第一表面21a及第二表面21b，且該第一表面21a結合有第一線路層211’，該第二表面21b結合有第二線路層211”。
所述之金屬層22係形成於該線路結構21之第一表面21a上且電性連接該第一線路層211’。
所述之電子元件23係設於該線路結構21之第一表面21a上且電性連接該金屬層22。
所述之封裝層24,24’係形成於該線路結構21之第一表面21a上，以包覆該些電子元件23。
所述之導電柱26係設於該線路結構21之第二表面21b上且電性連接該第二線路層211”。
所述之絕緣層27係形成於該線路結構21之第二表面21b上，以包覆該些導電柱26，且令該些導電柱26之部分表面外露於該絕緣層27。
於一實施例中，該第一線路層211’之最小線路寬度係小於該第二線路層211”之最小線路寬度。
於一實施例中，該金屬層22係為圖案化線路層。
於一實施例中，該封裝層24,24’之材質與該絕緣層27之材質係為相同。
於一實施例中，該封裝層24,24’之材質與該絕緣層27之材質係為不相同。
於一實施例中，該封裝層24’接觸該絕緣層27。
於一實施例中，該電子封裝件2復包括複數導電元件25，係形成於該些導電柱26上。
於一實施例中，該電子封裝件2’復包括至少一電子組件28，係接置於該些導電柱26上。
綜上所述，本發明之電子封裝件及其製法，藉由於該線路結構上直接長出該導電柱，且以該絕緣層包覆該些導電柱，因而不需形成孔洞，故能製作出深寬比較小之導電柱，使終端產品達到輕、薄、短、小之需求，且能提高產量，並節省化學藥劑費用支出。
再者，藉由該絕緣層取代習知矽中介板，並利用該些導電柱作為電路板與電子元件之間訊號傳遞的介質，故相較於習知技術，本發明之製法無需製作TSV，因而大幅降低製程難度及製作成本。
又，本發明之製法無需使用矽中介板，故不會發生習知矽中介板因加熱而發生翹曲之問題。
另外，藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板及一具有TSV之矽中介板，故可減少該電子封裝件之厚度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
21‧‧‧線路結構
21a‧‧‧第一表面
21b‧‧‧第二表面
211’‧‧‧第一線路層
211”‧‧‧第二線路層
22‧‧‧金屬層
23‧‧‧電子元件
24‧‧‧封裝層
25‧‧‧導電元件
26‧‧‧導電柱
27‧‧‧絕緣層

Claims (18)

  1. 一種電子封裝件，係包括：線路結構，係具有相對之第一表面及第二表面，且該第一表面結合有第一線路層，該第二表面結合有第二線路層；金屬層，係形成於該線路結構之第一表面上且電性連接該第一線路層；電子元件，係設於該線路結構之第一表面上且電性連接該金屬層；封裝層，係形成於該線路結構之第一表面上，以包覆該電子元件；複數導電柱，係設於該線路結構之第二表面上且電性連接該第二線路層；以及絕緣層，係形成於該線路結構之第二表面上，以包覆該些導電柱，且令各該些導電柱之部分表面外露於該絕緣層。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該金屬層係為圖案化線路層。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層之材質與該絕緣層之材質係為相同。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該封 裝層之材質與該絕緣層之材質係為不相同。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層可延伸至該線路結構之側面。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層接觸該絕緣層。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該些導電柱上之複數導電元件。
  9. 如申請專利範圍第1項所述之電子封裝件，復包括接置於該些導電柱上之電子組件。
  10. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之線路結構，且該線路結構之第一表面結合有第一線路層，該第二表面結合有第二線路層；形成複數導電柱於該線路結構之第二表面上，且該些導電柱電性連接該第二線路層；形成絕緣層於該線路結構之第二表面上，以令該絕緣層包覆該些導電柱；形成金屬層於該線路結構之第一表面上，且該金屬層電性連接該第一線路層；設置電子元件於該線路結構之第一表面上，且該電子元件電性連接該金屬層；形成封裝層於該線路結構之第一表面上，以包覆該電子元件；以及移除部分該絕緣層，以外露各該導電柱之部分表 面。
  11. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該第一線路層之最小線路寬度係小於該第二線路層之最小線路寬度。
  12. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該金屬層係為圖案化線路層。
  13. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該封裝層之材質與該絕緣層之材質係為相同。
  14. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該封裝層之材質與該絕緣層之材質係為不相同。
  15. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該封裝層可延伸至該線路結構之側面。
  16. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該封裝層接觸該絕緣層。
  17. 如申請專利範圍第10項所述之電子封裝件之製法，復包括形成複數導電元件於該些導電柱上。
  18. 如申請專利範圍第10項所述之電子封裝件之製法，復包括於該些導電柱上接置電子組件。
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