TWI587458B - 電子封裝件及其製法與基板結構 - Google Patents

電子封裝件及其製法與基板結構 Download PDF

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TWI587458B
TWI587458B TW104108424A TW104108424A TWI587458B TW I587458 B TWI587458 B TW I587458B TW 104108424 A TW104108424 A TW 104108424A TW 104108424 A TW104108424 A TW 104108424A TW I587458 B TWI587458 B TW I587458B
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conductive
dielectric layer
substrate body
carrier
electronic package
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TW201635449A (zh
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蔣靜雯
彭康瑋
陳光欣
陳賢文
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矽品精密工業股份有限公司
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Priority to TW104108424A priority Critical patent/TWI587458B/zh
Priority to CN201510304458.0A priority patent/CN106206509B/zh
Priority to US14/984,256 priority patent/US10049973B2/en
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Description

電子封裝件及其製法與基板結構
本發明係有關一種電子封裝件，尤指一種節省製作成本之電子封裝件及其製法與基板結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1A至1F圖係為習知3D晶片堆疊之電子封裝件1之製法之剖面示意圖。
如第1A圖所示，提供一具有相對之轉接側10b與置晶側10a之矽板體10，且該矽板體10之置晶側10a上形成有複數開孔100。
如第1B圖所示，將絕緣材102與導電材(如銅材)填入該些開孔100中以形成導電矽穿孔(Through-silicon via，簡稱TSV)101。接著，於該置晶側10a上形成一電性連接該導電矽穿孔101之線路重佈結構(Redistribution layer，簡稱RDL)。
具體地，該線路重佈結構之製法，係包括形成一介電層11於該置晶側10a上，再形成一線路層12於該介電層11上，且該線路層12形成有位於該介電層11中並電性連接該導電矽穿孔101之複數導電盲孔120，之後形成一絕緣保護層13於該介電層11與該線路層12上，且該絕緣保護層13外露部分該線路層11，最後結合複數如銲錫凸塊之第一導電元件14於該線路層12之外露表面上。
如第1C圖所示，一暫時性載具40(如玻璃)以膠材400結合於該置晶側10a之絕緣保護層13上，再研磨該轉接側10b之部分材質，使該些導電矽穿孔101之端面外露於該轉接側10b’。
具體地，於研磨製程中，該矽板體10未研磨前的厚度h約700至750um(如第1B圖所示)，而研磨後的厚度h’係為100um(如第1C圖所示)，則一般製程會先以機械研磨方式使該該矽板體10之厚度剩下102至105um，再以化學機械研磨(Chemical-Mechanical Polishing，簡稱CMP)方式研磨至100um。
再者，該膠材400之厚度t為50um，因而會受限於該膠材400之總厚度變動(total thickness variation，簡稱TTV)，若TTV過大(約為10um)，如第1C’圖所示，該矽板體10於左右側會發生高低傾斜，該矽板體10於研磨 時會有碎裂風險(crack risk)，且於研磨後，往往僅部分該導電矽穿孔101露出，而部分該導電矽穿孔101沒有露出。
又，因薄化該矽板體10有所限制(研磨後的厚度h’係為100um)，故該導電矽穿孔101會有一定的深度d(約100um)，使該導電矽穿孔101之深寬比受限為100um/10um(即深度d為100um，寬度w為10um)。
另外，若欲使該導電矽穿孔101之深度僅為10um，將因製程成本過高而無法量產。具體地，因該膠材400之TTV約為10um，使研磨(機械研磨與CMP)該矽板體10之厚度h’只能磨薄至剩下100um，而後續需藉由濕蝕刻(wet etch)移除該矽板體10之厚度h”約90um之多，才能使該導電矽穿孔101露出，故需採用濕蝕刻製程，但蝕刻製程時間冗長，導致需極多蝕刻藥液及製作成本提高。
如第1D圖所示，先形成一絕緣保護層15於該轉接側10b’上，且該絕緣保護層15外露該些導電矽穿孔101之端面，再結合複數第二導電元件16於該些導電矽穿孔101之端面上，且該第二導電元件16電性連接該導電矽穿孔101，其中，該第二導電元件16係含有銲錫材料或銅凸塊，且可選擇性含有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)160。
如第1E圖所示，沿如第1D圖所示之切割路徑S進行切單製程，以獲取複數個矽中介板(Through Silicon interposer，簡稱TSI)1a，再將至少一矽中介板1a以其第 二導電元件16設於一封裝基板19上，使該封裝基板19電性連接該些導電矽穿孔101，其中，該封裝基板19係以間距較大之電性接觸墊190結合該些第二導電元件16，使該些第二導電元件16電性連接該些導電矽穿孔101，再以底膠191包覆該些第二導電元件16。
如第1F圖所示，將具有間距較小之電極墊的複數電子元件17(如晶片)設置於該些第一導電元件14上，使該電子元件17電性連接該線路層12，其中，該電子元件17係以覆晶方式結合該些第一導電元件14，再以底膠171包覆該些第一導電元件14。
接著，形成封裝材18於該封裝基板19上，以令該封裝材18包覆該電子元件17與該矽中介板1a。
最後，形成複數銲球192於該封裝基板19之下側，以供接置於一如電路板之電子裝置(圖略)上。
惟，習知電子封裝件1之製法中，使用矽中介板1a作為電子元件17與封裝基板19之間訊號傳遞的介質，因需具備一定深寬比之控制(即該導電矽穿孔101之深寬比為100um/10um)，才能製作出適用的矽中介板1a，因而往往需耗費大量製程時間及化學藥劑之成本，導致製作成本難以降低。
再者，機械研磨製程並未將該矽板體10薄化至所需厚度h’，故於進行CMP製程時，該導電矽穿孔101之銅離子會滲入該矽板體10中，但由於該矽板體10為半導體材，所以各該導電矽穿孔101之間會產生橋接或漏電等問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種基板結構，係包括：基板本體，係具有相對之第一表面與第二表面；複數導電柱，係形成於該基板本體之第一表面上並電性連接該基板本體；以及介電層，係形成於該基板本體之第一表面上，以包覆該些導電柱，且令該些導電柱外露於該介電層。
本發明亦提供一種電子封裝件，係包括：基板本體，係具有相對之第一表面與第二表面；複數導電柱，係形成於該基板本體之第一表面上並電性連接該基板本體；介電層，係形成於該基板本體之第一表面上，以包覆該些導電柱，且令該些導電柱外露於該介電層；至少一電子元件，係設於該基板本體之第二表面上，使該電子元件電性連接該基板本體；以及封裝材，係形成於該基板本體之第二表面上，以令該封裝材包覆該電子元件。
本發明又提供一種電子封裝件之製法，係包括：形成複數導電柱於承載件中；形成基板本體於該承載件上，且該基板本體電性連接該導電柱；設置至少一電子元件於該基板本體上，使該電子元件電性連接該基板本體；形成封裝材於該基板本體上，以令該封裝材包覆該電子元件；移除該承載件，使該導電柱凸出該基板本體；以及形成介電層於該基板本體上，以包覆該些導電柱，且使該導電柱外 露於該介電層。
前述之製法中，該承載件係為絕緣板、金屬板或半導體板材。
前述之製法中，移除該承載件之製程係包括：形成暫時性載具於該封裝材上；以研磨製程部分該承載件；以及蝕刻剩餘的承載件。復包括於形成該介電層後，移除該暫時性載具。例如，該暫時性載具係為具膠材之玻璃，該膠材之厚度為10um；或者，該暫時性載具係為膠片，其厚度為10um。
前述之電子封裝件及其製法與基板結構中，該導電柱之端面與該介電層之表面齊平。
前述之電子封裝件及其製法與基板結構中，該導電柱之長寬比係為1至5之間。
前述之電子封裝件及其製法與基板結構中，復包括形成複數外接墊於該介電層上，使該外接墊電性連接該導電柱。又包括形成複數導電元件於該外接墊上。
由上可知，本發明之電子封裝件及其製法與基板結構，藉由縮小該導電柱之長寬比，使產品達到輕、薄、短、小之需求，且能提高產量，並降低製作成本。
再者，藉由該介電層取代習知矽板體，故無需製作習知導電矽穿孔，因而大幅降低製程難度及製作成本。
1,2‧‧‧電子封裝件
1a‧‧‧矽中介板
10‧‧‧矽板體
10a‧‧‧置晶側
10b,10b’‧‧‧轉接側
100‧‧‧開孔
101‧‧‧導電矽穿孔
102‧‧‧絕緣材
11‧‧‧介電層
12‧‧‧線路層
120‧‧‧導電盲孔
13,15,26,32‧‧‧絕緣保護層
14,25‧‧‧第一導電元件
16,31‧‧‧第二導電元件
160,250‧‧‧凸塊底下金屬層
17,27‧‧‧電子元件
171,191‧‧‧底膠
18,28‧‧‧封裝材
19‧‧‧封裝基板
190‧‧‧電性接觸墊
192‧‧‧銲球
2a‧‧‧基板結構
2b‧‧‧基板本體
2c‧‧‧中介部
20‧‧‧承載件
200‧‧‧導電柱
200a‧‧‧上端面
200b‧‧‧下端面
201‧‧‧絕緣層
21‧‧‧第一介電層
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧第一子層
22‧‧‧第一線路層
220‧‧‧第一電性接觸墊
221‧‧‧第一導電盲孔
23‧‧‧第二介電層
230‧‧‧第二子層
24‧‧‧第二線路層
240‧‧‧第二電性接觸墊
241‧‧‧第二導電盲孔
260‧‧‧開孔
270‧‧‧導電凸塊
29‧‧‧第三介電層
30‧‧‧外接墊
40,40’‧‧‧暫時性載具
400‧‧‧膠材
h,h’,h”,t,t’,t”,R‧‧‧厚度
a,d‧‧‧深度
w‧‧‧寬度
S‧‧‧切割路徑
第1A至1F圖係為習知電子封裝件之製法的剖面示意圖；其中，第1C’圖係為第1C圖之局部放大圖； 第2A至2H圖係為本發明之電子封裝件之製法的剖面示意圖；其中，第2G’圖係為第2G圖之另一態樣；以及第3圖係為第2H圖之後續製程的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、“第三”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一承載件20，且自其表面向內延伸形成有複數導電柱200。
於本實施例中，該承載件20係為絕緣板、金屬板、或如矽材、玻璃等之半導體板材，且該導電柱200係為金屬 柱，如銅柱。
再者，以該承載件20係為半導體板材為例，於製作該導電柱200時，先於該承載件20之表面上形成複數通孔，再形成一絕緣層201於該承載件20與該通孔之孔壁上，之後將導電材(如銅材)填入該通孔中，以令該導電材形成該導電柱200，且經由整平製程，使該導電柱200之上端面200a齊平該絕緣層201之表面。
又，可依需求採用不同之製程製作該導電柱200，並不限於上述。
如第2B圖所示，形成一第一介電層21於該承載件20之表面上。
於本實施例中，該第一介電層21係結合於該導電柱200之上端面200a與該絕緣層201之表面上。
再者，該第一介電層21係分為兩第一子層210。
如第2C圖所示，形成一第一線路層22於該第一介電層21中，且該第一線路層22具有複數第一電性接觸墊220與複數第一導電盲孔221，以令該第一電性接觸墊220藉由該第一導電盲孔221電性連接該導電柱200。
於本實施例中，該第一電性接觸墊220與該第一導電盲孔221係分別形成於不同之第一子層210中。
再者，單一該第一電性接觸墊220係連接單一該第一導電盲孔221。
如第2D圖所示，形成一第二介電層23於該第一介電層21上，且形成一第二線路層24於該第二介電層23中， 該第二線路層24具有複數第二電性接觸墊240與複數第二導電盲孔241，以令該第二電性接觸墊240藉由該第二導電盲孔241電性連接該第一線路層22。
於本實施例中，該第二介電層23係分為兩第二子層230，且該第二電性接觸墊240與該第二導電盲孔241係分別形成於不同之第二子層230中。
再者，單一該第二電性接觸墊240係連接單一該第二導電盲孔241，且單一該第一電性接觸墊220上係連接兩個第二導電盲孔241。
如第2E圖所示，形成複數第一導電元件25於該些第二電性接觸墊240上。
於本實施例中，先形成一絕緣保護層26於該第二介電層23與該些第二電性接觸墊240上，且該絕緣保護層26外露該些第二電性接觸墊240，再形成該些第一導電元件25於該些第二電性接觸墊240上。
再者，該第一導電元件25係含有銲錫材料或銅凸塊，且可選擇性含有凸塊底下金屬層(UBM)250。
又，單一該第一導電元件25係連接兩個第二電性接觸墊240。例如，該絕緣保護層26形成複數開孔260，且令兩個第二電性接觸墊240外露於單一開孔260中，再將該第一導電元件25形成於該開孔260中。
另外，該第一介電層21、第一線路層22、第二介電層23、第二線路層24與第一導電元件25可構成基板本體2b，且該絕緣保護層26可選擇性視為該基板本體2b之一部分。
如第2F圖所示，設置至少一電子元件27於該第一導電元件25上，使該電子元件27電性連接該第二線路層24。接著，形成封裝材28於該絕緣保護層26上，以令該封裝材28包覆該電子元件27。
於本實施例中，該電子元件27係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，該電子元件27係以複數導電凸塊270結合該第一導電元件25，其中，單一該導電凸塊270連接單一該第一導電元件25。
又，該封裝材28係為如環氧樹脂(epoxy)之封裝膠體或介電材。
如第2G圖所示，移除該承載件20，以外露該絕緣層201，且使該導電柱200凸出該第一介電層21。
於本實施例中，係先於該封裝材28上形成暫時性(Temporary)載具40,40’，如第2G及2G’圖所示，再以研磨製程(機械研磨配合CMP)薄化該承載件20，使其厚度R剩約25um(如第2F圖所示)，之後濕蝕刻厚度R約25um的承載件20。
再者，該暫時性載具40係為具膠材400之玻璃，如第2G圖所示；或如第2G’圖所示，該暫時性載具40’係為研磨用之膠片(Backside Grinding Tape)，其中，該膠材400之厚度t’或該暫時性載具40’(即膠片)之厚度t”約為10um，使其TTV約為1um。
又，該承載件20之厚度R可研磨至25um以下，故該導電柱200之深度a可為10um(如第2F圖所示)，使該導電柱200之深寬比為2，如10um/5um(如第2F圖所示，即深度a為10um，寬度w為5um)。
因此，本發明之製法可利用塗佈薄膠之方式改善TTV(即縮小TTV)，該承載件20於研磨時不會有碎裂風險(crack risk)，且因TTV極小(約為1um)，故於研磨製程後，該承載件20之厚度R可薄化至25um以下，使後續濕蝕刻僅需移除該承載件20之厚度約25um，即可完全移除該承載件20，因而蝕刻時間大幅縮短，並大幅降低蝕刻藥液成本。
再者，該導電柱200之長寬比(或深寬比)可依需求設計為1至5之間。
如第2H圖所示，形成一第三介電層29於該絕緣層201上，以包覆該導電柱200，再經由整平製程，使該導電柱200之下端面200b外露於該第三介電層29，使該第三介電層29與該導電柱200作為中介部2c，且該絕緣層201可選擇性視為該中介部2c之一部分。最後，移除該暫時性載具40，以製成本發明之電子封裝件2。
於本實施例中，該第三介電層29係為感光介質、聚醯亞胺(polyimide，簡稱PI)或聚對二唑苯(Polybenzoxazole，簡稱PBO)。
再者，該整平製程係將該導電柱200之下端面200b上之絕緣層201移除，且令該導電柱200之下端面200b、該 第三介電層29之表面與該絕緣層201之表面相互齊平。
因此，本發明之製法藉由完全移除該承載件20，再形成該第三介電層29，並研磨該第三介電層29以外露出該導電柱200，即使該導電柱200之銅離子滲入該第三介電層29中，且由於該第三介電層29為絕緣體，故各該導電柱200之間不會有橋接或漏電等問題。
再者，於後續製程中，如第3圖所示，形成複數外接墊30於該第三介電層29上，並使該外接墊30電性連接該導電柱200，再形成複數如銲球之第二導電元件31於該外接墊30上，以供接置於一如封裝基板或電路板之電子裝置(圖略)上。
於本實施例中，先形成另一絕緣保護層32於該第三介電層29與該外接墊30上，且該絕緣保護層32外露該些外接墊30之部分表面，再形成該些第二導電元件31於該些外接墊30上。
再者，單一該外接墊30係結合兩該導電柱200，使該第二導電元件31電性連接該導電柱200。
本發明之製法中，可製作出深寬比較小之導電柱200，如10(um)/5(um)，故可使終端產品達到輕、薄、短、小之需求。
再者，由於該導電柱200之深度a變短，故蝕刻該通孔(如第2A圖之製程)之時間縮短，而可提高產量(Throughput)，且可節省化學藥劑費用支出。
又，本發明之製法可製作出深寬比較小之導電柱 200，故相較於習知技術，移除該承載件20之時程較短，且能減少移除製程中之化學藥液之消耗，而能降低製造成本。
另外，本發明之製法係以第三介電層29取代習知矽板體，故可使終端產品達到輕、薄、短、小之需求，且無需以習知深寬比的製程製作該導電柱200，因而大幅降低製程難度及製作成本。
本發明係提供一種基板結構2a，係包括：一基板本體2b、複數導電柱200以及第三介電層29。
所述之基板本體2b係具有相對之第一表面21a與第二表面21b。
所述之導電柱200係形成於該基板本體2b之第一表面21a上並電性連接該些第一導電盲孔221，其中，該導電柱200之長寬比係為1至5之間。。
所述之第三介電層29係形成於該基板本體2b之第一表面21a上以包覆該些導電柱200，且令該些導電柱200之下端面200b外露於該第三介電層29。
於一實施例中，該導電柱200之下端面200b與該第三介電層29之表面齊平。
於一實施例中，所述之基板結構2a復包括形成於該第三介電層29上並電性連接該些導電柱200之複數外接墊30，且該基板結構2a復包括形成於該些外接墊30上之第二導電元件31。
本發明亦提供一種電子封裝件2，係包括：該基板結 構2a、一電子元件27以及封裝材28。
所述之電子元件27係設於該基板本體2b之第二表面21b上，使該電子元件27藉由該些第一導電元件25電性連接該第二線路層24。
所述之封裝材28係形成於該基板本體2b之第二表面21b上，以令該封裝材28包覆該電子元件27。
綜上所述，本發明之電子封裝件及其製法與基板結構，係藉由縮小該導電柱之長寬比，使產品達到輕、薄、短、小之需求，且能提高產量，並降低製作成本。
再者，藉由該第三介電層取代習知矽板體，使終端產品達到輕、薄、短、小之需求，且大幅降低製作成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
2a‧‧‧基板結構
2b‧‧‧基板本體
2c‧‧‧中介部
200‧‧‧導電柱
200b‧‧‧下端面
201‧‧‧絕緣層
21a‧‧‧第一表面
21b‧‧‧第二表面
27‧‧‧電子元件
28‧‧‧封裝材
29‧‧‧第三介電層

Claims (18)

  1. 一種電子封裝件，係包括：基板本體，係具有相對之第一表面與第二表面；複數導電柱，係形成於該基板本體之第一表面上並電性連接該基板本體，該導電柱之長寬比係為1至5之間；介電層，係形成於該基板本體之第一表面上，以包覆該些導電柱，且令該些導電柱外露於該介電層；至少一電子元件，係設於該基板本體之第二表面上，使該電子元件電性連接該基板本體；以及封裝材，係形成於該基板本體之第二表面上，以令該封裝材包覆該電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該導電柱之端面與該介電層之表面齊平。
  3. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該介電層上並電性連接該些導電柱之複數外接墊。
  4. 如申請專利範圍第3項所述之電子封裝件，復包括形成於該些外接墊上之導電元件。
  5. 一種電子封裝件之製法，係包括：形成複數導電柱於承載件中；形成基板本體於該承載件上，且令該基板本體電性連接該導電柱；設置至少一電子元件於該基板本體上，使該電子 元件電性連接該基板本體；形成封裝材於該基板本體上，以令該封裝材包覆該電子元件；移除該承載件，使該導電柱凸出該基板本體；以及形成介電層於該基板本體上，以包覆該些導電柱，且使該導電柱外露於該介電層。
  6. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該承載件係為絕緣板、金屬板或半導體板材。
  7. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該導電柱之端面與該介電層之表面齊平。
  8. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該導電柱之長寬比係為1至5之間。
  9. 如申請專利範圍第5項所述之電子封裝件之製法，其中，移除該承載件之製程係包括：形成暫時性載具於該封裝材上；以研磨製程部分該承載件；以及蝕刻剩餘的承載件。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，復包括於形成該介電層後，移除該暫時性載具。
  11. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該暫時性載具係為具膠材之玻璃，該膠材之厚度為10um。
  12. 如申請專利範圍第9項所述之電子封裝件之製法，其 中，該暫時性載具係為膠片，其厚度為10um。
  13. 如申請專利範圍第5項所述之電子封裝件之製法，復包括形成複數外接墊於該介電層上，使該外接墊電性連接該導電柱。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，復包括形成複數導電元件於該外接墊上。
  15. 一種基板結構，係包括：基板本體，係具有相對之第一表面與第二表面；複數導電柱，係形成於該基板本體之第一表面上並電性連接該基板本體，該導電柱之長寬比係為1至5之間；以及介電層，係形成於該基板本體之第一表面上，以包覆該些導電柱，且該些導電柱外露於該介電層。
  16. 如申請專利範圍第15項所述之基板結構，其中，該導電柱之端面與該介電層之表面齊平。
  17. 如申請專利範圍第15項所述之基板結構，復包括形成於該介電層上並電性連接該些導電柱之複數外接墊。
  18. 如申請專利範圍第17項所述之基板結構，復包括形成於該些外接墊上之導電元件。
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