TWI595603B - 封裝堆疊結構 - Google Patents

封裝堆疊結構 Download PDF

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TWI595603B
TWI595603B TW105136595A TW105136595A TWI595603B TW I595603 B TWI595603 B TW I595603B TW 105136595 A TW105136595 A TW 105136595A TW 105136595 A TW105136595 A TW 105136595A TW I595603 B TWI595603 B TW I595603B
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substrate
stack structure
hole
package stack
package
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TW105136595A
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TW201818510A (zh
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林長甫
姚進財
余國華
黃富堂
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矽品精密工業股份有限公司
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Priority to TW105136595A priority Critical patent/TWI595603B/zh
Priority to CN201611011487.9A priority patent/CN108074881B/zh
Priority to US15/434,824 priority patent/US20180130774A1/en
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Publication of TWI595603B publication Critical patent/TWI595603B/zh
Publication of TW201818510A publication Critical patent/TW201818510A/zh

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Description

封裝堆疊結構
本發明係有關一種封裝結構，尤指一種封裝堆疊結構。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂發展出堆疊複數封裝結構以形成封裝堆疊結構(Package on Package，簡稱POP)之技術，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於各種輕薄型電子產品。
第1圖係為習知封裝堆疊結構1之剖面示意圖。如第1圖所示，該封裝堆疊結構1係藉由銲錫球13堆疊封裝基板11及中介基板(interposer)12，其中，該封裝基板11上側設有半導體元件10，而下側設有用以接置電子裝置(如電路板，圖略)之銲球17，並於該封裝基板11與該中介基板12之間形成封裝膠體14，以包覆該半導體元件10與銲錫球13。
惟，習知封裝堆疊結構1中，該中介基板12之兩側具有防銲層123，於經過多道製程後，該防銲層123容易發生白化，使得該封裝膠體14與該中介基板12之間容易脫層(delamination)。
另外，於形成該封裝膠體14時，空氣容易殘留於該封裝基板11與該中介基板12之間，因而容易於該封裝膠體14內產生空洞(void)，導致良率降低。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種封裝堆疊結構，係包括：第一基板；第二基板，係具有相對之第一表面及第二表面，使該第二基板以其第一表面藉由複數導電元件疊設於該第一基板上，其中，該第二基板具有至少一連通該第一表面與第二表面之穿孔；以及封裝層，係形成於該第二基板與該第一基板之間及該穿孔中。
前述之封裝堆疊結構中，該穿孔之寬度係至多為50微米，例如，該穿孔之寬度係為10至25微米。
前述之封裝堆疊結構中，該第二基板之第一表面與第二表面上具有絕緣保護層，且該穿孔延伸貫穿該絕緣保護層，亦即該絕緣保護層形成有開口，且該開口連通至該穿孔，其中，該開口之寬度大於該穿孔之寬度。例如，該開口之寬度係至多為100微米，且該穿孔及該開口之縱剖面呈T形、I形或Ⅱ形。
前述之封裝堆疊結構中，復包括設於該第一基板上並電性連接該第一基板之電子元件。該穿孔之位置係對應該電子元件之位置，例如，該穿孔設於該第二基板之位置係對應該電子元件投影至該第二基板之範圍內，較佳地，該穿孔設於該第二基板之位置係對應該電子元件投影至該第二基板之角落處。
前述之封裝堆疊結構中，復包括設於該第二基板上並電性連接該第二基板之電子元件。
由上可知，本發明之封裝堆疊結構，主要藉由該第二基板形成有該穿孔，以於形成該封裝層時，供該封裝層之材料流入，藉以增加該封裝層與該第二基板的接觸面積，而增加兩者之結合力，尤其是該穿孔延伸至該絕緣保護層之開口的寬度大於穿孔之寬度，使該封裝層填充於該穿孔及該開口時，得以產生鎖固(lock)之效果，避免發生脫層問題。
再者，該穿孔可作為模壓排氣孔，以於形成該封裝層時，該封裝層可經由該穿孔流至該第二基板之第二表面，因而能排擠出氣體，故相較於習知技術，該封裝堆疊結構能避免孔洞之發生。
1,2‧‧‧封裝堆疊結構
10‧‧‧半導體元件
11‧‧‧封裝基板
12‧‧‧中介基板
123‧‧‧防銲層
13‧‧‧銲錫球
14‧‧‧封裝膠體
17‧‧‧銲球
20,25‧‧‧電子元件
200,250‧‧‧銲錫凸塊
21‧‧‧第一基板
210‧‧‧銲墊
22‧‧‧第二基板
22a‧‧‧第一表面
22b‧‧‧第二表面
220‧‧‧穿孔
221‧‧‧電性接觸墊
222‧‧‧外接墊
223‧‧‧絕緣保護層
223a‧‧‧開口
23‧‧‧導電元件
24‧‧‧封裝層
26‧‧‧底膠
D‧‧‧寬度
R‧‧‧擴大寬度
第1圖係為習知封裝堆疊結構之剖視示意圖；第2圖係為本發明封裝堆疊結構之剖視示意圖；第3A至3D圖係為對應第2圖之穿孔之不同實施例之局部放大剖視圖；以及 第4A至4C圖係為對應第2圖之不同實施例之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明封裝堆疊結構2之剖視示意圖。如第2圖所示，該封裝堆疊結構2係包括一第一基板21、一第二基板22、複數導電元件23以及封裝層24。
所述之第一基板21係為封裝基板，其上設有至少一電子元件20。
於本實施例中，該第一基板21之構造可為核心式(core)或無核心式(coreless)之結構，其具有至少一線路層，且該 線路層包含有複數銲墊210。
再者，該電子元件20係為主動元件、被動元件或其組合，該主動元件係例如晶片，而該被動元件係例如電阻、電容及電感。具體地，該電子元件20係藉由複數銲錫凸塊200設於部分該銲墊210上，即該電子元件20以覆晶方式電性連接該第一基板21。應可理解地，該電子元件20亦可以打線方式電性連接該銲墊210。
所述之第二基板22係具有相對之第一表面22a及第二表面22b，且該第二基板22具有至少一連通該第一表面22a與第二表面22b之穿孔220。
於本實施例中，該第二基板22之構造可為核心式或無核心式之結構，其具有至少一線路層，且該線路層包含有複數位於該第一表面22a上之電性接觸墊221及複數位於該第二表面22b上之外接墊222，並於該第一及第二表面22a,22b上形成有例如防銲層之絕緣保護層223，且令該些電性接觸墊221及外接墊222外露於該絕緣保護層223。
再者，該穿孔220係以雷射、機械鑽孔或其它方式(如噴砂、銼、切割、銑、研磨、水刀或蝕刻等)形成，且該穿孔220之寬度D為50μm以下，較佳為10至25μm。
又，該穿孔220之形狀可依需求設計，例如，該穿孔220可延伸貫穿該絕緣保護層223，而於該絕緣保護層223中形成有對應之開口223a，亦即該絕緣保護層223之開口223a連通至該穿孔220。具體地，如第2圖所示，該穿孔220延伸至該些絕緣保護層223，且其寬度D保持一致(即 該穿孔220與該開口223a之寬度均相同)；或者，如第3A及3B圖所示，該穿孔220延伸至其中一絕緣保護層223之部分係擴大其寬度，以令該穿孔220及該開口223a之縱剖面呈「T」形，亦即該絕緣保護層223之開口223a之寬度R大於穿孔220之寬度D。或者，如第3C圖所示，該穿孔220延伸至兩絕緣保護層223之部分均擴大其寬度，例如該穿孔220及該開口223a之縱剖面呈「I」形。亦或，如第3D圖所示，多個(2個)穿孔220延伸至該絕緣保護層223之部分係相互連通，例如該多個穿孔220及該開口223a之縱剖面呈「Ⅱ」形。前述之該穿孔220延伸至該絕緣保護層223之擴大寬度R較佳為100μm以下。
另外，佈設於該第二基板22之穿孔220位置主要係對應設置於該第一基板21上之該電子元件20之相對位置。如第4A至4C圖所示，該穿孔220之位置係位於該電子元件20對應該第二基板22之投影範圍內，其中，因於該電子元件20之四個角落處的應力較大，較容易發生脫層，故該穿孔220之位置以對應該電子元件20之四個角落較佳，且該穿孔220之位置亦可對應該電子元件20之中心位置(如第4B圖所示)，亦或其它位置，另該穿孔220之數量可為一個或多個，且該穿孔220延伸至該絕緣保護層223之開口223a之形狀可為方形(如第4A及4B圖所示)或圓弧狀(如第4C圖所示)。應可理解地，該穿孔220之位置、數量及形狀等可依需求設計，並不限於上述。
所述之導電元件23係結合於該第二基板22之第一表 面22a與該第一基板21之間，使該第二基板22疊設於該第一基板21上，且該導電元件23電性連接該第二基板22之電性接觸墊221及該第一基板21之銲墊210。
於本實施例中，該導電元件23係為銲球或電鍍銅柱之金屬柱。
所述之封裝層24係形成於該第二基板22之第一表面22a與該第一基板21之間及該穿孔220中，且包覆該些導電元件23與該電子元件20。
於本實施例中，形成該封裝層24之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)。
另一方面，該第二基板22之第二表面22b上設有至少一電子元件25，且該電子元件25係可選自封裝件、主動元件、被動元件或其組合，該主動元件係例如晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該電子元件25係以覆晶方式(如藉由銲錫凸塊250)電性連接該外接墊222，並形成底膠26於該電子元件25與該第二基板22之第二表面22b(或絕緣保護層223)之間。應可理解地，該電子元件25亦可以打線方式電性連接該外接墊222。
綜上所述，本發明之封裝堆疊結構2係藉由該穿孔220之設計，供該封裝層24之材料流入，藉以增加該封裝層24與該第二基板22的接觸面積，尤其是該穿孔220延伸至該絕緣保護層223之開口223a的寬度大於該穿孔220之 寬度，使該封裝層24填充於該穿孔220及該開口223a時，得以產生鎖固(lock)之效果，而增加封裝層24與第二基板22之結合力，有效避免脫層的發生。
再者，該穿孔220可作為模壓排氣孔，以於形成該封裝層24時，該封裝層24可經由該穿孔220流至該第二基板22之第二表面22b，因而能排擠出氣體，故能避免孔洞之發生。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝堆疊結構
20,25‧‧‧電子元件
200,250‧‧‧銲錫凸塊
21‧‧‧第一基板
210‧‧‧銲墊
22‧‧‧第二基板
22a‧‧‧第一表面
22b‧‧‧第二表面
220‧‧‧穿孔
221‧‧‧電性接觸墊
222‧‧‧外接墊
223‧‧‧絕緣保護層
223a‧‧‧開口
23‧‧‧導電元件
24‧‧‧封裝層
26‧‧‧底膠
D‧‧‧寬度

Claims (11)

  1. 一種封裝堆疊結構，係包括：第一基板；第二基板，係具有相對之第一表面及第二表面，使該第二基板以其第一表面藉由複數導電元件疊設於該第一基板上，其中，該第二基板具有至少一連通該第一表面與第二表面之穿孔，且該第二基板之第一表面與第二表面上具有絕緣保護層，該穿孔延伸貫穿該絕緣保護層；以及封裝層，係形成於該第二基板與該第一基板之間及該穿孔中。
  2. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該穿孔之寬度係至多為50微米。
  3. 如申請專利範圍第2項所述之封裝堆疊結構，其中，該穿孔之寬度係為10至25微米。
  4. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該絕緣保護層形成有開口，且該開口連通至該穿孔。
  5. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該開口之寬度大於該穿孔之寬度。
  6. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該開口之寬度係至多為100微米。
  7. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該穿孔及該開口之縱剖面呈T形、I形或Ⅱ形。
  8. 如申請專利範圍第1項所述之封裝堆疊結構，復包括接 置於該第一基板上並電性連接該第一基板之電子元件。
  9. 如申請專利範圍第8項所述之封裝堆疊結構，其中，該穿孔設於該第二基板之位置係對應該電子元件投影至該第二基板之範圍內。
  10. 如申請專利範圍第9項所述之封裝堆疊結構，其中，該穿孔設於該第二基板之位置係對應該電子元件投影至該第二基板之角落處。
  11. 如申請專利範圍第1項所述之封裝堆疊結構，復包括接置於該第二基板上並電性連接該第二基板之電子元件。
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