TWI660476B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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TWI660476B
TWI660476B TW103123899A TW103123899A TWI660476B TW I660476 B TWI660476 B TW I660476B TW 103123899 A TW103123899 A TW 103123899A TW 103123899 A TW103123899 A TW 103123899A TW I660476 B TWI660476 B TW I660476B
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dielectric layer
conductive
opening
carrier
manufacturing
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TW103123899A
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TW201603215A (zh
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白裕呈
林俊賢
邱士超
蕭惟中
孫銘成
沈子傑
陳嘉成
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矽品精密工業股份有限公司
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Priority to TW103123899A priority Critical patent/TWI660476B/zh
Priority to CN201410362830.9A priority patent/CN105321902B/zh
Priority to US14/562,972 priority patent/US20160013123A1/en
Publication of TW201603215A publication Critical patent/TW201603215A/zh
Priority to US15/636,217 priority patent/US20170301658A1/en
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Publication of TWI660476B publication Critical patent/TWI660476B/zh

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Abstract

一種封裝結構之製法，係先提供一具有複數銲墊之承載件，再壓合一介電層於該承載件上，之後形成複數導電柱於該介電層中，最後移除該介電層之部分材質以形成一開口，使該些銲墊外露於該開口，且該些導電柱係位於該開口周圍，藉以達到簡化製程之目的。本發明復提供該封裝結構。

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種能簡化製程之封裝結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂堆加複數封裝件以形成封裝堆疊結構(Package on Package，POP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
一般封裝堆疊結構(PoP)係僅以銲錫球(solder ball)堆疊與電性連接上、下封裝件，但隨著產品尺寸規格與線距越來越小，該些銲錫球之間容易發生橋接(bridge)現象，將影響產品之良率。
於是，遂發展出一種封裝堆疊結構，係以銅柱(Cu pillar)作支撐，以增加隔離(stand off)效果，可避免發 生橋接現象。第1A及1B圖係為習知封裝堆疊結構1之製法之剖面示意圖。
如第1A圖所示，先提供一具有相對之第一及第二表面11a,11b之第一基板11，且於該第一基板11之第一表面11a上形成複數銅柱13。
如第1B圖所示，設置一電子元件15於該第一表面11a上且以覆晶方式電性連接該第一基板11，再疊設一第二基板12於該銅柱13上，之後形成封裝膠體16於該第一基板11之第一表面11a與該第二基板12之間。具體地，該第二基板12藉由複數導電元件17結合該銅柱13，且該導電元件17係由金屬柱170與銲錫材料171構成。
惟，習知封裝堆疊結構1中，該銅柱13係以電鍍形成，致使其尺寸變異不易控制，故容易發生各銅柱13之高度不一致之情況，因而產生接點偏移之問題，致使該些導電元件17與該些銅柱13接觸不良，而造成電性不佳，因而影響產品良率。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種封裝結構，係包括：承載件，係具有複數銲墊；介電層，係具有相對之第一表面與第二表面，該介電層係以其第一表面設於該承載件上，以令該介電層覆蓋該些銲墊，且該介電層之第二表面上具有至少一開口，使該些銲墊外露於該開 口；以及複數導電柱，係形成於該介電層中，且該些導電柱係位於該開口周圍。
本發明復提供一種封裝結構之製法，係包括：提供一具有複數銲墊之承載件、及一具有相對之第一表面與第二表面之介電層；將該介電層藉其第一表面壓合於該承載件上，以令該介電層覆蓋該些銲墊；形成複數導電柱於該介電層中；以及於該介電層之第二表面形成至少一開口，使該些銲墊外露於該開口，且該些導電柱係位於該開口周圍。
前述之製法中，於壓合該介電層與該承載件之前，該介電層之第二表面上具有導電層，以利用該導電層製作該導電柱。
前述之製法中，該導電柱之步驟係先形成貫穿該介電層之複數穿孔，再於該些穿孔中填充導電材料以作為該導電柱。
前述之製法中，復包括設置堆疊件至該介電層之第二表面上，且該堆疊件電性連接該導電柱。例如，該堆疊件係為封裝基板、半導體晶片、中介板或封裝件。
前述之封裝結構及其製法中，該承載件係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。
前述之封裝結構及其製法中，該介電層之第二表面上復具有電性連接該導電柱之線路層。
前述之封裝結構及其製法中，該介電層係為感光介質。例如，形成該開口之製程係使用曝光顯影製程。
另外，前述之封裝結構及其製法中，復包括設置電子元件於該開口中，且該電子元件電性連接該些銲墊。
由上可知，本發明之封裝結構及其製法，主要藉由在該承載件上壓合介電層以製作導電柱，而能增加隔離效果及避免橋接現象。
再者，藉由該些穿孔控制各該導電柱之尺寸，使各該導電柱之高度一致，以避免接點偏移之問題，故相較於習知技術，後續製程之導電元件與該些導電柱不會發生接觸不良或短路之問題，因而能有效提高產品良率。
1‧‧‧封裝堆疊結構
11‧‧‧第一基板
11a,22a‧‧‧第一表面
11b,22b‧‧‧第二表面
12‧‧‧第二基板
13‧‧‧銅柱
15,28‧‧‧電子元件
16‧‧‧封裝膠體
17,291‧‧‧導電元件
170‧‧‧金屬柱
171‧‧‧銲錫材料
2,3‧‧‧封裝結構
21‧‧‧承載件
210‧‧‧銲墊
211‧‧‧電性連接墊
211’‧‧‧線路部
212‧‧‧導電盲孔
213‧‧‧介電部
214‧‧‧金屬層
22‧‧‧介電層
220‧‧‧開口
23‧‧‧導電層
25,25’‧‧‧線路層
26‧‧‧導電柱
260‧‧‧穿孔
27‧‧‧絕緣保護層
281‧‧‧導電凸塊
29‧‧‧堆疊件
30‧‧‧封裝材
A‧‧‧承載區
第1A至1B圖係為習知堆疊式封裝結構之製法的剖視示意圖；以及第2A至2G圖係為本發明之堆疊式封裝結構之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之封裝結構2,3之製法之剖視示意圖。
如第2A圖所示，提供一具有複數銲墊210與複數電性連接墊211之承載件21。
於本實施例中，該承載件21係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。例如，第2A圖所示，該承載件21係為無核心層(coreless)封裝基板，其由複數介電部213、線路部211’與導電盲孔212構成，且於該承載件21下側具有如銅之金屬層214。
再者，該承載件21係定義有一承載區A，使該些銲墊210位於該承載區A內，而該電性連接墊211位於該承載區A外。
如第2B圖所示，壓合一具有導電層23之介電層22於該承載件21上，再以雷射鑽孔方式於對應該電性連接墊211的位置上形成貫穿該介電層22與該導電層23之複數穿孔260。
於本實施例中，該介電層22具有相對之第一表面22a與第二表面22b，且該介電層22以其第一表面22a壓合於該承載件21上，以令該介電層22覆蓋該些銲墊210，且 該導電層23設於該介電層22之第二表面22b上。
再者，該介電層22之材質係為感光介質(photo imageable dielectric，簡稱PID)，且該導電層23係為銅層。
又，藉由將該介電層22與該承載件21以熱壓合直接壓合，使製程簡化。
如第2C圖所示，利用該導電層23，於該介電層22之第二表面22b上製作一線路層25，且於該些穿孔260中形成導電材料以作為導電柱26，且藉由該些導電柱26電性連接該線路層25與該些電性連接墊211。
於本實施例中，該線路層25並未形成於對應該承載區A之第二表面22b上。
再者，利用該承載件21下側之金屬層214製作另一線路層25’。
如第2D圖所示，使用曝光顯影製程，形成一開口220於該介電層22之第二表面22b上，使該些銲墊210外露於該開口220，且該些導電柱26係位於該開口220周圍。
於本實施例中，該承載件21於該承載區A之表面亦外露於該開口220。
如第2E圖所示，可於該介電層22之第二表面22b、該承載件21下側與該線路層25,25’上分別形成一絕緣保護層27，且該些絕緣保護層27係外露出部分該線路層25,25’，供後續製程中接置其它外部元件。
如第2F圖所示，於該開口220內設置至少一電子元件28，且該電子元件28以複數導電凸塊281電性連接該些銲 墊210。
如第2G圖所示，設置一堆疊件29於該線路層25上，以令該堆疊件29疊設於該介電層22之第二表面22b上，且覆蓋該開口220與該電子元件28，以製得本發明之封裝結構3之另一態樣。
於本實施例中，該堆疊件29係為封裝基板、半導體晶片、晶圓、中介板或封裝件，且該堆疊件29係藉由複數如銲錫材料或金屬柱之導電元件291電性結合至該線路層25與該導電柱26。
再者，形成封裝材30於該堆疊件29與承載件21之間，以包覆該些導電凸塊281。
本發明復提供一種封裝結構2，係包括：一承載件21、一介電層22以及複數導電柱26。
所述之承載件21係為封裝基板，其具有複數銲墊210。
所述之介電層22係感光介質，其具有相對之第一表面22a與第二表面22b，該介電層22係以其第一表面22a設於該承載件21上，以令該介電層22覆蓋該些銲墊210，且該介電層22之第二表面22b上具有開口220，使該些銲墊210外露於該開口220，又該介電層22之第二表面22b上復具有電性連接該導電柱26之線路層25。
所述之導電柱26係設於該介電層22中，且該些導電柱26係位於該開口220周圍。
於一實施例中，所述之封裝結構2復包括電子元件28，係設於該開口220中，且該電子元件28電性連接該些 銲墊210。
綜上所述，本發明封裝結構2及其製法中，藉由在承載件21上形成一介電層22，使該導電柱26嵌入該介電層22中，再於該介電層22上接置該堆疊件29，藉以增加隔離(stand off)各該導電柱26之效果、及避免各該導電柱26之間發生橋接現象。
再者，藉由該些穿孔260控制各該導電柱26之尺寸，使各該導電柱26之高度一致，以令該些導電元件291之接置處高度一致，因而能避免接點偏移之問題，故該些導電元件291與該些導電柱26不會發生接觸不良或短路(short)之問題，因而能有效提高產品良率。
又，藉由該介電層22具有感光性，故能使用曝光顯影製程形成該開口220，以簡化製程。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (12)

  1. 一種封裝結構，係包括：承載件，係具有複數銲墊；介電層，係具有相對之第一表面與第二表面，該介電層係以其第一表面設於該承載件上，且該介電層之第二表面上具有至少一開口，使該些銲墊外露於該開口，並形成有貫穿該介電層之複數穿孔，其中，該介電層係感光介質；以及複數導電柱，係形成於該介電層之穿孔中並自該第一表面一體延伸至該第二表面，且該些導電柱係位於該開口周圍。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該承載件係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該介電層之第二表面上復具有電性連接該導電柱之線路層。
  4. 如申請專利範圍第1項所述之封裝結構，復包括電子元件，係設於該開口中，且該電子元件電性連接該些銲墊。
  5. 一種封裝結構之製法，係包括：提供一具有複數銲墊之承載件、及一具有相對之第一表面與第二表面之介電層；將該介電層藉其第一表面壓合於該承載件上，以令該介電層覆蓋該些銲墊，且形成有貫穿該介電層之複數穿孔，其中，該介電層係感光介質；於該些穿孔中填充導電材料以形成複數導電柱於該介電層之穿孔中，且該導電柱係自該第一表面一體延伸至該第二表面；以及於該介電層之第二表面形成至少一開口，使該些銲墊外露於該開口，且該些導電柱係位於該開口周圍。
  6. 如申請專利範圍第5項所述之封裝結構之製法，其中，該承載件係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。
  7. 如申請專利範圍第5項所述之封裝結構之製法，其中，於壓合該介電層與該承載件之前，該介電層之第二表面上具有導電層，以利用該導電層製作該導電柱。
  8. 如申請專利範圍第5項所述之封裝結構之製法，其中，該介電層之第二表面上復具有電性連接該導電柱之線路層。
  9. 如申請專利範圍第5項所述之封裝結構之製法，其中，形成該開口之製程係使用曝光顯影製程。
  10. 如申請專利範圍第5項所述之封裝結構之製法，復包括設置電子元件於該開口中，且該電子元件電性連接該些銲墊。
  11. 如申請專利範圍第5項所述之封裝結構之製法，復包括設置堆疊件至該介電層之第二表面上，且該堆疊件電性連接該導電柱。
  12. 如申請專利範圍第11項所述之封裝結構之製法，其中，該堆疊件係為封裝基板、半導體晶片、中介板或封裝件。
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