CN105321902A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105321902A
CN105321902A CN201410362830.9A CN201410362830A CN105321902A CN 105321902 A CN105321902 A CN 105321902A CN 201410362830 A CN201410362830 A CN 201410362830A CN 105321902 A CN105321902 A CN 105321902A
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dielectric layer
making
encapsulating structure
conductive
opening
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CN105321902B (zh
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白裕呈
林俊贤
邱士超
萧惟中
孙铭成
沈子杰
陈嘉成
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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Abstract

一种封装结构及其制法，该制法，先提供一具有多个焊垫的承载件，再压合一介电层于该承载件上，之后形成多个导电柱于该介电层中，最后移除该介电层的部分材质以形成一开口，使该些焊垫外露于该开口，且该些导电柱位于该开口周围，藉以达到简化制程的目的。本发明还提供该封装结构。

Description

封装结构及其制法
技术领域
本发明有关一种封装结构，尤指一种能简化制程的封装结构及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductordevice)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装件以形成封装堆迭结构(PackageonPackage，POP)，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：记忆体、中央处理器、绘图处理器、影像应用处理器等，藉由堆迭设计达到系统的整合，适合应用于轻薄型各种电子产品。
一般封装堆迭结构(PoP)仅以焊锡球(solderball)堆迭与电性连接上、下封装件，但随着产品尺寸规格与线距越来越小，该些焊锡球之间容易发生桥接(bridge)现象，将影响产品的良率。
于是，遂发展出一种封装堆迭结构，其以铜柱(Cupillar)作支撑，以增加隔离(standoff)效果，可避免发生桥接现象。图1A及图1B为现有封装堆迭结构1的制法的剖面示意图。
如图1A所示，先提供一具有相对的第一及第二表面11a,11b的第一基板11，且于该第一基板11的第一表面11a上形成多个铜柱13。
如图1B所示，设置一电子元件15于该第一表面11a上且以覆晶方式电性连接该第一基板11，再迭设一第二基板12于该铜柱13上，之后形成封装胶体16于该第一基板11的第一表面11a与该第二基板12之间。具体地，该第二基板12藉由多个导电元件17结合该铜柱13，且该导电元件17由金属柱170与焊锡材料171构成。
然而，现有封装堆迭结构1中，该铜柱13以电镀形成，致使其尺寸变异不易控制，故容易发生各铜柱13的高度不一致的情况，因而产生接点偏移的问题，致使该些导电元件17与该些铜柱13接触不良，而造成电性不佳，因而影响产品良率。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种封装结构及其制法，以达到简化制程的目的。本发明还提供该封装结构。
本发明的封装结构，包括：承载件，其具有多个焊垫；介电层，其具有相对的第一表面与第二表面，该介电层以其第一表面设于该承载件上，以令该介电层覆盖该些焊垫，且该介电层的第二表面上具有至少一开口，使该些焊垫外露于该开口；以及多个导电柱，其形成于该介电层中，且该些导电柱位于该开口周围。
本发明还提供一种封装结构的制法，包括：提供一具有多个焊垫的承载件、及一具有相对的第一表面与第二表面的介电层；将该介电层藉其第一表面压合于该承载件上，以令该介电层覆盖该些焊垫；形成多个导电柱于该介电层中；以及于该介电层的第二表面形成至少一开口，使该些焊垫外露于该开口，且该些导电柱位于该开口周围。
前述的制法中，于压合该介电层与该承载件之前，该介电层的第二表面上具有导电层，以利用该导电层制作该导电柱。
前述的制法中，该导电柱的步骤先形成贯穿该介电层的多个穿孔，再于该些穿孔中填充导电材料以作为该导电柱。
前述的制法中，还包括设置堆迭件至该介电层的第二表面上，且该堆迭件电性连接该导电柱。例如，该堆迭件为封装基板、半导体晶片、中介板或封装件。
前述的封装结构及其制法中，该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
前述的封装结构及其制法中，该介电层的第二表面上还具有电性连接该导电柱的线路层。
前述的封装结构及其制法中，该介电层为感光介质。例如，形成该开口的制程为使用曝光显影制程。
另外，前述的封装结构及其制法中，还包括设置电子元件于该开口中，且该电子元件电性连接该些焊垫。
由上可知，本发明的封装结构及其制法，主要藉由在该承载件上压合介电层以制作导电柱，而能增加隔离效果及避免桥接现象。
此外，藉由该些穿孔控制各该导电柱的尺寸，使各该导电柱的高度一致，以避免接点偏移的问题，故相较于现有技术，后续制程的导电元件与该些导电柱不会发生接触不良或短路的问题，因而能有效提高产品良率。
附图说明
图1A至图1B为现有堆迭式封装结构的制法的剖视示意图；以及
图2A至图2G为本发明的堆迭式封装结构的制法的剖视示意图。
符号说明
1封装堆迭结构
11第一基板
11a,22a第一表面
11b,22b第二表面
12第二基板
13铜柱
15,28电子元件
16封装胶体
17,291导电元件
170金属柱
171焊锡材料
2,3封装结构
21承载件
210焊垫
211电性连接垫
211’线路部
212导电盲孔
213介电部
214金属层
22介电层
220开口
23导电层
25,25’线路层
26导电柱
260穿孔
27绝缘保护层
281导电凸块
29堆迭件
30封装材
A承载区。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的封装结构2,3的制法的剖视示意图。
如图2A所示，提供一具有多个焊垫210与多个电性连接垫211的承载件21。
于本实施例中，该承载件21为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。例如，图2A所示，该承载件21为无核心层(coreless)封装基板，其由多个介电部213、线路部211’与导电盲孔212构成，且于该承载件21下侧具有如铜的金属层214。
此外，该承载件21定义有一承载区A，使该些焊垫210位于该承载区A内，而该电性连接垫211位于该承载区A外。
如图2B所示，压合一具有导电层23的介电层22于该承载件21上，再以激光钻孔方式于对应该电性连接垫211的位置上形成贯穿该介电层22与该导电层23的多个穿孔260。
于本实施例中，该介电层22具有相对的第一表面22a与第二表面22b，且该介电层22以其第一表面22a压合于该承载件21上，以令该介电层22覆盖该些焊垫210，且该导电层23设于该介电层22的第二表面22b上。
此外，该介电层22的材质为感光介质(photoimageabledielectric,简称PID)，且该导电层23为铜层。
又，藉由将该介电层22与该承载件21以热压合直接压合，使制程简化。
如图2C所示，利用该导电层23，于该介电层22的第二表面22b上制作一线路层25，且于该些穿孔260中形成导电材料以作为导电柱26，且藉由该些导电柱26电性连接该线路层25与该些电性连接垫211。
于本实施例中，该线路层25并未形成于对应该承载区A的第二表面22b上。
此外，利用该承载件21下侧的金属层214制作另一线路层25’。
如图2D所示，使用曝光显影制程，形成一开口220于该介电层22的第二表面22b上，使该些焊垫210外露于该开口220，且该些导电柱26位于该开口220周围。
于本实施例中，该承载件21于该承载区A的表面亦外露于该开口220。
如图2E所示，可于该介电层22的第二表面22b、该承载件21下侧与该线路层25,25’上分别形成一绝缘保护层27，且该些绝缘保护层27外露出部分该线路层25,25’，供后续制程中接置其它外部元件。
如图2F所示，于该开口220内设置至少一电子元件28，且该电子元件28以多个导电凸块281电性连接该些焊垫210。
如图2G所示，设置一堆迭件29于该线路层25上，以令该堆迭件29迭设于该介电层22的第二表面22b上，且覆盖该开口220与该电子元件28，以制得本发明的封装结构3的另一实施例。
于本实施例中，该堆迭件29为封装基板、半导体晶片、晶圆、中介板或封装件，且该堆迭件29藉由多个如焊锡材料或金属柱的导电元件291电性结合至该线路层25与该导电柱26。
此外，形成封装材30于该堆迭件29与承载件21之间，以包覆该些导电凸块281。
本发明还提供一种封装结构2，包括：一承载件21、一介电层22以及多个导电柱26。
所述的承载件21为封装基板，其具有多个焊垫210。
所述的介电层22为感光介质，其具有相对的第一表面22a与第二表面22b，该介电层22以其第一表面22a设于该承载件21上，以令该介电层22覆盖该些焊垫210，且该介电层22的第二表面22b上具有开口220，使该些焊垫210外露于该开口220，又该介电层22的第二表面22b上还具有电性连接该导电柱26的线路层25。
所述的导电柱26设于该介电层22中，且该些导电柱26位于该开口220周围。
于一实施例中，所述的封装结构2还包括电子元件28，其设于该开口220中，且该电子元件28电性连接该些焊垫210。
综上所述，本发明封装结构2及其制法中，藉由在承载件21上形成一介电层22，使该导电柱26嵌入该介电层22中，再于该介电层22上接置该堆迭件29，藉以增加隔离(standoff)各该导电柱26的效果、及避免各该导电柱26之间发生桥接现象。
此外，藉由该些穿孔260控制各该导电柱26的尺寸，使各该导电柱26的高度一致，以令该些导电元件291的接置处高度一致，因而能避免接点偏移的问题，故该些导电元件291与该些导电柱26不会发生接触不良或短路(short)的问题，因而能有效提高产品良率。
又，藉由该介电层22具有感光性，故能使用曝光显影制程形成该开口220，以简化制程。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种封装结构，包括：
承载件，其具有多个焊垫；
介电层，其具有相对的第一表面与第二表面，该介电层以其第一表面设于该承载件上，以令该介电层覆盖该些焊垫，且该介电层的第二表面上具有至少一开口，使该些焊垫外露于该开口；以及
多个导电柱，其形成于该介电层中，且该些导电柱位于该开口周围。
2.如权利要求1所述的封装结构，其特征为，该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
3.如权利要求1所述的封装结构，其特征为，该介电层的第二表面上还具有电性连接该导电柱的线路层。
4.如权利要求1所述的封装结构，其特征为，该介电层为感光介质。
5.如权利要求1所述的封装结构，其特征为，该封装结构还包括电子元件，其设于该开口中，且该电子元件电性连接该些焊垫。
6.一种封装结构的制法，其包括：
提供一具有多个焊垫的承载件、及一具有相对的第一表面与第二表面的介电层；
将该介电层藉其第一表面压合于该承载件上，以令该介电层覆盖该些焊垫；
形成多个导电柱于该介电层中；以及
于该介电层的第二表面形成至少一开口，使该些焊垫外露于该开口，且该些导电柱位于该开口周围。
7.如权利要求6所述的封装结构的制法，其特征为，该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
8.如权利要求6所述的封装结构的制法，其特征为，于压合该介电层与该承载件之前，该介电层的第二表面上具有导电层，以利用该导电层制作该导电柱。
9.如权利要求6所述的封装结构的制法，其特征为，该导电柱的步骤先形成贯穿该介电层的多个穿孔，再于该些穿孔中填充导电材料以作为该导电柱。
10.如权利要求6所述的封装结构的制法，其特征为，该介电层的第二表面上还具有电性连接该导电柱的线路层。
11.如权利要求6所述的封装结构的制法，其特征为，该介电层为感光介质。
12.如权利要求11所述的封装结构的制法，其特征为，形成该开口的制程使用曝光显影制程。
13.如权利要求6所述的封装结构的制法，其特征为，该制法还包括设置电子元件于该开口中，且该电子元件电性连接该些焊垫。
14.如权利要求6所述的封装结构的制法，其特征为，该制法还包括设置堆迭件至该介电层的第二表面上，且该堆迭件电性连接该导电柱。
15.如权利要求14所述的封装结构的制法，其特征为，该堆迭件为封装基板、半导体晶片、中介板或封装件。
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