CN104576593A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN104576593A
CN104576593A CN201310526773.9A CN201310526773A CN104576593A CN 104576593 A CN104576593 A CN 104576593A CN 201310526773 A CN201310526773 A CN 201310526773A CN 104576593 A CN104576593 A CN 104576593A
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Prior art keywords
substrate
making
stackware
heap
structures according
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Inventor
陈嘉成
孙铭成
沈子杰
洪良易
萧惟中
白裕呈
邱士超
江东昇
张翊峰
王隆源
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN104576593A publication Critical patent/CN104576593A/zh
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Abstract

一种封装结构及其制法，该封装结构包括第一基板、设于该第一基板上且具有开口的增层部、设于该开口中且电性连接该第一基板的电子组件、设于该增层部上的堆栈件、以及设于该增层部与该堆栈件之间的封装胶体。藉由该增层部的设计，以增加隔离效果及避免桥接现象。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构，尤指一种得提升堆栈良率的封装结构。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装件以形成封装堆栈结构(Package on Package，POP)，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子组件，例如：内存、中央处理器、绘图处理器、影像应用处理器等，藉由堆栈设计达到系统的整合，适合应用于轻薄型各种电子产品。
一般封装堆栈结构(PoP)仅以焊锡球(solder ball)堆栈与电性连接上、下封装件，但随着产品尺寸规格与线距越来越小，该些焊锡球之间容易发生桥接(bridge)现象，将影响产品的良率。
于是，遂发展出一种封装堆栈结构，以铜柱(Cu pillar)作支撑，以增加隔离(stand off)效果，可避免发生桥接现象。第1A及1B图为现有封装堆栈结构1的制法的剖面示意图。
如图1A所示，先提供一具有相对的第一及第二表面11a,11b的第一基板11，且于该第一基板11的第一表面11a上形成多个铜柱13。
如图1B所示，设置一电子组件15于该第一表面11a上且以覆晶方式电性连接该第一基板11，再叠设一第二基板12于该铜柱13上，之后形成封装胶体16于该第一基板11的第一表面11a与该第二基板12之间。具体地，该第二基板12藉由多个导电组件17结合该铜柱13，且该导电组件17由金属柱170与焊锡材料171构成。
然而，现有封装堆栈结构1中，该铜柱13以电镀形成，致使其尺寸变异不易控制，所以容易发生各铜柱13的高度不一致的情况，因而产生接点偏移的问题，致使该些导电组件17与该些铜柱13接触不良，而造成电性不佳，因而影响产品良率。
因此，如何克服现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明的主要目的为提供一种封装结构及其制法，以增加隔离效果及避免桥接现象。
本发明的封装结构，包括：第一基板；增层部，其设于该第一基板上并电性连接该第一基板，且该增层部具有开口；至少一电子组件，其设于该开口中，且电性连接该第一基板；堆栈件，其设于该增层部上，以令该堆栈件叠设于该第一基板上；以及封装胶体，其设于该增层部与该堆栈件之间。
本发明还提供一种封装结构的制法，其包括：提供一第一基板，该第一基板上具有增层部，且该增层部具有开口；设置至少一电子组件于该开口中，且该电子组件电性连接该第一基板；以及设置堆栈件于该增层部上，以令该堆栈件叠设于该第一基板上。
前述的制法中，该第一基板的制程包括：提供该第一基板；以及形成该增层部于该第一基板上，且形成该开口于该增层部上，该增层部并电性连接该第一基板。
前述的封装结构及其制法中，该增层部的制程包括：形成至少一介电层于该第一基板上，且形成该开口与多个盲孔于该介电层上；形成多个导电体于该些盲孔中，使该些导电体电性连接该第一基板；及设置该电子组件于该开口中。
依前述技术中，形成该介电层的材质为预浸材，且该介电层先压合于该第一基板上，再形成该开口于该介电层上；或者，该介电层先形成该开口，再压合该介电层于该第一基板上。
依前述技术中，该开口及该些盲孔以激光钻孔方式形成者，而该导电体为金属材且为柱状或凹槽状。
依前述技术中，该堆栈件与该导电体藉由导电组件相结合。
依前述技术中，还包括形成线路层于该介电层上，且该线路层电性连接该些导电体。
前述技术中，还包括形成绝缘保护层于该介电层上，且外露该些导电体，使该封装胶体设于该绝缘保护层与该堆栈件之间。
前述的封装结构及其制法中，该第一基板为线路板。
前述的封装结构及其制法中，该开口外露该第一基板的表面，使该电子组件设于该第一基板的表面上。
前述的封装结构及其制法中，该电子组件为主动组件或被动组件。
前述的封装结构及其制法中，该堆栈件与该增层部藉由多个导电组件相结合。
前述的封装结构及其制法中，该堆栈件为第二基板或封装件，例如，该第二基板为线路板。
另外，前述的制法中，还包括形成封装胶体于该增层部与该堆栈件之间，且前述的封装结构及其制法中，该堆栈件的宽度小于该第一基板的宽度，使该封装胶体包覆该堆栈件。又该封装胶体还设于该第一基板与该堆栈件之间。
由上可知，本发明封装结构及其制法，主要藉由在该第一基板上形成该增层部，以增加隔离效果及避免桥接现象。
此外，藉由该些盲孔控制各该导电体的尺寸，使各该导电体的高度一致，以避免接点偏移的问题，所以相较于现有技术，该些导电组件与该些导电体不会发生接触不良或短路的问题，因而能有效提高产品良率。
附图说明
图1A至图1B为现有封装堆栈结构的制法的剖视示意图；
图2A至图2F为本发明封装结构的制法的剖视示意图；其中，图2C’为图2C的另一实施例；以及
图3及图4为本发明封装结构的其它实施例的剖视示意图。
符号说明
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“顶”、“底”、“侧面”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2F为本发明的封装结构2的制法的剖视示意图。
如图2A所示，提供一具有相对的第一表面21a及第二表面21b的第一基板21。
于本实施例中，该第一基板21为线路板，其具有一芯层21’及形成于该芯层21’上、下侧的多个层间线路213，且该第一表面21a上具有多个焊垫210与多个电性接触垫211，而该第一基板21的第二表面21b上具有多个植球垫212。
此外，该芯层21’的层间线路213的数量可于上、下侧均相同或不相同。
另外，可形成一例如防焊层的绝缘保护层24’于该第一基板21的第二表面21b上，且该绝缘保护层24’的开孔240’外露该些植球垫212。
如图2B所示，形成一介电层20于该第一基板21的第一表面21a上，且形成一开口200及多个盲孔201于该介电层20上。
于本实施例中，先以压合方式形成该介电层20于该第一基板21的第一表面21a上，再以激光钻孔方式形成该开口200及该些盲孔201。于其它实施例中，也可先形成该开口200及该些盲孔201于该介电层20上，再压合该介电层20至该第一基板21的第一表面21a上。
此外，该些盲孔201分别外露该些电性接触垫211，且该开口200外露该些焊垫210及其周围的该第一基板21的第一表面21a。
又，形成该介电层20的材质可为预浸材(Prepreg,PP)。
如图2C所示，形成一线路层23于该介电层20上，且形成多个导电体230于该些盲孔201中，以令该介电层20、线路层23与导电体230作为增层部28，且使该些导电体230电性连接该线路层23与该第一基板21的层间线路213与电性接触垫211。
于本实施例中，于该介电层20与该线路层23上形成有例如防焊层的一绝缘保护层24，且该绝缘保护层24藉由多个开孔240分别外露该些导电体230。
此外，该导电体230为如铜的金属材，且该导电体230为柱状。
又，于一实施例中，该导电体230’为凹槽状，如图2C’所示。
如图2D所示，藉由多个焊锡凸块250设置一电子组件25于该开口200中的该些焊垫210上，并藉由底胶251包覆该些焊锡凸块250，使该电子组件25设于该第一基板21的第一表面21a上，以形成一封装件，且该电子组件25以覆晶方式电性连接该第一基板21的层间线路213与焊垫210。
于本实施例中，该电子组件25为主动组件及/或被动组件，该主动组件例如为芯片，而该被动组件例如为电阻、电容或电感。
于其它实施例中，该电子组件25也可以打线方式电性连接该第一基板21。
如图2E所示，设置一堆栈件22于该导电体230上，以令该堆栈件22叠设于该增层部28上，且覆盖该电子组件25。
于本实施例中，该堆栈件22为第二基板，如线路板，其具有多个层间线路223，且该堆栈件22藉由多个导电组件27电性结合至该导电体230。例如，该堆栈件22的底面22b以如焊锡材料的导电组件27电性连接该导电体230，使该堆栈件22叠设于该增层部28上。或者，该导电体230与该堆栈件22之间也可形成由金属柱270(如铜柱)与焊锡材料271构成的导电组件27，以利于堆栈制程。
此外，如图3所示，该堆栈件32也可为封装件，包含一基板22’、设于该基板22’的顶面22a的其它电子组件35及包覆该电子组件35的封装胶体36，且该电子组件35以覆晶方式或打线方式电性连接该基板22’。
如图2F所示，形成封装胶体26于该第一基板21的第一表面21a与该堆栈件22之间。
于本实施例中，该封装胶体26设于该介电层20(或该绝缘保护层24)与该堆栈件22之间，而未设于该开口200中，所以该封装胶体26包覆该些导电组件27，而未包覆该电子组件25。于其它实施例中，该封装胶体26也可填满该第一基板21的第一表面21a与该堆栈件22之间，以包覆该些导电组件27与该电子组件25。
于另一实施例中，如图3所示，该堆栈件32的宽度d小于该第一基板21的宽度r，使该封装胶体26’还包覆该堆栈件32的侧面32c与顶面32a。
于另一实施例中，本发明的封装结构4中，如图4所示，该增层部48也可包含多个介电层20与多个线路层23。
本发明的制法藉由在第一基板21上形成增层部28(即该介电层20、线路层23与导电体230)，使该导电体230嵌入该介电层20中，再于该增层部28上接置该堆栈件22,32(即另一基板或封装件)，藉以增加隔离(stand off)各该导电体230的效果、及避免各该导电体230之间发生桥接现象。
此外，藉由该些盲孔201控制各该导电体230的尺寸，使各该导电体230的高度一致，以令该些导电组件27的接置处高度一致，因而能避免接点偏移的问题，所以该些导电组件27与该些导电体230不会发生接触不良或短路(short)的问题，因而能有效提高产品良率。
本发明还提供一种封装结构2,3,4，包括：一第一基板21、设于该第一基板21上并电性连接该第一基板21的增层部28,48、电性连接该第一基板21的一电子组件25、叠设于该增层部28,48上的一堆栈件22,32、以及设于该增层部28,48(或该绝缘保护层24)与该堆栈件22,32之间的封装胶体26,26’。
所述的第一基板21为线路板，其具有相对的第一表面21a与第二表面21b。
所述的增层部28,48具有一开口200，且该开口200外露该第一基板21的第一表面21a。
于本实施例中，该增层部28,48包含：设于该第一基板21上的至少一介电层20、设于该介电层20上的线路层23、及位于该介电层20中且外露于该介电层20的导电体230。
具体地，该开口200穿设该介电层20，且该介电层20具有多个盲孔201，并且形成该介电层20的材质为预浸材(Prepreg,PP)。该导电体230,230’设于该盲孔201中并电性连接该线路层23与该第一基板21，又该导电体230,230’为金属材，且该导电体230,230’为柱状或凹槽状。此外，所述的封装结构2,3,4还包括一绝缘保护层24，设于该增层部28,48上并外露该些导电体230,230’。
所述的电子组件25为主动组件或被动组件，其设于该开口200中的第一基板21的第一表面21a上。
所述的堆栈件22,32设于该增层部28,48上。具体地，该堆栈件22,32与该导电体230,230’藉由多个导电组件27相结合，以令该堆栈件22,32叠设于该第一基板21上。
于一实施例中，所述的封装胶体26’还设于该第一基板21与该堆栈件32之间。
于一实施例中，该堆栈件22为如线路板的第二基板；而于另一实施例中，该堆栈件32为封装件。
于一实施例中，该堆栈件32的宽度d小于该第一基板21的宽度r，使该封装胶体26’还包覆该堆栈件32。
综上所述，本发明封装结构及其制法，藉由在该第一基板上形成介电层，使该导电体嵌入该介电层中，再于该增层部上接置该堆栈件，藉以增加隔离效果及避免桥接现象。
此外，藉由该些盲孔控制各该导电体的尺寸，使各该导电体的高度一致，以避免接点偏移的问题，所以该些导电组件与该些导电体不会发生接触不良或短路的问题，因而能有效提高产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (41)

1.一种封装结构，包括：
第一基板；
增层部，其设于该第一基板上并电性连接该第一基板，且该增层部具有开口；
至少一电子组件，其设于该开口中，且电性连接该第一基板；
堆栈件，其设于该增层部上，以令该堆栈件叠设于该第一基板上；以及
封装胶体，其设于该增层部与该堆栈件之间。
2.根据权利要求1所述的封装结构，其特征在于，该第一基板为线路板。
3.根据权利要求1所述的封装结构，其特征在于，该开口外露该第一基板的表面，使该电子组件设于该第一基板的表面上。
4.根据权利要求1所述的封装结构，其特征在于，该增层部包含：
至少一介电层，其设于该第一基板上，且该开口穿设该介电层；及
至少一导电体，其位于该介电层中且外露于该介电层，并电性连接该第一基板。
5.根据权利要求4所述的封装结构，其特征在于，形成该介电层的材质为预浸材。
6.根据权利要求4所述的封装结构，其特征在于，形成该导电体的材质为金属材。
7.根据权利要求4所述的封装结构，其特征在于，该导电体为柱状或凹槽状。
8.根据权利要求4所述的封装结构，其特征在于，该堆栈件与该导电体藉由多个导电组件相结合。
9.根据权利要求4所述的封装结构，其特征在于，该封装结构还包括线路层，其设于该介电层上，且电性连接该导电体。
10.根据权利要求4所述的封装结构，其特征在于，该封装结构还包括绝缘保护层，其设于该增层部上，且外露该导电体。
11.根据权利要求10所述的封装结构，其特征在于，该封装胶体设于该绝缘保护层与该堆栈件之间。
12.根据权利要求1所述的封装结构，其特征在于，该电子组件为主动组件或被动组件。
13.根据权利要求1所述的封装结构，其特征在于，该堆栈件与该增层部藉由多个导电组件相结合。
14.根据权利要求1所述的封装结构，其特征在于，该堆栈件为第二基板或封装件。
15.根据权利要求14所述的封装结构，其特征在于，该第二基板为线路板。
16.根据权利要求1所述的封装结构，其特征在于，该堆栈件的宽度小于该第一基板的宽度。
17.根据权利要求16所述的封装结构，其特征在于，该封装胶体包覆该堆栈件。
18.根据权利要求1所述的封装结构，其特征在于，该封装胶体还设于该第一基板与该堆栈件之间。
19.一种封装结构的制法，包括：
提供一第一基板，该第一基板上具有增层部，且该增层部具有开口；
设置至少一电子组件于该开口中，且该电子组件电性连接该第一基板；以及
设置堆栈件于该增层部上，以令该堆栈件叠设于该第一基板上。
20.根据权利要求19所述的封装结构的制法，其特征在于，该第一基板的制程包括：
提供该第一基板；以及
形成该增层部于该第一基板上，且形成该开口于该增层部上，该增层部并电性连接该第一基板。
21.根据权利要求19所述的封装结构的制法，其特征在于，该第一基板为线路板。
22.根据权利要求19所述的封装结构的制法，其特征在于，该开口外露该第一基板的表面，使该电子组件设于该第一基板的表面上。
23.根据权利要求19所述的封装结构的制法，其特征在于，该增层部的制程包括：
形成至少一介电层于该第一基板上，且形成该开口与多个盲孔于该介电层上；
形成多个导电体于该些盲孔中，使该些导电体电性连接该第一基板；及
设置该电子组件于该开口中。
24.根据权利要求23所述的封装结构的制法，其特征在于，该介电层先压合于该第一基板上，再形成该开口于该介电层上。
25.根据权利要求23所述的封装结构的制法，其特征在于，该介电层先形成该开口，再压合该介电层于该第一基板上。
26.根据权利要求23所述的封装结构的制法，其特征在于，形成该介电层的材质为预浸材。
27.根据权利要求23所述的封装结构的制法，其特征在于，该开口及该些盲孔以激光钻孔方式形成者。
28.根据权利要求23所述的封装结构的制法，其特征在于，形成该导电体的材质为金属材。
29.根据权利要求23所述的封装结构的制法，其特征在于，该导电体为柱状或凹槽状。
30.根据权利要求23所述的封装结构的制法，其特征在于，该堆栈件与该导电体藉由多个导电组件相结合。
31.根据权利要求23所述的封装结构的制法，其特征在于，该制法还包括形成线路层于该介电层上，且该线路层电性连接该些导电体。
32.根据权利要求23所述的封装结构的制法，其特征在于，该制法还包括形成绝缘保护层于该增层部上，且外露该导电体。
33.根据权利要求32所述的封装结构的制法，其特征在于，该制法还包括形成封装胶体于该绝缘保护层与该堆栈件之间。
34.根据权利要求19所述的封装结构的制法，其特征在于，该电子组件为主动组件或被动组件。
35.根据权利要求19所述的封装结构的制法，其特征在于，该堆栈件与该增层部藉由多个导电组件相结合。
36.根据权利要求19所述的封装结构的制法，其特征在于，该堆栈件为第二基板或封装件。
37.根据权利要求36所述的封装结构的制法，其特征在于，该第二基板为线路板。
38.根据权利要求19所述的封装结构的制法，其特征在于，该堆栈件的宽度小于该第一基板的宽度。
39.根据权利要求38所述的封装结构的制法，其特征在于，该制法还包括形成封装胶体于该增层部与该堆栈件之间，且该封装胶体包覆该堆栈件。
40.根据权利要求19所述的封装结构的制法，其特征在于，该制法还包括形成封装胶体于该增层部与该堆栈件之间。
41.根据权利要求40所述的封装结构的制法，其特征在于，该封装胶体还形成于该第一基板与该堆栈件之间。
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