CN107708300A - 电子堆迭结构及其制法 - Google Patents

电子堆迭结构及其制法 Download PDF

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Publication number
CN107708300A
CN107708300A CN201610705783.2A CN201610705783A CN107708300A CN 107708300 A CN107708300 A CN 107708300A CN 201610705783 A CN201610705783 A CN 201610705783A CN 107708300 A CN107708300 A CN 107708300A
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substrate
electronics
stacking structure
passive device
preparation
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CN107708300B (zh
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邱志贤
石启良
洪家惠
陈嘉扬
张月琼
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子堆迭结构及其制法，该电子堆迭结构包括：第一基板、设于该第一基板上的被动元件与第一电子元件、以及设于该被动元件上的第二基板，通过该第二基板通过该被动元件而堆迭至该第一基板上，以利用该些被动元件的高度与体积，使该第一与第二基板之间的距离得以固定。

Description

电子堆迭结构及其制法
技术领域
本发明关于一种堆迭结构，特别是关于一种电子堆迭结构及其制法。
背景技术
随着近年来可携式电子产品的蓬勃发展，各类相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展，为因应此趋势，半导体封装业界遂开发各实施例的堆迭封装(package on package，简称PoP)技术，以期能符合轻薄短小与高密度的要求。
如图1所示，其为现有封装堆迭结构1的剖视示意图。如图1所示，该封装堆迭结构1包括：具有相对的第一表面11a及第二表面11b的第一基板11；覆晶结合该第一基板11的第一半导体芯片10；形成于该第一基板11的电性接触垫111上的焊锡柱13；形成于该第一基板11上以包覆该第一半导体芯片10与焊锡柱13的第一封装胶体14；设于该第二表面11b的植球垫112上的焊球114；通过焊锡柱13迭设于该第一基板11上的第二基板12；以打线方式结合于该第二基板12上的第二半导体芯片15a,15b；以及形成于该第二基板12上以包覆该第二半导体芯片15a,15b的第二封装胶体16。
但是，现有封装堆迭结构1中，由于该第一与第二基板11,12间以焊锡柱13作为支撑与电性连接的元件，而随着电子产品的接点(即I/O)数量愈来愈多，在封装件的尺寸大小不变的情况下，各该焊锡柱13间的间距需缩小，致使容易发生桥接(bridge)的现象，因而造成产品良率过低及可靠度不佳等问题，致使无法应用于更精密的细间距产品。
尤其是，该焊锡柱13于回焊后的体积及高度的公差大，即尺寸变异不易控制，致使不仅接点容易产生缺陷(例如，于回焊时，该焊锡柱13会先变成软塌状态，同时于承受上方第二基板12的重量后，该焊锡柱13容易塌扁变形，继而与邻近该焊锡柱13桥接)，导致电性连接品质不良，且该焊锡柱13所排列成的栅状阵列(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该第一基板11与第二基板12之间呈倾斜接置，甚至产生接点偏移的问题。
此外，若以铜柱取代该焊锡柱13作为支撑，虽可避免倾斜接置的问题，但铜柱的成本较高，故不符合经济效益。
又，由于该些焊锡柱13会占用该第一基板11与第二基板12的布设空间，致使于该第一基板11与第二基板12上难以增加被动元件的数量，因而该封装堆迭结构1难以符合高性能的需求；若要于该第一基板11与第二基板12上增加芯片或被动元件的数量，则需增加该第一基板11与第二基板12的布设面积，致使该封装堆迭结构1不符合朝轻、薄、短、小方向设计的趋势。
另外，设于该第一基板11或第二基板12上的被动元件(图未示)，其接地部(ground)需通过焊锡柱13连结至系统接地部(ground)，致使传递路径过长，而降低该封装堆迭结构1的电气特性。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子堆迭结构及其制法，使第一与第二基板之间的距离得以固定。
本发明的电子堆迭结构，包括：第一基板；第二基板，其通过多个被动元件堆迭于该第一基板上；以及电子元件，其设于该第一基板及/或第二基板上。
本发明还提供一种电子堆迭结构的制法，其包括：提供第一基板及第二基板；以及将该第二基板间隔多个被动元件堆迭于该第一基板上，其中，于该第一基板或第二基板上设有至少一电子元件。
前述的电子堆迭结构及其制法中，该电子元件通过多个导电凸块设于该第一基板或第二基板上。
前述的电子堆迭结构及其制法中，该被动元件电性连接该第一基板或第二基板。
前述的电子堆迭结构及其制法中，该被动元件未电性连接该第一基板与第二基板。
前述的电子堆迭结构及其制法中，该被动元件位于该第一基板的角落处。
前述的电子堆迭结构及其制法中，还包括形成封装层于该第一基板与第二基板之间，且该封装层包覆该些被动元件。
由上可知，本发明的电子堆迭结构及其制法中，是将该第二基板间隔该被动元件而堆迭至该第一基板上，使该第一与第二基板之间的距离固定，故相比于现有技术，本发明的电子堆迭结构无需进行如回焊焊锡柱的制造方法，而通过维持该些被动元件的高度与体积，以避免电性连接品质不良、共面性不良、倾斜接置等问题，因而不仅可提高产品良率，且无须使用成本较高的铜柱。
此外，通过该被动元件作为支撑件，因而不需增加该第一基板与第二基板的布设面积，即可增加被动元件的数量，故相比于现有技术，本发明的电子堆迭结构不仅能符合高性能的需求，且能符合朝轻、薄、短、小方向设计的趋势。
另外，该被动元件作为支撑件，使该被动元件的接地部能通过较短路径连结至系统接地部，故相比于现有通过焊锡柱的较长路径，该电子堆迭结构能提供绝佳的电气特性。
附图说明
图1为现有封装堆迭结构的剖面示意图；
图2A至图2C为本发明的电子堆迭结构的制法的剖面示意图；
图3A至图3G为图2A(省略电子元件)的不同实施例的上视示意图；其中，图3B为局部上视示意图；以及
图4A至图4C为本发明的电子堆迭结构的其它实施例的剖面示意图。
符号说明：
1 封装堆迭结构
10 第一半导体芯片
11,21 第一基板
11a 第一表面
11b 第二表面
111 电性接触垫
112 植球垫
114 焊球
12,22 第二基板
13 焊锡柱
14 第一封装胶体
15a,15b 第二半导体芯片
16 第二封装胶体
2,2’,4,4’,4” 电子堆迭结构
20 第一电子元件
200,400 导电凸块
210,220 线路层
23,40b 被动元件
24,44 封装层
40,40’ 第二电子元件
40a 主动元件。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子堆迭结构的制法的剖面示意图。
如图2A所示，提供一第一基板21，且该第一基板21上设有至少一第一电子元件20与多个被动元件23。
于本实施例中，该第一基板21为线路板，其具有多个线路层210。应可理解地，该第一基板21也可为其它承载件，并不限于上述。
此外，该第一电子元件20为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该第一电子元件20通过多个导电凸块200以覆晶方式设于该第一基板21上侧的线路层210上，例如，该导电凸块200为焊锡材料。或者，该第一电子元件20可通过多个焊线(图略)以打线方式电性连接该第一基板21上侧的线路层210。
又，该被动元件23为例如电阻、电容及电感，且该被动元件23可选择性地电性连接或未电性连接该第一基板21。具体地，该被动元件23以去耦合电容(decouplingcapacitor)为例。
如图2B所示，将一第二基板22结合至该被动元件23上，使该第二基板22通过该些被动元件23堆迭于该第一基板21上，以形成电子堆迭结构2。
于本实施例中，该第二基板22可例如为硅中介板、线路板、抑或封装件，且该被动元件23可选择性地电性连接或未电性连接该第二基板22(其线路层220)。例如，当该被动元件23没有电性连结该第一基板21及第二基板22时，该被动元件23可视为仅具有支撑功能的虚设(dummy)电子元件。
此外，该被动元件23的布设可依需求作配置。如图3A所示，其配合该第二基板22的重量作配置，以于该第一基板21的角落处或重量分布不均处(如位于基板的1/4等分位置等的不同位置)布设被动元件23；或者，如图3B至图3G所示，可依该电子堆迭结构2的应力分布作配置，以于该第一基板21的单一角落处布设多个被动元件23，也就是，该电子堆迭结构2的应力集中于角落，故选择性于角落处设置多个被动元件23，藉以达到平衡应力，以减少该电子堆迭结构2的翘曲。
如图2C所示，形成一封装层24于该第一基板21上侧与该第二基板22下侧之间，使该封装层24包覆该第一电子元件20、该些被动元件23与该些导电凸块200。
于本实施例中，该第一基板21的下侧线路层上可形成有焊球(图略)，以供接置如电路板或另一线路板的电子结构。
此外，如图4A所示的电子堆迭结构4，也可设置第二电子元件40于该第二基板22上侧，再形成另一封装层44于该第二基板22上侧，且该另一封装层44包覆该第二电子元件40，其中，该第二电子元件40为主动元件40a、被动元件40b或其二者组合等，该主动元件40a为例如半导体芯片，且该被动元件40b为例如电阻、电容及电感。例如，该主动元件40a通过多个导电凸块400以覆晶方式设于该第二基板22上侧的线路层220上，且该导电凸块400为焊锡材料；或者，该主动元件40a可以打线方式电性连接该第二基板22。
又，如图4B所示的电子堆迭结构4’，该第二电子元件40’也可通过多个导电凸块400设于该第二基板22下侧的线路层220上，其制造方法先将第二电子元件40’设于该第二基板22下侧，再将设有该第二电子元件40’的第二基板22接置于被动元件23上。
另外，如图4C所示的电子堆迭结构4”，为同时采用图4A及图4B的第二电子元件40,40’的布设。
应可理解地，除了该被动元件23之外，该第一基板21与第二基板22之间还可增设如焊锡柱、铜核球或其它导体元件的支撑件(图略)，其可电性连接(或不电性连接)该第一基板21或第二基板22。
另外于其它实施例中，也可先将被动元件23接置于第二基板22下表面，再将结合有该被动元件23的第二基板22间隔该被动元件23而接置于该第一基板21上。此外，可选择于该第一基板21及第二基板22上择一设置电子元件或同时设置电子元件(如第一电子元件20及第二电子元件40)。
本发明的制法中，于该第一基板21与第二基板22之间通过该被动元件23作为支撑(及电性连接)的元件，故随着电子产品的接点(即I/O)数量愈来愈多，在封装件的尺寸大小不变的情况下，各该被动元件23间的间距缩小后，不会发生桥接(bridge)的现象，因而能提高产品良率及可靠度，使该电子堆迭结构2,2’,4,4’,4”得以应用于更精密的细间距产品。
尤其是，本发明的制法通过该第二基板22直接接触结合至该被动元件23上，因而该电子堆迭结构2,2’,4,4’,4”无需进行回焊焊锡柱的制造方法，故能维持该些被动元件23的高度与体积，使该第二基板22与该第一基板21之间的距离固定。因此，该电子堆迭结构2,2’,4,4’,4”能维持良好的电性连接品质，且该些被动元件23所排列成的栅状阵列(gridarray)的共面性(coplanarity)良好，因而接点应力(stress)保持平衡而不会造成该第一与第二基板21,22之间呈倾斜接置，以避免产生接点偏移的问题。
此外，由于该第二基板22与该第一基板21之间的距离固定，故若于该第一基板21与第二基板22之间增设焊锡柱，即使进行回焊该焊锡柱的制造方法，仍可控制该些焊锡柱的高度与体积，以于回焊该些焊锡柱后，该些焊锡柱所构成的接点仍可维持良好的电性连接品质，且该些焊锡柱所排列成的栅状阵列的共面性良好，因而接点应力保持平衡而不会造成该第一与第二基板21,22之间呈倾斜接置，以避免产生接点偏移的问题。
又，通过该被动元件23作为支撑件，因而不需增加该第一基板21与第二基板22的布设面积，即可增加被动元件的数量，故该电子堆迭结构2,2’,4,4’,4”不仅能符合高性能的需求，且能符合朝轻、薄、短、小方向设计的趋势。
另外，该被动元件23作为支撑件，使该被动元件23的接地部(ground)能通过最短路径(也就是直接连接该第一基板21的线路层210与第二基板22的线路层220)连结至该第一电子元件20与系统接地部(ground)，故相比于现有通过焊锡柱的较长路径，该电子堆迭结构2,2’,4,4’,4”能提供绝佳的电气特性。
本发明提供一种电子堆迭结构2,2’,4,4’,4”，其包括：第一基板21、设于该第一基板21上的被动元件23、设于该被动元件23上的第二基板22、设于该第一基板21上的第一电子元件20、设于该第二基板22上的第二电子元件40,40’、以及设于该第一基板21与第二基板22之间的封装层24。
所述的第二基板22通过该些被动元件23堆迭于该第一基板21上。
所述的封装层24包覆该些被动元件23。
于一实施例中，该第一电子元件20通过多个导电凸块200设于该第一基板21上。
于一实施例中，该第二电子元件40,40’通过多个导电凸块400设于该第二基板22上。
于一实施例中，该被动元件23电性连接该第一基板21及/或第二基板22。
于一实施例中，该被动元件23未电性连接该第一基板21与第二基板22。
于一实施例中，该被动元件23设于该第一基板21的角落处。
综上所述，本发明的电子堆迭结构及其制法，主要通过将该第二基板通过该些被动元件而堆迭至该第一基板上，使该第二基板与该第一基板之间的距离固定，因而能维持良好的电性连接品质与共面性，且因接点应力保持平衡而不会造成倾斜接置。
此外，通过该被动元件作为支撑件，因而不需增加该第一基板与第二基板的布设面积，即可增加被动元件的数量，故本发明的电子堆迭结构不仅能符合高性能的需求，且能符合朝轻、薄、短、小方向设计的趋势。
另外，该被动元件作为支撑件，使该被动元件的接地部能通过最短路径连结至系统接地部，故该电子堆迭结构能提供绝佳的电气特性。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (14)

1.一种电子堆迭结构，其特征为，该电子堆迭结构包括：
第一基板；
第二基板，其通过多个被动元件堆迭于该第一基板上；以及
电子元件，其设于该第一基板及/或第二基板上。
2.如权利要求1所述的电子堆迭结构，其特征为，该电子元件通过多个导电凸块设于该第一基板上。
3.如权利要求1所述的电子堆迭结构，其特征为，该电子元件通过多个导电凸块设于该第二基板上。
4.如权利要求1所述的电子堆迭结构，其特征为，该被动元件电性连接该第一基板或第二基板。
5.如权利要求1所述的电子堆迭结构，其特征为，该被动元件未电性连接该第一基板与第二基板。
6.如权利要求1所述的电子堆迭结构，其特征为，该被动元件位于该第一基板的角落处。
7.如权利要求1所述的电子堆迭结构，其特征为，该被动元件位于该第一基板的重量分布不均处。
8.一种电子堆迭结构的制法，其特征为，该制法包括：
提供第一基板及第二基板；以及
将该第二基板间隔多个被动元件而堆迭于该第一基板上，其中，于该第一基板或第二基板上设有至少一电子元件。
9.如权利要求8所述的电子堆迭结构的制法，其特征为，该电子元件通过多个导电凸块设于该第一基板上。
10.如权利要求8所述的电子堆迭结构的制法，其特征为，该电子元件通过多个导电凸块设于该第二基板上。
11.如权利要求8所述的电子堆迭结构的制法，其特征为，该被动元件电性连接该第一基板或第二基板。
12.如权利要求8所述的电子堆迭结构的制法，其特征为，该被动元件未电性连接该第一基板与第二基板。
13.如权利要求8所述的电子堆迭结构的制法，其特征为，该被动元件位于该第一基板的角落处。
14.如权利要求8项所述的电子堆迭结构的制法，其特征为，该制法还包括形成封装层于该第一基板与第二基板之间，且该封装层包覆该些被动元件。
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