CN110767636A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110767636A
CN110767636A CN201910201970.0A CN201910201970A CN110767636A CN 110767636 A CN110767636 A CN 110767636A CN 201910201970 A CN201910201970 A CN 201910201970A CN 110767636 A CN110767636 A CN 110767636A
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China
Prior art keywords
package substrate
bumps
pads
chip
distance
Prior art date
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Withdrawn
Application number
CN201910201970.0A
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English (en)
Inventor
张A·N
白南奎
赵允来
韩承宪
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110767636A publication Critical patent/CN110767636A/zh
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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Abstract

一种半导体封装，包括：封装基板；多个外部连接，封装基板下方；主芯片，在封装基板上；至少一个从芯片，在主芯片上；多个第一凸块和多个第二凸块，在封装基板与主芯片之间；以及多根引线，将封装基板与至少一个从芯片相连。封装基板包括：多条第一路径，将多个第一凸块与多个外部连接相连；以及多条第二路径，将多个第二凸块与多根引线相连。封装基板的上表面包括沿第一方向延伸的第一边和第二边以及沿第二方向延伸的第三边和第四边。

Description

半导体封装
相关申请的交叉引用
本申请要求于2018年7月25日在韩国知识产权局提交的韩国专利申请第10-2018-0086767号的优先权，该申请的公开内容通过引用全部并入本文中。
技术领域
本发明构思涉及半导体封装，更具体地，涉及包括多个半导体芯片的半导体封装。
背景技术
为了实现更高密度的半导体封装，已经开发了包括多个堆叠的半导体芯片的半导体封装。多个半导体芯片可以通过引线或者通过硅通孔(TSV)彼此连接。此外，半导体芯片可以通过使用引线的引线接合方法或者使用凸块的倒装芯片接合方法来连接到封装基板。
发明内容
本发明构思提供了一种具有改善的信号完整性(SI)特性和/或更高成本竞争力的半导体封装。
根据本发明构思的一方面，提供了一种半导体封装，包括：封装基板；多个外部连接，在所述封装基板下方；主芯片，在所述封装基板上；至少一个从芯片，在所述主芯片上；多个第一凸块和多个第二凸块，在所述封装基板和所述主芯片之间；以及多根引线，将所述封装基板和所述至少一个从芯片相连。封装基板包括：多条第一路径，将多个第一凸块与多个外部连接相连；以及多条第二路径，将多个第二凸块与多根引线相连。封装基板的上表面包括沿第一方向延伸的第一边和第二边以及沿第二方向延伸的第三边和第四边。
根据本发明构思的一方面，提供了一种半导体封装，包括：封装基板，包括多个第一上焊盘、与所述多个第一上焊盘相连的多个下焊盘、多个第二上焊盘以及与所述多个第二上焊盘相连的多个第三上焊盘；多个外部连接，与所述封装基板的所述多个下焊盘相连；主芯片，在所述封装基板上；至少一个从芯片，在所述主芯片上；多个第一凸块，在所述封装基板的所述多个第一上焊盘与所述主芯片之间；多个第二凸块，在所述封装基板的所述多个第二上焊盘与所述主芯片之间；以及多根引线，将所述封装基板的所述多个第三上焊盘和所述至少一个从芯片相连，封装基板的上表面包括沿第一方向延伸的第一边和第二边以及沿第二方向延伸的第三边和第四边。
根据本发明构思的一方面，提供了一种半导体封装，包括：封装基板；多个外部连接，封装基板下方；主芯片，在封装基板上；至少一个从芯片，在主芯片上；多个第一凸块和多个第二凸块，在封装基板与主芯片之间；以及多根引线，将封装基板和至少一个从芯片相连。封装基板包括接触所述多个第一凸块的多个第一上焊盘以及接触所述多个第二凸块和所述多根引线的多个第二上焊盘。
附图说明
根据以下结合附图进行的详细描述，将更清楚地理解本发明构思的实施例，在附图中：
图1是示出了根据本发明构思的实施例的半导体封装的框图；
图2是示出了根据本发明构思的实施例的半导体封装的截面图；
图3是示出了根据本发明构思的实施例的主芯片和多个凸块的仰视图；
图4是示出了根据本发明构思的实施例的封装基板的顶面的俯视图；
图5是示出了根据本发明构思的实施例的封装基板的顶面的俯视图；
图6是示出了根据本发明构思的实施例的主芯片和多个凸块的仰视图；
图7是示出了根据本发明构思的实施例的封装基板的顶面的俯视图；
图8是示出了根据本发明构思的实施例的半导体封装的截面图；
图9是示出了根据本发明构思的实施例的半导体封装的截面图；
图10是示出了根据本发明构思的实施例的封装基板的顶面的俯视图；以及
图11是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。
具体实施方式
图1是示出了根据本发明构思的实施例的半导体封装100的框图。
参考图1，根据本发明构思的实施例的半导体封装100可以包括封装基板110、主芯片120和/或至少一个从芯片130。在图1中，半导体封装100被示为包括三个从芯片130。然而，半导体封装100中包括的从芯片130的数量可以变化。例如，半导体封装100可以包括一个或多个从芯片130。
封装基板110可以包括用于将主芯片120与外部连接(未示出)相连的第一路径P1和用于将至少一个从芯片130与主芯片120相连的第二路径P2。主芯片120可以通过倒装芯片接合方法连接到封装基板110。主芯片120通过封装基板110的第一路径P1连接到外部连接，并且可以通过封装基板110的第二路径P2连接到至少一个从芯片130。至少一个从芯片130可以通过引线接合方法连接到封装基板110。至少一个从芯片130可以通过封装基板110的第二路径P2连接到主芯片120。在一个实施例中，第一路径P1和第二路径P2是用于电连接的路径。
主芯片120和至少一个从芯片130中的每一个可以是存储器芯片。存储器芯片可以是例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或者电阻性随机存取存储器(RRAM)芯片。主芯片120和至少一个从芯片130可以是相同类型的存储器芯片。例如，主芯片120和至少一个从芯片130都可以是DRAM芯片。
图2是示出了根据本发明构思的实施例的半导体封装的截面图。
参考图2，根据本发明构思的实施例的半导体封装100可以包括封装基板110、外部连接190、主芯片120、至少一个从芯片130、芯片粘合层160、多个凸块151和152、多根引线140和/或模制单元(例如，密封剂)180。
封装基板110可以包括例如印刷电路板(PCB)或者柔性PCB(FPCB)。封装基板110可以包括基层114、多个第一上焊盘111、多个第二上焊盘112、多个第三上焊盘113、多个下焊盘115、多条第一路径P1和/或多条第二路径P2。多个第一上焊盘111、多个第二上焊盘112和多个第三上焊盘113可以布置在基层114的上部中，并且多个下焊盘115可以布置在基层114的下部中。
多个第一上焊盘111可以与多个第一凸块151相连。多个第二上焊盘112可以与多个第二凸块152相连。多个第三上焊盘113可以与多根引线140相连。多个下焊盘115可以与多个外部连接190相连。多条第一路径P1可以将多个第一上焊盘111连接到多个下焊盘115。多条第二路径P2可以将多个第二上焊盘112连接到多个第三上焊盘113。
基层114可以由环氧树脂、聚酯树脂、聚酰亚胺树脂或者这些树脂的组合形成。基层114可以由例如玻璃纤维环氧树脂复合材料形成。多个第一上焊盘111、多个第二上焊盘112、多个第三上焊盘113、多个下焊盘115、多条第一路径P1和/或多条第二路径P2可以由诸如铜(Cu)的导电材料形成。
多个外部连接190可以将半导体封装100连接到外部电路。多个外部连接190可以布置在封装基板110的多个下焊盘115上。多个外部连接190可以由例如金(Au)、银(Ag)、Cu、镍(Ni)、锡(Sn)、铅(Pb)或者这些金属的组合形成。外部连接190可以包括例如焊球。根据联合电子器件工程委员会(JEDEC)标准，多个外部连接190可以布置在封装基板110的下表面上。JEDDEC标准是基于如下情况的：主芯片120不是通过引线接合方法而是通过倒装芯片接合方法连接到封装基板110。
主芯片120可以布置在封装基板110上。与多个第一凸块151或者多个第二凸块152接触的芯片焊盘(未示出)可以位于主芯片120的下表面上。主芯片120可以通过多个第一凸块151、多个第一上焊盘111、多条第一路径P1和/或封装基板110的多个下焊盘115连接到外部连接190。主芯片120可以通过多个第二凸块152、多个第二上焊盘112、多条第二路径P2、封装基板110的多个第三上焊盘113和/或多根引线140连接到至少一个从芯片130。
至少一个从芯片130可以布置在主芯片120上。当半导体封装100包括多个从芯片130时，多个从芯片130可以堆叠在主芯片120上。至少一个从芯片130可以通过多根引线140、多个第三上焊盘113、多条第二路径P2、多个第二上焊盘112和多个第二凸块152连接到主芯片120。
芯片粘合层160可以位于从芯片130的下表面上。引线接合焊盘170可以位于从芯片130的上表面上。芯片粘合层160可以包括例如环氧树脂。引线接合焊盘170可以包括铝(A1)、Cu、Ag、Au或者上述金属的组合。
多个凸块151和152可以位于主芯片120和封装基板110之间。也就是说，多个凸块151和152可以附接到主芯片120的下表面。多个凸块151和152可以包括多个第一凸块151和多个第二凸块152。多个第一凸块151将主芯片120连接到封装基板110的多个第一上焊盘111。多个第二凸块152将主芯片120连接到封装基板110的多个第二上焊盘112。多个凸块151和152可以由Au、Ag、Cu、Ni、Sn、Pb或者上述金属的组合形成。多个凸块151和152可以包括例如焊球。
多根引线140可以将至少一个从芯片130上的引线接合焊盘170连接到封装基板110的多个第三上焊盘113。多根引线140可以包括Al、Cu、Ag、Au或者上述金属的组合。
模制单元(例如，密封剂)180覆盖封装基板110的上表面并且可以包裹主芯片120和至少一个从芯片130。模制单元180可以包括热固性树脂、热塑性树脂、紫外(UV)固化树脂或者上述树脂的组合。模制单元180可以包括例如环氧树脂、硅树脂或者上述树脂的组合。模制单元180可以包括例如环氧模塑复合物(EMC)。
图3是示出了根据本发明构思的实施例的主芯片和多个凸块的仰视图。
参考图3，主芯片120的下表面可以近似是矩形或者正方形。也就是说，主芯片120的下表面可以包括四条边，即，第一边120E1、第二边120E2、第三边120E3和第四边120E4。主芯片120的下表面的第一边120E1和第二边120E2可以沿第一方向X延伸。主芯片120的下表面的第三边120E3和第四边120E4可以沿第二方向Y延伸。第一方向X可以垂直于第二方向Y。
主芯片120的下表面的第一中心线120CL1沿第一方向X延伸以与主芯片120的下表面的第一边120E1和第二边120E2保持平行，并且可以经过主芯片120的下表面的中心点120CP。从主芯片120的下表面的第一中心线120CL1沿第二方向Y到主芯片120的下表面的第一边120E1的距离可以与从主芯片120的下表面的第一中心线120CL1沿第二方向Y到主芯片120的下表面的第二边120E2的距离相同。
主芯片120的下表面的第二中心线120CL2沿第二方向Y延伸以与主芯片120的下表面的第三边120E3和第四边120E4保持平行，并且可以经过主芯片120的下表面的中心点120CP。从主芯片120的下表面的第二中心线120CL2沿第一方向X到主芯片120的下表面的第三边120E2的距离可以与从主芯片120的下表面的第二中心线120CL2沿第一方向X到主芯片120的下表面的第四边120E4的距离相同。
主芯片120的下表面的第一中心线120CL1和第二中心线120CL2可以与主芯片120的下表面的中心点120CP相交。也就是说，从主芯片120的下表面的中心点120CP沿第二方向Y到主芯片120的下表面的第一边120E1的距离与从主芯片120的下表面的中心点120CP沿第二方向Y到主芯片120的下表面的第二边120E2的距离相同。从主芯片120的下表面的中心点120CP沿第一方向X到主芯片120的下表面的第三边120E3的距离可以与从主芯片120的下表面的中心点120CP沿第一方向X到主芯片120的下表面的第四边120E4的距离相同。
多个第一凸块151可以包括第一组151a和第二组151b。在多个第一凸块151中，第一组的第一凸块151a距主芯片120的下表面的第三边120E3的距离可以小于距主芯片120的下表面的第四边120E4的距离。另一方面，在多个第一凸块151中，第二组的第一凸块151b距主芯片120的下表面的第四边120E4的距离可以小于距主芯片120的下表面的第三边120E3的距离。在多个第一凸块151中，第一组的第一凸块151a可以被配置为发送不同于第二组的第一凸块151b发送的信号的信号。例如，多个第一凸块151中的第一组151a被配置为发送数据信号，并且多个第一凸块151中的第二组151b可以被配置为发送地址信号和时钟信号。
多个第一凸块151可以比多个第二凸块152更靠近主芯片120的下表面的第一中心线120CL1。
多个第一凸块151中的至少一个可以布置在主芯片120的下表面的中心部分中。例如，多个第一凸块151中的至少一个距主芯片120的下表面的第一中心线120CL1的距离可以小于距主芯片120的下表面的第一边120E1和第二边120E2的距离。此外，多个第一凸块151中的至少一个距主芯片120的下表面的第二中心线120CL2的距离可以小于距主芯片120的下表面的第三边120E3和第四边120E4的距离。
在一些实施例中，多个第一凸块151中的全部第一凸块可以布置在主芯片120的下表面的中心部分中。例如，多个第一凸块151中的全部第一凸块距主芯片120的下表面的第一中心线120CL1的距离可以小于距主芯片120的下表面的第一边120E1和第二边120E2的距离。
多个第二凸块152可以布置在主芯片120的下表面的边缘部分处。在一些实施例中，多个第二凸块152可以与主芯片120的下表面的第一边120E1或者第二边120E2相邻。也就是说，在多个第二凸块152中的第一组的第二凸块152a距主芯片120的下表面的第一边120E1的距离可以小于距主芯片120的下表面的第一中心线120CL1的距离。此外，在多个第二凸块152中的第二组的第二凸块152b距主芯片120的下表面的第二边120E2的距离可以小于距主芯片120的下表面的第一中心线120CL1的距离。在一些实施例中，多个第二凸块152可以是沿主芯片120的下表面的第一边120E1和第二边120E2布置的。也就是说，在多个第二凸块152中，第一组的第二凸块152a和第二组的第二凸块152b可以是沿第一方向X布置的。
图4是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。
参考图4，封装基板的上表面可以近似是矩形或正方形。也就是说，封装基板110的上表面可以包括四条边，即，第一边110E1、第二边110E2、第三边110E3和第四边110E4。封装基板110的上表面的第一边110E1和第二边110E2可以沿第一方向X延伸。封装基板110的上表面的第三边110E3和第四边110E4可以沿第二方向Y延伸。
封装基板110的上表面的第一中心线110CL1沿第一方向X延伸以与封装基板110的上表面的第一边110E1和第二边110E2保持平行，并且可以经过封装基板110的上表面的中心点110CP。从封装基板110的上表面的第一中心线110CL1沿第二方向Y到封装基板110的上表面的第一边110E1的距离可以与从封装基板110的上表面的第一中心线110CL1沿第二方向Y到封装基板110的上表面的第二边110E2的距离相同。
封装基板110的上表面的第二中心线110CL2沿第二方向Y延伸以与封装基板110的上表面的第三边110E3和第四边110E4保持平行，并且可以经过封装基板110的上表面的中心点110CP。从封装基板110的上表面的第二中心线110CL2沿第一方向X到封装基板110的上表面的第三边110E3的距离可以与从封装基板110的上表面的第二中心线110CL2沿第一方向X到封装基板110的上表面的第四边110E4的距离相同。
封装基板110的上表面的第一中心线110CL1和第二中心线110CL2可以与封装基板110的上表面的中心点110CP相交。也就是说，从封装基板110的上表面的中心点110CP沿第二方向Y到封装基板110的上表面的第一边110E1的距离与从封装基板110的上表面的中心点110CP沿第二方向Y到封装基板110的上表面的第二边110E2的距离相同。从封装基板110的上表面的中心点110CP沿第一方向X到封装基板110的上表面的第三边110E3的距离可以与从封装基板110的上表面的中心点110CP沿第一方向X到封装基板110的上表面的第四边110E4的距离相同。
多个第一上焊盘111可以包括第一组111a和第二组111b。在多个上焊盘111中的第一组上焊盘111a距封装基板110的上表面的第三边110E3的距离可以小于距封装基板110的上表面的第四边110E4的距离。在多个第一上焊盘111中的第二组上焊盘111b距封装基板110的上表面的第四边110E4的距离可以小于距封装基板110的上表面的第三边110E3的距离。
多个第一上焊盘111可以比多个第二上焊盘112更靠近封装基板110的上表面的第一中心线110CL1。此外，多个第一上焊盘11I可以比多个第三上焊盘113更靠近封装基板110的上表面的第一中心线110CL1。此外，多个第二上焊盘112可以比多个第三上焊盘113更靠近封装基板110的上表面的第一中心线110CL1。
多个第一上焊盘111可以布置在封装基板110的中心部分中。也就是说，多个第一上焊盘111距封装基板110的上表面的第一中心线110CL1的距离可以小于距封装基板110的上表面的第一边110E1和第二边110E2的距离。
多个第三上焊盘113可以布置在封装基板110的边缘部分处。在一些实施例中，多个第三上焊盘113可以与封装基板110的上表面的第一边110E1或者第二边110E2相邻。也就是说，在多个第三上焊盘113中的第一组的第三上焊盘113a距封装基板110的上表面的第一边110E1的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。此外，在多个第三上焊盘113中的第二组的第三上焊盘113b距封装基板110的上表面的第二边110E2的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。在一些实施例中，多个第三上焊盘113可以是沿封装基板110的上表面的第一边110E1和第二边110E2布置的。也就是说，在多个第三上焊盘113中，第一组的第三上焊盘113a和第二组的第三上焊盘113b可以是沿第一方向X布置的。
在一些实施例中，多个第二上焊盘112可以布置在封装基板110的边缘部分处。在一些实施例中，多个第二上焊盘112可以与封装基板110的上表面的第一边110E1或者第二边110E2相邻。也就是说，在多个第二上焊盘112中的第一组的第二上焊盘112a距封装基板110的上表面的第一边110E1的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。此外，在多个第二上焊盘112中的第二组的第二上焊盘112b距封装基板110的上表面的第二边110E2的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。在一些实施例中，多个第二上焊盘112可以是沿封装基板110的上表面的第一边110E1和第二边110E2布置的。也就是说，在多个第二上焊盘112中，第一组的第二上焊盘112a和第二组的第二上焊盘112b可以是沿第一方向X布置的。
图5是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。
参考图5，为了说明封装基板110的多个第一上焊盘111和多个下焊盘115之间的连接关系，一起示出了封装基板110的下表面上的多个下焊盘115和封装基板110中的多条第一路径P1。为了方便起见，多条第一路径P1被示为直线。然而，多条第一路径P1实际上可以具有更复杂的形状。
多条第一路径P1将多个第一上焊盘111连接到多个下焊盘115。由于多个第一上焊盘111位于封装基板110的上表面的中心部分，即，由于多个第一上焊盘111被布置为距封装基板110的第一中心线110CL1的距离小于距封装基板110的上表面的第一边110E1和第二边110E2的距离，因此多条第一路径P1的长度可以小于在多个第一上焊盘111位于封装基板110的上表面的边缘处的情况。因此，根据本发明构思的实施例的半导体封装100(参考图2)的信号完整性(SI)可以得到改善。
参考图2，根据基于倒装芯片定义的JEDEC标准来布置多个下焊盘115和多个外部连接190。因此，当通过倒装芯片接合将主芯片120连接到封装基板110时，与主芯片120通过引线接合连接到封装基板110的情况相比，可以减小多条第一路径P1的长度或使其最小化。因此，根据本发明构思的实施例的半导体封装100的SI可以得到改善。
另一方面，至少一个从芯片130通过多根引线140连接到封装基板110的多个第三上焊盘113，这是一种低成本的方式。因此，根据本发明构思的实施例的半导体封装100可以具有较高的成本竞争力。
图6是示出了根据本发明构思的实施例的主芯片和多个凸块的仰视图。
参考图6，多个第一凸块151可以比多个第二凸块152更靠近主芯片120的下表面的中心点120CP。此外，多个第二凸块152还可以包括第三组152c和第四组152d。在多个第二凸块152中的第三组的第二凸块152c可以与主芯片120的下表面的第三边120E3相邻。也就是说，在多个第二凸块152中的第三组的第二凸块152c距主芯片120的下表面的第三边120E3的距离可以小于距主芯片120的下表面的第二中心线120CL2的距离。在多个第二凸块152中的第四组的第二凸块152d可以与主芯片120的下表面的第四边120E4相邻。也就是说，在多个第二凸块152中的第四组的第二凸块152d距主芯片120的下表面的第四边120E4的距离可以小于距主芯片120的下表面的第二中心线120CL2的距离。在一些实施例中，在多个第二凸块152中，第三组的第二凸块152c和第四组的第二凸块152d可以是分别沿主芯片120的下表面的第三边120E3和第四边120E4布置的。也就是说，在多个第二凸块152中，第三组的第二凸块152c和第四组的第二凸块152d可以是沿第二方向Y布置的。
图7是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。
参考图7，多个第二上焊盘112还包括第三组112c和第四组112d。在多个第二上焊盘112中，第三组的第二上焊盘112c可以与封装基板110的上表面的第三边110E3相邻。也就是说，在多个第二上焊盘112中的第三组的第二上焊盘112c距封装基板110的上表面的第三边110E3的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。此外，在多个第二上焊盘112中，第四组的第二上焊盘112d可以与封装基板110的上表面的第四边110E4相邻。也就是说，在多个第二上焊盘112中的第四组的第二上焊盘112d距封装基板110的上表面的第四边110E4的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。
此外，多个第三上焊盘113还包括第三组113c和第四组113d。在多个第三上焊盘113中，第三组的第三上焊盘113c可以与封装基板110的上表面的第三边110E3相邻。也就是说，在多个第三上焊盘113中的第三组的第三上焊盘113c距封装基板110的上表面的第三边110E3的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。此外，在多个第三上焊盘113中，第四组的第三上焊盘113d可以与封装基板110的上表面的第四边110E4相邻。也就是说，在多个第三上焊盘113中的第四组的第三上焊盘113d距封装基板110的上表面的第四边110E4的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。
在一些实施例中，多个第一上焊盘111可以比多个第二上焊盘112更靠近封装基板110的上表面的中心点110CP。此外，多个第一上焊盘111可以比多个第三上焊盘113更靠近封装基板110的上表面的中心点110CP。
图8是示出了根据本发明构思的实施例的半导体封装的截面图。在下文中，将描述根据图2的实施例的半导体封装与根据图8的实施例的半导体封装之间的差别。
参考图8，至少一个从芯片130可以以Z字形堆叠。
图9是示出了根据本发明构思的实施例的半导体封装的截面图。在下文中，将描述根据图2的实施例的半导体封装与根据图9的实施例的半导体封装之间的差别。
参考图9，多根引线140和多个第二凸块152可以接触封装基板110的多个第二上焊盘212。也就是说，至少一个从芯片130可以通过多根引线140、多个第二上焊盘212和/或多个第二凸块152连接到主芯片120。
图10是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。在下文中，将描述图4的实施例与图10的实施例之间的差别。
参考图10，多个第二上焊盘212可以与封装基板110的上表面的第一边110E1或第二边110E2相邻。也就是说，在多个第二上焊盘212中的第一组的第二上焊盘212a距封装基板110的上表面的第一边110E1的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。此外，在多个第二上焊盘212中的第二组的第二上焊盘212b距封装基板110的上表面的第二边110E2的距离可以小于距封装基板110的上表面的第一中心线110CL1的距离。在一些实施例中，多个第二上焊盘212可以是沿封装基板110的上表面的第一边110E1和第二边110E2布置的。也就是说，在多个第二上焊盘212中，第一组的第二上焊盘212a和第二组的第二上焊盘212b可以是沿第一方向X布置的。
多个第二上焊盘212的面积可以大于多个第一上焊盘111的面积。
图11是示出了根据本发明构思的实施例的封装基板的顶面的俯视图。在下文中，将描述图10的实施例与图11的实施例之间的差别。
参考图11，多个第二上焊盘212还包括第三组212c和第四组212d。在多个第二上焊盘212中，第三组的第二上焊盘212c可以与封装基板110的上表面的第三边110E3相邻。也就是说，在多个第二上焊盘212中的第三组的第二上焊盘212c距封装基板110的上表面的第三边110E3的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。此外，在多个第二上焊盘212中，第四组的第二上焊盘212d可以与封装基板110的上表面的第四边110E4相邻。也就是说，在多个第二上焊盘212中的第四组的第二上焊盘212d距封装基板110的上表面的第四边110E4的距离可以小于距封装基板110的上表面的第二中心线110CL2的距离。
尽管已经参考本发明构思的实施例具体示出和描述了本发明构思，但是应当理解，在不脱离所附权利要求的精神和范围的情况下，可以在其中进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
封装基板；
多个外部连接，在所述封装基板下方；
主芯片，在所述封装基板上；
至少一个从芯片，在所述主芯片上；
多个第一凸块和多个第二凸块，在所述封装基板和所述主芯片之间；以及
多根引线，将所述封装基板与所述至少一个从芯片相连；
其中所述封装基板包括：多条第一路径，将所述多个第一凸块与所述多个外部连接相连；以及多条第二路径，将所述多个第二凸块与所述多根引线相连，以及
其中所述封装基板的上表面包括沿第一方向延伸的第一边和第二边以及沿第二方向延伸的第三边和第四边。
2.根据权利要求1所述的半导体封装，其中，所述主芯片通过所述多个第一凸块和所述封装基板的所述多条第一路径连接到所述多个外部连接。
3.根据权利要求1所述的半导体封装，其中，所述至少一个从芯片通过所述多根引线、所述封装基板的所述多条第二路径和所述多个第二凸块连接到所述主芯片。
4.根据权利要求1所述的半导体封装，其中，所述多个第一凸块比所述多个第二凸块更靠近沿所述第一方向延伸并经过所述主芯片的下表面的中心点的第一中心线。
5.根据权利要求1所述的半导体封装，其中，所述多个第一凸块比所述多个第二凸块更靠近所述主芯片的下表面的中心点。
6.根据权利要求1所述的半导体封装，其中，所述多个第一凸块中的至少一个距沿所述第一方向延伸并经过所述主芯片的下表面的中心点的第一中心线的距离小于距所述主芯片的下表面的第一边和第二边的距离。
7.根据权利要求1所述的半导体封装，其中，所述多个第一凸块中的至少一个距沿所述第二方向延伸并经过所述主芯片的下表面的中心点的第二中心线的距离小于距所述主芯片的下表面的第三边和第四边的距离。
8.根据权利要求1所述的半导体封装，
其中，所述多个第二凸块中的第一组的第二凸块距所述主芯片的下表面的第一边的距离小于距沿所述第一方向延伸并经过所述主芯片的下表面的中心点的第一中心线的距离，以及
其中，所述多个第二凸块中的第二组的第二凸块距所述主芯片的下表面的第二边的距离小于距所述主芯片的下表面的第一中心线的距离。
9.根据权利要求8所述的半导体封装，其中，所述第一组的第二凸块和所述第二组的第二凸块是沿所述第一方向布置的。
10.根据权利要求1所述的半导体封装，
其中，所述多个第二凸块中的第三组的第二凸块距所述主芯片的下表面的第三边的距离小于距沿所述第二方向延伸并经过所述主芯片的下表面的中心点的第二中心线的距离，以及
其中，所述多个第二凸块中的第四组的第二凸块距所述主芯片的下表面的第四边的距离小于距所述主芯片的下表面的第二中心线的距离。
11.根据权利要求10所述的半导体封装，其中，所述第三组的第二凸块和所述第四组的第二凸块是沿所述第二方向布置的。
12.一种半导体封装，包括：
封装基板，包括多个第一上焊盘、与所述多个第一上焊盘相连的多个下焊盘、多个第二上焊盘以及与所述多个第二上焊盘相连的多个第三上焊盘；
多个外部连接，与所述封装基板的所述多个下焊盘相连；
主芯片，在所述封装基板上；
至少一个从芯片，在所述主芯片上；
多个第一凸块，在所述封装基板的所述多个第一上焊盘与所述主芯片之间；
多个第二凸块，在所述封装基板的所述多个第二上焊盘与所述主芯片之间；以及
多根引线，将所述封装基板的所述多个第三上焊盘与所述至少一个从芯片相连，
其中所述封装基板的上表面包括沿第一方向延伸的第一边和第二边以及沿第二方向延伸的第三边和第四边。
13.根据权利要求12所述的半导体封装，其中，所述多个第一上焊盘比所述多个第二上焊盘更靠近沿所述第一方向延伸并经过所述封装基板的上表面的中心点的第一中心线。
14.根据权利要求12所述的半导体封装，其中，所述多个第一上焊盘比所述多个第三上焊盘更靠近沿所述第一方向延伸并经过所述封装基板的上表面的中心点的第一中心线。
15.根据权利要求12所述的半导体封装，其中，所述多个第二上焊盘比所述多个第三上焊盘更靠近沿所述第一方向延伸并经过所述封装基板的上表面的中心点的第一中心线。
16.根据权利要求12所述的半导体封装，
其中，所述多个第三上焊盘中的第一组的第三上焊盘距所述封装基板的上表面的第一边的距离小于距沿所述第一方向延伸并经过所述封装基板的上表面的中心点的第一中心线的距离，
其中，所述多个第三上焊盘中的第二组的第三上焊盘距所述封装基板的上表面的第二边的距离小于距所述封装基板的上表面上的第一中心线的距离。
17.根据权利要求12所述的半导体封装，
其中，所述多个第三上焊盘中的第三组的第三上焊盘距所述封装基板的上表面的第三边的距离小于距沿所述第二方向延伸并经过所述封装基板的上表面的中心点的第二中心线的距离，
其中，所述多个第三上焊盘中的第四组的第三上焊盘距所述封装基板的上表面的第四边的距离小于距所述封装基板的上表面上的第二中心线的距离。
18.根据权利要求12所述的半导体封装，其中，所述多个第一上焊盘比所述多个第三上焊盘更靠近所述封装基板的上表面的中心点。
19.一种半导体封装，包括：
封装基板；
多个外部连接，在所述封装基板下方；
主芯片，在所述封装基板上；
至少一个从芯片，在所述主芯片上；
多个第一凸块和多个第二凸块，在所述封装基板和所述主芯片之间；以及
多根引线，将所述封装基板与所述至少一个从芯片相连；
其中，所述封装基板包括接触所述多个第一凸块的多个第一上焊盘以及接触所述多个第二凸块和所述多根引线的多个第二上焊盘。
20.根据权利要求19所述的半导体封装，其中，所述多个第二上焊盘中的每一个的尺寸大于所述多个第一上焊盘中的每一个的尺寸。
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