CN105742262A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN105742262A
CN105742262A CN201510940505.0A CN201510940505A CN105742262A CN 105742262 A CN105742262 A CN 105742262A CN 201510940505 A CN201510940505 A CN 201510940505A CN 105742262 A CN105742262 A CN 105742262A
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mounting blocks
semiconductor chip
installing device
substrate
conductive material
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CN201510940505.0A
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CN105742262B (zh
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李俊奎
权容台
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Nepes Co Ltd
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Nepes Co Ltd
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Abstract

本发明公开了一种半导体封装，其中，半导体芯片和安装器件一起封装在半导体封装中。半导体封装包括半导体芯片、安装块和互连部件，在安装块上的第一安装器件安装在基板上，基板包括形成在其上的电路，互连部件被配置以将半导体芯片电连接至安装块。

Description

半导体封装及其制造方法
相关申请的交叉引用
本申请要求于2014年12月30日向韩国知识产权局提交的申请号为10-2014-0194450的韩国专利申请的权益，其全部内容在此引入以作参考。
技术领域
本发明的实施例涉及一种半导体封装及其制造方法。更具体地说，本发明的实施例涉及一种半导体芯片和安装器件同时封装在其中的半导体封装及其制造方法。
背景技术
最近，因为由于精细加工技术和功能多样化导致半导体器件的芯片尺寸减小和输入/输出端子的数目增加，所以焊盘(pad)电极的间距正逐渐变得更细。另外，随着各种功能的汇聚加快，用于将多个器件集成在单个封装中的系统级封装技术变得至关重要。此外，系统级封装技术已经发展成用于维持短的信号间隔来最小化操作之间的噪声并提高信号速度的三维堆叠技术，。
半导体封装已经通过使用凸块工艺的倒装芯片方法来制造，凸块工艺用于半导体芯片之间或半导体芯片与基板之间的电连接。然而，这种凸块工艺具有输入/输出焊盘的数量和芯片尺寸由于减小凸块的尺寸的限制而受到限制的问题。
也就是说，当半导体芯片的尺寸减小和输入/输出焊盘的数量增加时，半导体封装具有完全容纳半导体芯片的顶部表面上的多个焊球即输入/输出端子的局限性。为了解决这个问题，半导体封装已被发展为具有嵌入式结构、扇出结构等，在嵌入式结构中，半导体芯片被嵌入在电路板中，在扇出结构中，焊球即半导体芯片的最终输入/输出端子被设置在半导体芯片的外部周向表面上。
同时，当有源器件和无源器件设置在单个封装中时，有源器件和无源器件通常同时安装在一个封装基板上。在此，具有比有源器件端子数量少且间距大的无源器件可通过常规表面安装技术(SMT)简单地安装在低端基板上，但是当无源器件与有源器件同时安装在同一基板上时，需要高端封装基板，这导致封装价格和工艺难度的增加。
另外，当有源器件和无源器件布置在设置在载具上的封装中时，通常使用拾取和放置工艺。在这种情况下，当多个无源器件被包括在封装中时，花费在拾取和放置工艺中的时间增加，其直接导致封装价格的增加。
半导体模块及其方法在韩国未审专利公开第10-2012-0010021号(于2012年2月2日公开)中公开。
现有技术文献
专利文献
韩国未审专利公开第10-2012-0010021号(于2012年2月2日公开)
发明内容
因此，本发明的一方面是提供一种半导体封装及其制造方法，在半导体封装中，包括安装器件的基板与半导体芯片分离地形成。
本发明的其他方面将在随后的说明书中被部分地阐述、将从说明书中显而易见或可通过本发明的实践而得知。
根据本发明的一个方面，半导体封装包括半导体芯片、安装块和互连部件，其中，安装块上的第一安装器件安装在基板上，基板包括形成在其上的电路，互连部件被配置以将半导体芯片电连接至安装块。
半导体封装可进一步包括模塑在半导体芯片和安装块上的密封剂。半导体芯片的焊盘和安装块的导电材料可被暴露在密封剂的一个表面上。互连部件可电连接至半导体芯片的焊盘和安装块的导电材料。
安装块可设置在半导体芯片的外侧上，密封剂可填充半导体芯片和安装块之间的空间以使半导体芯片和安装块成为一体。
安装块可包括包含过孔(viahole)的基板、通过基板的过孔的导电材料和电连接至导电材料的一侧的第一安装器件，导电材料的另一侧可电连接至互连部件。
第一安装器件可包括无源元件。
基板可包括设置在基板的中央部分的开口，半导体芯片可被容纳在开口中并且安装在互连部件上。
基板可包括被配置成围绕半导体芯片的多个基板。
第一安装器件可包括不同类型的安装器件，基板可包括不同类型的基板，在不同类型的基板上安装不同类型的安装器件。
安装块可连接至互连部件以形成容纳半导体芯片的空间，半导体芯片可被容纳在由安装块形成的空间中并且连接至互连部件。
半导体封装可进一步包括第二安装器件，其容纳在由安装块形成的空间中并且连接至互连部件。
半导体封装可进一步包括密封剂，其被模塑在半导体芯片、安装块和第二安装器件上。半导体芯片的焊盘、安装块的导电材料和第二安装器件的导电材料可被暴露在密封剂的一个表面上。互连部件可电连接至半导体芯片的焊盘、安装块的导电材料和第二安装器件的导电材料。
根据本发明的一个方面，半导体封装的制造方法包括将安装器件安装在被配置以形成将要容纳半导体芯片的开口的安装块上，将半导体芯片装载在由装载在载具上的安装块形成的开口中，将密封剂模塑在半导体芯片、安装块和安装器件上以及将互连部件形成在去除载具的表面上以将半导体芯片电连接至安装块。
装载半导体芯片可包括将安装块的表面附接至载具以及将半导体芯片通过由安装块形成的开口装载在载具上，模塑密封剂可包括使设置在载具上的半导体芯片、安装块和安装器件成为一体。
安装块可通过用导电材料涂覆在基板中形成的过孔并将基板的顶部电连接至基板的底部来形成，安装器件可被安装以电连接至安装块的导电材料。
安装块可包括多个安装块，多个安装块可被设置以围绕容纳半导体的开口。
第一安装器件可安装在安装块上，第二安装器件可与半导体芯片一起安装在开口中，开口由装载在载具上的安装块形成。
附图说明
从实施例的下述描述并结合附图，本发明的这些和/或其它方面将变得明显且更容易理解，其中：
图1是说明根据本发明的实施例的半导体封装的结构的剖视图；
图2是说明根据本发明的实施例的板的平面图；
图3是沿图2的线A-A截取的剖视图；
图4是说明板上的电路的形成过程的剖视图；
图5是说明将半导体器件和无源元件安装在电路板上的过程的剖视图；
图6是说明将参照图5描述的安装块和半导体芯片装载在载具上的过程的剖视图；
图7是说明模塑密封剂的过程的剖视图；
图8是说明去除载具状态的剖视图；
图9是说明互连部件的形成过程的剖视图；
图10是说明外部连接端子的形成过程的剖视图；
图11是说明根据本发明的另一个实施例的板的平面图；
图12是说明根据本发明的另一个实施例的半导体封装的结构的剖视图。
具体实施方式
现在将详细地参考本发明的实施例，其示例示出在附图中，其中相似的参考标号始终表示相似的元件。下面的实施例被提供仅仅是为了允许本领域普通技术人员能够实施本发明，并且不旨在限制本发明。本发明可通过其它修改实施例实施。在附图中，为了方便可夸大构成组件的厚度、长度和宽度，省略多余部分的描述以便清楚地描述本发明。在下面的描述中，术语“和/或”包括所列出的项目中的一个或多个的任何和所有组合。
图1是说明根据本发明的实施例的半导体封装1的结构的剖视图，图2是说明根据本发明的实施例的板110的平面图。
参照图1和图2，半导体封装1可包括其上安装有安装器件220和安装器件230的安装块、半导体芯片210、模塑在安装块和半导体芯片210上的密封剂300、将安装块电连接至半导体芯片210的互连部件400和外部连接端子500。
安装块可包括电路板100和安装在电路板100上的安装器件220和安装器件230。电路板100可以是例如印刷电路板(PCB)。
电路板100可通过在绝缘板110中形成过孔111(请参阅图3)、用导电填料120填充过孔111以将板110的顶部电连接至板110的底部以及在板110的一个表面或两个表面上形成电路来形成。同时，板110可由纤维增强玻璃或塑料构成。
将导电填料120与外部绝缘的绝缘层130可形成在板110的两个表面上，绝缘层130的部分可以是开口的以暴露导电填料120。另外，安装器件220和安装器件230或互连层420可连接至暴露导电填料120的部分。例如，安装器件220和安装器件230可连接至暴露在电路板100的一个表面上的导电填料120，互连层420可连接至暴露在电路板100的另一表面上的导电填料120。
过孔111可用作在电路板100的垂直方向传输电信号的通道。过孔111可填充有诸如导电糊膏等导电填料120。同时，过孔111可包括诸如硅穿孔(TSV)等通孔。此外，过孔111可包括多个过孔或必要时可设置在不同位置。
虽然未在图1和图2中示出，但是电路板100可包括焊盘(未示出)，其形成在暴露在绝缘层130中的导电填料120上。焊盘可由包括金属的导电材料构成并且可用于将电信号容易地传输至导电填料120。
安装器件220和安装器件230可安装在电路板100上以形成安装块。一个安装器件或多个安装器件可安装在一个电路板100上。
安装块可形成容纳半导体芯片210的空间112。例如，安装块可包括多个安装块并且多个安装块可被设置以围绕容纳半导体芯片210的空间112。图2说明了四个矩形安装块，其被垂直地设置以在其中央形成空间112。然而，图2仅仅说明了安装块的排列方法的一个实施例，因此可提供安装块的各种排列方法。
同时，在安装块之间形成的空间112被配置以容纳半导体芯片210，优选的是，空间112的宽度大于半导体芯片210的宽度。
半导体芯片210包括半导体集成电路(IC)。半导体IC互连半导体基板中的诸如晶体管、二极管和电阻器等电路器件。另外，半导体芯片210可以是内存芯片或逻辑芯片。例如，内存芯片可包括DRAM、SRAM、闪速存储器、PRAM、ReRAM、FeRAM或MRAM。例如，逻辑芯片可以是控制内存芯片的控制器。
半导体芯片210可包括具有其中形成有电路的有源区域的有源平面212(相对于有源平面212的平面被称为非有源平面213)，配置为与外部器件交换信号的焊盘211可形成在有源平面212上。焊盘211可以是导电材料并且可用作将半导体芯片210连接至外部器件的通道。此外，焊盘211可与半导体芯片210一体成型。
焊盘211可电连接至互连层420。在此，焊盘211和互连层420可通过凸块或导电粘接材料进行连接。例如，焊盘211和互连层420可通过使用包括铅(Pb)或锡(Sn)的金属熔化剂的焊料接合方法来连接。
安装器件220和安装器件230可包括无源元件220或半导体器件230。无源元件220可指消耗、累积或发出向其提供的功率的元件，且可包括电子器件、电阻器、电容器、电感器、变压器、继电器等。此外，半导体器件230可包括二极管、晶体管、整流器等。
同时，安装器件220和安装器件230可包括可安装在电路板100上的各种元件。例如，安装器件220和安装器件230可包括有源元件。
安装器件220和安装器件230可包括焊盘221和焊盘231以与外部器件交换信号。焊盘221和焊盘231可由导电材料构成。
安装在电路板100上的安装器件220和安装器件230可具有比半导体芯片210更少数量的端子和更宽的间距。因此，与其上安装有半导体芯片210的电路板相比，安装器件220和安装器件230可安装在低端电路板上。因此，没有必要将半导体芯片210与安装器件220和安装器件230安装在一个电路板上。因为电路板100根据安装器件220和安装器件230的类型独立地选自半导体芯片210，所以可降低生产成本。
另外，因为电路板100仅形成在其上安装有安装器件220和安装器件230的部分中，所以可最小化电路板100的尺寸，并可降低半导体封装1的尺寸、重量和制造成本。另外，安装器件220和安装器件230可使用表面安装技术(SMT)被安装在电路板100上。
同时，当安装块与多个安装器件220和安装器件230成为一体时，装载过程可通过将半导体芯片210和安装块装载在载具600上来完成(请参阅图6)。因此，与使用拾取-放置工艺单独装载安装器件220和安装器件230的每一个的时间相比，制程时间可减少。另外，因为可选择和安装无缺陷的安装块，所以可防止当利用拾取-放置工艺单独装载安装器件220和安装器件230时出现的问题，并可提高制程良率。
密封剂300可被模塑以使半导体芯片210和安装块成为一体。例如，密封剂300可填充在半导体芯片210和安装块之间的空间中。密封剂300可包括诸如环氧模塑料(EMC)等绝缘材料。
另外，密封剂300可围绕和密封安装块使得安装块不被暴露到外部并且覆盖半导体芯片210和安装块的上表面以保护半导体芯片210和安装块免受外部影响。
同时，半导体芯片210的焊盘211和电路板100的导电填料120可暴露在密封剂300的一个表面上。
互连部件400可将半导体芯片210电连接至安装在安装块上的安装器件220和安装器件230。互连部件400可包括导电材料。例如，互连部件400可包括诸如铜、铜合金、铝或铝合金等金属。此外，互连部件400可通过重新路由(rerouting)金属线而形成。
互连部件400可包括第一绝缘层410，其形成在密封剂300的一个表面上并且包括使半导体芯片210的焊盘211和电路板100的导电填料120暴露的开口；以及互连层420，其形成在第一绝缘层410上以形成互连并连接至半导体芯片210的焊盘211和电路板100的导电填料120。另外，互连部件400可进一步包括第二绝缘层430，其形成在第一绝缘层410和互连层420上。第二绝缘层430可暴露互连层420的部分。
外部连接端子500的一侧可连接至通过第二绝缘层430的开口被暴露的互连层420，外部连接端子500的另一侧可连接至外部基板(未示出)或另一个半导体封装。
虽然焊球在图1中被作为外部连接端子500的一个示例来说明，但是可使用焊接凸块。另外，诸如有机涂覆或金属电镀等表面处理可在外部连接端子500的表面上进行以防止其氧化。例如，有机涂覆可以是有机焊接保护(OSP)涂覆，金属电镀可以是金(Au)、镍(Ni)、铅(Pb)或银(Ag)电镀。
以下，参照图3-12详细地描述根据本发明的实施例的半导体封装1的制造方法。首先参照图3-图5描述设置安装块的过程。
图3是沿图2的线A-A截取的剖视图，图4是说明板110上的电路的形成过程的剖视图，图5是说明将半导体器件230和无源元件220安装在电路板100上的过程的剖视图。
根据本发明的实施例的半导体封装1的安装块可通过形成用于安装安装器件220和安装器件230的电路板100和将安装器件220和安装器件230安装在电路板100上来设置。
在形成电路板100的过程中，板110的顶部和底部可通过用导电填料120填充形成在板110中的过孔来电连接。另外，绝缘层130形成在板110的每个表面上，开口形成在绝缘层130内以暴露导电填料120的部分。
导电填料120可包括导电糊膏。可选地，板110的顶部和底部可通过将导电销插入过孔111中和对过孔111进行金属电镀来电连接。
安装器件220和安装器件230安装在电路板100的一个表面上。将安装器件220和安装器件230安装在电路板100上的过程可利用SMT进行。安装器件220的焊盘221和安装器件230的焊盘231可连接至通过绝缘层130的开口暴露的导电填料120。另外，安装器件220和安装器件230可通过粘合剂等牢固地固定至电路板100。
同时，安装块的中央部分可以是开口的以形成空间112，半导体芯片210可设置在空间112中。例如，多个安装块可被设置以围绕容纳半导体芯片210的空间112。在此，形成在安装块的中央部分中的空间112的宽度可大于半导体芯片210的宽度。半导体芯片210和安装块之间的空间112可填充有将在后面描述的密封剂300，从而可使半导体芯片210和安装块成为一体。
图6是说明将参照图5描述的安装块和半导体芯片210装载在载具600上的过程的剖视图。
粘合剂层610可形成在载具600的表面上。粘合剂层610可以是例如双面胶带。
安装块与半导体芯片210可被装载在载具600的表面上，在载具600的表面上形成粘合剂层610。例如，在安装块固定至粘合剂层610之后，半导体芯片210可通过插入在由安装块形成的开口中固定至粘合剂层610。此外，在半导体芯片210被装载在载具600上之后，可装载安装块。
可装载安装块使得电路板100的与电路板100的其上安装有安装器件220和安装器件230的表面相对的表面朝向载具600。另外，可装载半导体芯片210使得其有源平面212朝向载具600。在此，半导体芯片210的有源平面212是指其中形成有电路和焊盘211的平面。
图7是说明模塑密封剂300的过程的剖视图。
密封剂300可被模塑以使被装载在载具600上的半导体芯片210和安装块成为一体。在这方面，密封剂300可填充半导体芯片210和安装块之间的空间。在此，形成在安装块中的开口的内表面与半导体芯片210的侧表面可优选地彼此间隔开。因为密封剂300渗透并填充空间，所以半导体芯片210和安装块可被牢固地固定。
同时，密封剂300可密封安装块以包围安装块的外侧并且覆盖半导体芯片210与安装器件220和安装器件230的上部分。即，在密封剂300被模塑在载具600上之后，半导体芯片210的非有源平面213与安装器件220和安装器件230的上表面可不暴露于外部。
可选地，密封剂300可以这种方式模塑使得半导体芯片210的非有源平面213或安装器件220和安装器件230的上表面暴露于外部。例如，密封剂300可被模塑为具有与半导体芯片210与安装器件220和安装器件230的上表面的较高的一个相同的高度以最小化半导体封装1的高度。可选地，在密封剂300被模塑以覆盖半导体芯片210与安装器件220和安装器件230之后，半导体芯片210的非有源平面213或安装器件220和安装器件230的上表面可利用研磨工艺来暴露。
图8是说明将载具600从电路板100去除的状态的剖视图，图9是说明互连部件400的形成过程的剖视图。
参照图8和图9，当固化密封剂300时，载具600和粘合剂层610被去除，互连部件400形成在已经去除载具600和粘合剂层610的表面上。安装块与半导体芯片210可暴露在去除载具600和粘合剂层610的表面上。更具体地说，可暴露其上未安装安装器件220和安装器件230的电路板100的表面和半导体芯片210的有源平面212。
可选地，在将半导体芯片210和安装块装载在载具600上的过程期间，电路板100的表面和半导体芯片210的有源平面212可使用凸块等与载具600分离。这种情况下，密封剂300可渗透到载具600与半导体芯片210和安装块之间的空间中，从而即使在去除载具600之后，半导体芯片210和安装块可能不被暴露在密封剂300的表面上。然而，即使在这种情况下，因为凸块等通过密封剂300的表面暴露，所以互连层420可电连接至半导体芯片210和安装器件220和安装器件230。
将详细地描述形成互连部件400的过程。
首先，第一绝缘层410形成在已经去除载具600的表面上。在此，第一绝缘层410可形成以暴露电路板100的导电填料120的一部分和半导体芯片210的焊盘211。可使用蚀刻工艺以暴露第一绝缘层410的部分。同时，不包括暴露区域的第一绝缘层410可通过使用掩模工艺等形成。
在形成第一绝缘层410后，可形成互连层420。互连层420可通过重新路由工艺形成电路并可将半导体芯片210的焊盘211电连接至电路板100的导电填料120。
最后，形成第二绝缘层430。第二绝缘层430可形成在第一绝缘层410和互连层420上并可暴露互连层420的一部分。通过第二绝缘层430暴露的互连层420可电连接至外部电路。
图10是说明外部连接端子500的形成过程的剖视图。
外部连接端子500附接至第二绝缘层430并且连接至互连层420的暴露的部分。外部连接端子500可利用导电粘合剂材料附接。
通过外部连接端子500的附接，半导体芯片210与安装器件220和安装器件230可通过互连层420和外部连接端子500电连接至外部电路。
图11是说明根据本发明的另一个实施例的板110-1的平面图。
根据本发明的实施例的板110-1可包括在其中央部分的插入半导体芯片210的开口。例如，板110-1可具有四方形状，根据半导体芯片210的形状的穿过板110-1的开口112可形成在板110-1的中央部分。
半导体封装1的形成过程可在高温下进行。特别地，因为互连部件400的形成过程通常在高温下进行，所以可能发生密封剂300的变形。在此，可通过以一体的形式形成板110-1使密封剂300的变形最小化。因此，在互连层420的形成过程中，互连层420可形成以匹配半导体芯片210的焊盘211和电路板100的导电填料120的通过密封剂300暴露的细间距。
图12是说明根据本发明的另一个实施例的半导体封装2的结构的剖视图。
在根据本发明的实施例的半导体封装2中，另一个安装器件240可与半导体芯片210一起被装载在安装块之间的空间112中。在此，安装在电路板100上的元件被称为第一安装器件220和第一安装器件230，装载在安装块之间的空间112中的安装器件240被称为第二安装器件240。
第二安装器件240可直接连接至互连层420，就像半导体芯片210一样。即，第二安装器件240的焊盘241可连接至通过第一绝缘层410暴露的互连层420。
此外，密封剂300使其上安装有半导体芯片210和第一安装器件220和第一安装器件230的安装块和第二安装器件240成为一体。例如，密封剂300可填充在半导体芯片210和第二安装器件240之间和第二安装器件240和安装块之间的空间。
同时第二安装器件240的高度可大于第一安装器件220和第一安装器件230的高度。半导体封装2的总高度可通过将具有相对小高度的第一安装器件220和第一安装器件230安装在电路板100上和将具有相对大高度的第二安装器件240安装在互连部件400上来减小。与根据图1中说明的实施例的半导体封装1相比，可以看出，半导体封装2的总高度小于半导体封装1的总高度。
从上面描述中明显的是，在根据本发明的实施例的半导体封装及半导体封装的制造方法中，安装器件与半导体芯片分离地安装。因此，半导体封装的总成本可通过降低其上安装有安装块的基板的价格和减小用于安装安装器件的制程时间来降低。
另外，因为半导体芯片电连接至安装器件，而无需安装在基板上，所以可减小半导体封装的高度，且可降低半导体封装的重量和价格。
此外，因为具有大高度的安装器件安装在其中安装有半导体芯片的由安装块形成的空间中，所以可减小半导体封装的总高度。
虽然已经示出和描述了本发明的一些实施例，但是本领域技术人员将理解的是，在不脱离本发明的原理和精神的前提下，可对这些实施例进行改变，本发明的范围由权利要求和它们的等同对象限定。

Claims (16)

1.一种半导体封装，其包括：
半导体芯片；
安装块，在其上的第一安装器件安装在基板上，所述基板包括形成在所述基板上的电路；以及
互连部件，其被配置以将所述半导体芯片电连接至所述安装块。
2.根据权利要求1所述的半导体封装，其进一步包括模塑在所述半导体芯片和所述安装块上的密封剂，其中：
所述半导体芯片的焊盘和所述安装块的导电材料被暴露在所述密封剂的一个表面上；以及
所述互连部件电连接至所述半导体芯片的所述焊盘和所述安装块的所述导电材料。
3.根据权利要求2所述的半导体封装，其中：
所述安装块设置在所述半导体芯片的外侧上；以及
所述密封剂填充所述半导体芯片和所述安装块之间的空间以使所述半导体芯片和所述安装块成为一体。
4.根据权利要求1所述的半导体封装，其中：
所述安装块包括包含过孔的基板、穿过所述基板的过孔的导电材料和电连接至所述导电材料的一侧的所述第一安装器件；以及
所述导电材料的另一侧电连接至所述互连部件。
5.根据权利要求1所述的半导体封装，其中所述第一安装器件包括无源元件。
6.根据权利要求1所述的半导体封装，其中：
所述基板包括设置在所述基板的中央部分的开口；以及
所述半导体芯片被容纳在所述开口中并且安装在所述互连部件上。
7.根据权利要求1所述的半导体封装，其中所述基板包括多个基板，所述多个基板被配置成围绕所述半导体芯片。
8.根据权利要求7所述的半导体封装，其中：
所述第一安装器件包括不同类型的安装器件；以及
所述基板包括不同类型的基板，在所述不同类型的基板上安装所述不同类型的安装器件。
9.根据权利要求1所述的半导体封装，其中：
所述安装块连接至所述互连部件，所述安装块被设置以形成容纳所述半导体芯片的空间；以及
所述半导体芯片被容纳在由所述安装块形成的所述空间中并且连接至所述互连部件。
10.根据权利要求9所述的半导体封装，其进一步包括第二安装器件，所述第二安装器件容纳在由所述安装块形成的所述空间中并且连接至所述互连部件。
11.根据权利要求10所述的半导体封装，其进一步包括密封剂，所述密封剂被模塑在所述半导体芯片、所述安装块和所述第二安装器件上，其中：
所述半导体芯片的焊盘、所述安装块的导电材料和所述第二安装器件的导电材料被暴露在所述密封剂的一个表面上；以及
所述互连部件电连接至所述半导体芯片的所述焊盘、所述安装块的所述导电材料和所述第二安装器件的所述导电材料。
12.一种半导体封装的制造方法，其包括：
将安装器件安装在安装块上，所述安装块被配置以形成开口，半导体芯片将被容纳在所述开口中；
将所述半导体芯片装载在由装载在载具上的所述安装块形成的所述开口中；
将密封剂模塑在所述半导体芯片、所述安装块和所述安装器件上；以及
将互连部件形成在去除所述载具的表面上以将所述半导体芯片电连接所述安装块。
13.根据权利要求12所述的方法，其中：
装载所述半导体芯片包括将所述安装块的表面附接至所述载具以及将所述半导体芯片通过由所述安装块形成的所述开口装载在所述载具上；以及
模塑所述密封剂包括使设置在所述载具上的所述半导体芯片、所述安装块和所述安装器件成为一体。
14.根据权利要求12所述的方法，其中：
所述安装块通过用导电材料涂覆在基板中形成的过孔并将所述基板的顶部电连接至所述基板的底部来形成；以及
所述安装器件被安装以电连接至所述安装块的所述导电材料。
15.根据权利要求12所述的方法，其中所述安装块包括多个安装块，所述多个安装块被设置以围绕容纳半导体的开口。
16.根据权利要求12所述的方法，其中：
第一安装器件安装在所述安装块上；以及
第二安装器件与所述半导体芯片一起安装在所述开口中，所述开口由装载在所述载具上的所述安装块形成。
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