TWI584446B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TWI584446B
TWI584446B TW104140268A TW104140268A TWI584446B TW I584446 B TWI584446 B TW I584446B TW 104140268 A TW104140268 A TW 104140268A TW 104140268 A TW104140268 A TW 104140268A TW I584446 B TWI584446 B TW I584446B
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mounting
semiconductor wafer
mounting block
component
semiconductor
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TW104140268A
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TW201635480A (zh
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李俊奎
權容台
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Ｎｅｐｅｓ股份有限公司
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Description

半導體封裝及其製造方法 交叉引用相關申請
本申請主張韓國專利申請案No.10-2014-0194450的權益，該專利申請案為2014年12月30日在韓國智財局提申，其揭露的內容在此引用作為參考。
本發明的實施例是關於半導體封裝及其製造方法。更具體地說，本發明的實施例是關於一種半導體封裝以及其製造方法，其中半導體晶片與安裝元件被同時封裝。
近年來，由於微細加工技術與功能的多樣化，半導體元件的晶片尺寸變小且輸入/輸出終端的數目增加，使得電極墊之間的間距逐漸變小。另外，隨著各種功能的整合速度加快，用於整合複數個元件在單一封裝中的系統級封裝技術是日益重要。此外，系統級封裝技術已發展為三維堆疊技術，用於維持較短的信號間隔，以減少操作之間的雜訊與增進信號速度。
使用凸塊(bumping)製程進行半導體晶片之間或半導體晶片與基板之間的電性連接，藉由覆晶(flip-chip)方 法製造半導體封裝。然而，此種凸塊製程的問題是輸入/輸出墊的數目與晶片尺寸是有限的，來自於需減小凸塊尺寸的限制。
也就是說，當半導體晶片的尺寸變小與輸入/輸出墊的數目增加，半導體封裝的限制在於需在半導體晶片的上表面完全容納複數個焊球，即，輸入/輸出端。為了解決此問題，半導體封裝已發展為具有嵌入式結構與扇出(fan-out)結構，其中半導體晶片被嵌入在電路板中，扇出結構中的焊球，即，半導體晶片的最終輸入/輸出端被佈置在半導體晶片的外周圍表面，或諸如此類。
同時，當主動元件與被動元件被佈置在單個封裝中，主動元件與被動元件一般被同時安裝在一封裝基板上。在此，比起主動元件，被動元件具有少量的端子以及較大的間距，可以簡單地透過一般表面安裝技術(SMT)將其安裝在一低階基板上，但是，當被動元件與主動元件被安裝在同一基板上，則需要高階封裝基板，這將會導致封裝成本與製程難度的增加。
另外，當主動元件與被動元件被佈置在載體上的一封裝，通常使用取放(pick-and-placement)製程。在這種情況下，當複數個被動元件被包括在一封裝中，用在取放製程的時間會增加，直接導致封裝成本增加。
半導體模組與其方法揭露於韓國未經審查的專利公開號No.10-2012-0010021(於2012年2月2日公開)。
現有技術文獻
專利文件
韓國未審查專利公開號No.10-2012-0010021(於2012年 2月2日公開)
因此，本發明的一個樣態是提供一種半導體封裝以及其製造方法，半導體封裝為包括一安裝元件的一基板獨立於一半導體晶片而形成。
本發明的其他樣態將在隨後的說明中逐步闡述，並且逐步地從說明中更顯而易見，或者可通過本發明的實踐而得知。
根據本發明的一個樣態，一半導體封裝包括：一半導體晶片、一安裝塊以及一互連部分。在該安裝塊其上為一第一安裝元件被安裝在一基板上，該基板包括形成在其上的一電路。該互連部分被配置為將該半導體晶片電性連接到該安裝塊。
該半導體封裝更包括：一封裝膠，該封裝膠模製在該半導體晶片與該安裝塊上。該半導體晶片的一墊與該安裝塊的一導電材料可暴露在該封裝膠的一表面。該互連部分可電性連接到該半導體晶片的該墊與該安裝塊的該導電材料。
該安裝塊可設置在該半導體晶片的一外側，且該封裝膠可填充在該半導體晶片與該安裝塊之間的一空間以整合該半導體晶片與該安裝塊。
該安裝塊可包括：一基板，該基板包括一通孔，一導電材料通過該基板的該通孔，且該第一安裝元件電性連接到該導電材料的一側，並且該導電材料的另一側電性連接到該互連部分。
該第一安裝元件可包括一被動元件。
該基板可包括配置在其中心部分的一開口，且該半導體晶片可容納在該開口中並安裝在該互連部分上。
該基板可包括複數個基板，該些基板被配置成包圍該半導體晶片。
該第一安裝元件可包括不同類型的安裝元件，且該基板可包括不同類型的基板，該基板上可安裝不同類型的安裝元件。
該安裝塊可被連接到該互連部分，以形成容納該半導體晶片的一空間，並且該半導體晶片可被容納在由該安裝塊所形成的該空間中且被連接到該互連部分。
該半導體封裝更包括一第二安裝元件，該第二安裝元件容納在由該安裝塊所形成的該空間中且被連接到該互連部件。
該半導體封裝件更包括一封裝膠，該封裝膠模製在該半導體晶片、該安裝塊以及該第二安裝元件上。該半導體晶片的一墊、該安裝塊的一導電材料以及該第二安裝元件的一導電材料被暴露在該封裝膠的一表面。該互連部分可電性連接到該半導體晶片的該墊、該安裝塊的該導電材料以及該第二安裝元件的該導電材料。
根據本發明的一個樣態，一種製造半導體封裝的方法包括：在一安裝塊上安裝一安裝元件，該安裝塊裝配為形成一開口，該開口容納該半導體晶片；在一載體上由該安裝塊所形成的該開口中裝載該半導體晶片；模製一封裝膠在該半導 體晶片、該安裝塊以及該安裝元件上，並在移除該載體的一表面上形成一互連部分，以電性連接該半導體晶片到該安裝塊。
該半導體晶片的裝載可包括：附著該安裝塊的一表面到該載體，且在該載體上經由該安裝塊所形成的該開口中裝載該半導體晶片，以及封裝膠的模製可包括：整合配置在該載體上的該半導體晶片、該安裝塊以及該安裝元件。
該安裝塊可經由以一導電材料塗布形成在一基板中的一通孔，且該通孔電性連接到該基板的一頂部與該基板的一底部，該安裝元件可被安裝以電性連接該安裝塊的該導電材料。
安裝塊可包括複數個安裝塊，且該些安裝塊可被佈置成圍繞該開口，該開口中容納有該半導體晶片。
一第一安裝元件可被安裝在該安裝塊上，以及一第二安裝元件可以與該半導體晶片一起裝載在該開口中，該開口由在該載體上裝載的該安裝塊而形成。
1‧‧‧半導體封裝
2‧‧‧半導體封裝
100‧‧‧電路板
110‧‧‧板
110-1‧‧‧板
111‧‧‧通孔
112‧‧‧空間
120‧‧‧導電填料
130‧‧‧絕緣層
210‧‧‧半導體晶片
211‧‧‧墊
212‧‧‧主動面
213‧‧‧惰性面
220‧‧‧安裝元件
221‧‧‧墊
230‧‧‧安裝元件
231‧‧‧墊
240‧‧‧第二安裝元件
241‧‧‧墊
300‧‧‧封裝膠
400‧‧‧互連部分
410‧‧‧第一絕緣層
420‧‧‧互連層
430‧‧‧第二絕緣層
500‧‧‧外部連接端子
600‧‧‧載體
610‧‧‧黏著劑
本發明的這些與/或其他樣態，從下列實施例與結合其中的附圖的說明將更顯而易見且更容易理解：圖1繪示根據本發明實施例的半導體封裝結構的剖面圖；圖2繪示根據本發明實施例的板的平面圖；圖3是沿圖2中的線A-A所截取的剖面圖；圖4繪示形成在板上的電路的製程剖面圖；圖5繪示在電路板上安裝半導體元件與被動元件的製程剖面圖； 圖6繪示在載體上裝載參照圖5的安裝塊與半導體晶片的製程剖面圖；圖7繪示模製封裝膠的製程剖面圖；圖8繪示載體被移除狀態的剖面圖；圖9繪示形成內連部分的製程剖面圖；圖10繪示形成外部連接端子的製程剖面圖；圖11繪示根據本發明另一實施例的板的平面圖；以及圖12繪示根據本發明另一實施例的半導體封裝結構的剖面圖。
現在將詳細地說明本發明的實施例，其為繪示在附圖中的例子，其中類似的元件會重頭到尾使用類似的參考符號。下面的實施例僅為提供本領域的普通技術人員實現本發明，且意味著不限制本發明。本發明可透過其他修改的實施例體現。在附圖中，組成構件的厚度、長度以及寬度可能被誇大以方便說明，並且多餘部分的描述也被省略，以便清楚地說明本發明。在以下的說明中，術語「與/或」包括一個或多個列出的項目的任意組合與所有組合。
圖1繪示根據本發明實施例的半導體封裝1的結構的剖面圖，且圖2繪示根據本發明實施例的板110的平面圖。
參考圖1與圖2，半導體封裝1可包括在其上安裝安裝元件220與230的安裝塊、半導體晶片210、模製在安裝塊與半導體晶片210上的封裝膠300、電性連接安裝塊到半導體晶片210的互連部分400，以及外部連接端子500。
安裝塊可包括電路板100與安裝在電路板100上的安裝元件220與230。電路板100可以是，例如，為印刷電路板(PCB)。
可藉由在絕緣板110中形成通孔111(請參閱圖3)、以導電填料120填充通孔111以電性連接板110的頂端到板110的底端，以及在板110的兩表面或一表面上形成一電路，以形成電路板100。同時，板110可由纖維增強的玻璃或塑膠形成。
從外部隔絕導電填料120的絕緣層130可形成在板110的兩個表面上，且部分的絕緣層130是開放的，以暴露導電填料120。另外，安裝元件220與230或互連層420可連接到暴露的導電填料120的部分。例如，安裝元件220與230可被連接到在電路板100的一表面上暴露的導電填料120，且互連層420可被連接到在電路板100的另一表面上暴露的導電填料120。
通孔111可作為路徑，用以在電路板100的垂直方向傳送電訊號。通孔111可填充導電填料120，例如導電膏。同時，通孔111可包括通孔，例如為貫通矽(TSV)的通孔。此外，如所需，通孔111可包括複數個通孔，或者可被佈置在不同的位置。
雖然在圖1與圖2中未繪示，電路板100可包括墊(未繪示)，墊形成在絕緣層130所暴露的導電填料120上。墊可由包括金屬的導電材料所形成，且可容易地傳送電訊號到導電填料120。
安裝元件220與230可被安裝在電路板100上， 以形成安裝塊。安裝元件或複數個安裝元件可被安裝在電路板100上。
安裝塊可形成空間112，其中空間112容納半導體晶片210。例如，安裝塊可包括複數個安裝塊，且複數個安裝塊可被佈置成圍繞容納半導體晶片210的空間112。圖2繪示四個垂直地設置的矩形安裝塊，以在其中心形成空間112。然而，圖2僅繪示了佈置安裝塊的一方法的一實施例，因此，也可提供佈置安裝塊的各種方法。
同時，形成在安裝塊之間的空間112被配置為容納半導體晶片210，最佳地，空間112的寬度比半導體晶片210的寬度還大。
半導體晶片210包括半導體積體電路(IC)。半導體積體電路將電路元件在半導體基板上互連，例如將電晶體、二極體以及電阻互連。另外，半導體晶片210可以是記憶體晶片或邏輯晶片。例如，記憶體晶片可包括動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、相變隨機存取記憶體(PRAM)、電阻式隨機存取記憶體(ReRAM)、鐵電隨機存取記憶體(FeRAM)或磁阻式隨機存取記憶體(MRAM)。例如，邏輯晶片可以是控制記憶體晶片的控制器。
半導體晶片210可包括具主動區域的主動面212，其中形成電路(相對於主動面212的平面被稱為惰性面213)，配置成與外部元件交換訊號的墊211可形成在主動面212上。墊211可為導電材料，並且可作為連接半導體晶片210到外部 元件的路徑。此外，墊211可與半導體晶片210一體成形。
墊211可被電性連接到互連層420，在此，墊211與互連層420可藉由凸塊或導電黏接劑材料連接。例如，可藉由焊接方法使用包括鉛(Pb)或錫(Sn)的金屬熔化劑，墊211與互連層420進行連接。
安裝元件220與230可包括被動元件220或半導體元件230。被動元件220可以指消耗、累積，或向其發射電力的元件，且被動元件220包括電子元件、電阻、電容、電感、變壓器以及繼電器，或類似物。此外，半導體元件230可包括二極體、電晶體、整流器或類似物。
同時，安裝元件220與230可包括各種可以被安裝在電路板100上的元件。例如，安裝元件220與230可包括主動元件。
安裝元件220與230可包括墊221和231，以與外部元件交換訊號。墊221與231可由導電材料形成。
安裝在電路板100上的安裝元件220與230具有較少數目的端子且具有比半導體晶片210更寬的間距。於是，安裝元件220與230可被安裝在低階電路板(相對於在其上安裝半導體晶片210的電路板)上。因此，沒必要同時在電路板上安裝半導體晶片210以及安裝元件220與230。由於電路板100取決於安裝元件220與230的類型，與半導體晶片210無關，因此可降低生產成本。
此外，由於電路板100僅在安裝元件220與230被安裝的部分形成，因此可最小化電路板100的尺寸，且可降低 半導體封裝1的尺寸、重量以及製造成本。另外，安裝元件220與230可使用表面安裝技術(SMT)被安裝在電路板100上。
同時，當安裝塊與複數個安裝元件220與230被整合時，加載製程可藉由在載體600上裝載半導體晶片210與安裝塊(請參閱圖6)而完成。因此，可縮短製程時間(與以拾取製程個別裝載每個安裝元件220與230的時間相比)。另外，由於沒有缺陷的安裝塊可被選擇並安裝，可防止使用拾取製程個別裝載安裝元件220與230的問題發生，可改善良率。
封裝膠300可被模製以整合半導體晶片210與安裝塊。例如，封裝膠300可填充在半導體晶片210與安裝塊之間的空間。封裝膠300可包括絕緣材料，諸如環氧模製化合物(EMC)。
另外，封裝膠300可圍繞與密封安裝塊，使得安裝塊不會被暴露到外部中，且覆蓋半導體晶片210的上表面與安裝塊，以保護半導體晶片210與安裝塊不受外界影響。
同時，半導體晶片210的墊211與電路板100的導電填料120被暴露在封裝膠300的一個表面。
互連部分400可與半導體晶片210以及安裝在安裝塊上的安裝元件220與230電性連接。互連部分400可包括導電材料。例如，互連部分400可包括金屬，如銅、銅合金、鋁或鋁合金。此外，互連部分400可藉由繞道(reroute)製程的金屬線而形成。
互連部分400可包括第一絕緣層410與互連層420，第一絕緣層410形成在封裝膠300的一表面上且暴露出 包括半導體晶片210的墊211以及電路板100的導電填料120的一開口，互連層420形成在第一絕緣層410上，以形成半導體晶片210的墊211與電路板110的導電填料120之間的互連及連接。此外，互連部分400更包括第二絕緣層430，第二絕緣層430形成在第一絕緣層410與互連層420上。第二絕緣層430可暴露部分的互連層420。
外部連接端子500的一側可連接到穿過第二絕緣層430的開口而暴露的互連層420，以及外部連接端子500的另一側可以連接到外部基板(未繪示)或另一半導體封裝。
雖然在圖1中焊球被繪示為外部連接端子500的一個例子，也可使用焊錫凸塊。另外，進行表面處理，如有機塗層或電鍍金屬，也可在外部連接端子500的表面上執行，以防止其氧化。例如，有機塗層可以是有機焊料保存(OSP)塗層，且電鍍金屬可以是金(Au)、鎳(Ni)、鉛(Pb)，或銀(Ag)電鍍。
以下，將參照圖3至圖12，詳細說明根據本發明實施例的半導體封裝1的製造方法。首先，參照圖3至圖5，說明提供安裝塊的製程。
圖3是沿圖2的線A-A截取的剖面圖。圖4是在板110上形成電路的製程剖面圖。圖5繪示在電路板100上安裝半導體元件230與被動元件220的製程剖面圖。
可藉由形成電路板100(用於安裝安裝元件220與230)以及在電路板100上安裝安裝元件220與230來提供根據本發明實施例的半導體封裝1的安裝塊。
在形成電路板100的製程中，板110的頂面與底 面可藉由填充通孔而電性連接，通孔以導電填料120形成在板110中。另外，絕緣層130形成在板110的每個表面上，且在絕緣層130形成開口以暴露部分的導電填料120。
導電填料120可包括導電膏。二擇一地，板110的頂部與底部可藉由在通孔111中插入導電銷而電性連接，以及在通孔111進行金屬電鍍。
安裝元件220與230被安裝在電路板100的一表面上。在電路板100上安裝安裝元件220與230的製程可使用表面安裝製程(SMT)進行。安裝元件220與230的墊221與墊231可被連接到穿過絕緣層130的開口而暴露的導電填料120。此外，藉由黏著劑或類似物，安裝元件220與230可被牢固地固定在電路板100上。
同時，安裝塊的中心部分可以是開放的，以形成空間112，且半導體晶片210可設置在空間112。例如，複數個安裝塊可被佈置為圍繞容納半導體晶片210的空間112。在此，形成在安裝塊的中心部分的空間112的寬度可能會比半導體晶片210的寬度還寬。在半導體晶片210與安裝塊之間的空間112可填充封裝膠300，稍後會說明此製程，因此半導體晶片210與安裝塊可被整合。
圖6繪示在載體600上裝載參照圖5說明的安裝塊與半導體晶片210的製程剖面圖。
可在載體600的表面上形成黏著劑610。黏著劑610，例如，可為雙面膠帶。
安裝塊與半導體晶片210可被裝載在載體600的 表面上，在載體600的表面上形成黏著劑610。例如，在安裝塊固定到黏著劑610後，半導體晶片210可藉由被插入到安裝塊所形成的開口中而被固定到黏著劑610。另外，在半導體晶片210被裝載在載體600上之後，可裝載安裝塊。
安裝塊可被裝載，使得相對於電路板100一表面(安裝元件220與230被安裝的表面)的電路板100的另外一表面面對載體600。此外，半導體晶片210可被裝載，使得其主動面212面向載體600。在此，半導體晶片210的主動面212是指其中形成有電路與墊211的平面。
圖7繪示模製封裝膠300的製程剖面圖。
封裝膠300可被模製以整合半導體晶片210與安裝塊(兩者被裝載到載體600上)。在此，封裝膠300可填充在半導體晶片210與安裝塊之間的空間。在此，最佳的是，形成在安裝塊的開口的內面與半導體晶片210的側面為彼此間隔分離。由於封裝膠300滲透並填充在空間中，半導體晶片210與安裝塊可被牢固地固定。
同時，封裝膠300可密封安裝塊以包圍安裝塊的外側，並覆蓋半導體晶片210的上部以及安裝元件220與230。也就是說，在封裝膠300被模製在載體600上之後，半導體晶片210的惰性面213以及安裝元件220與230的上表面不會被暴露到外界。
二擇一地，封裝膠300可被模製，使得半導體晶片210的惰性面213或安裝元件220與230的上表面被暴露到外界。例如，封裝膠300可被模製為具有相同高度(比半導體 晶片210的上表面或安裝元件220與230的上表面中較高的一個)，以最小化半導體封裝1的高度。二擇一地，在封裝膠300被模製以覆蓋半導體晶片210以及安裝元件220與230之後，半導體晶片210的惰性面213或安裝元件220與230的上表面可使用研磨製程來暴露。
圖8繪示一個狀態的剖面圖，其中載體600從電路板100移除，以及圖9繪示形成互連部分400的製程剖面圖。
參考圖8與圖9，當封裝膠300固化時，載體600與黏著劑610被去除，並且從載體600與黏著劑610被去除的表面上形成互連部分400。安裝塊與半導體晶片210可從載體600與黏著劑610被去除的表面上露出。更具體地說，電路板100的表面(未安裝安裝元件220與230的表面)與半導體晶片210的主動面212可被暴露。
二擇一地，在載體600上裝載半導體晶片210與安裝塊的製程中，電路板100的表面與半導體晶片210的主動面212可以從載體600使用凸塊或類似物分離。在這種情況下，封裝膠300可滲透到載體600、半導體晶片210以及安裝塊之間的空間，因而即使之後載體600被移除，半導體晶片210與安裝塊不會暴露在封裝膠300的表面上。然而，即使在這種情況下，由於凸塊或類似物會經由封裝膠300的表面暴露出來，互連層420可被電性連接到半導體晶片210以及安裝元件220與230。
將詳細說明形成互連部分400的製程。
首先，第一絕緣層410形成在載體600已被移除的表面上。在此，第一絕緣層410可被形成以暴露在電路板100 的導電填料120的一部分以及暴露半導體晶片210的墊211。蝕刻製程可用以暴露部分的第一絕緣層410。同時，藉由使用掩模製程或類似製程，第一絕緣層410可避開暴露的區域而形成。
在形成第一絕緣層410之後，可形成互連層420。互連層420可經由繞道(reroute)製程形成電路，並且可電性連接半導體晶片210的墊211到電路板100的導電填料120。
最後，形成第二絕緣層430。第二絕緣層430可形成在第一絕緣層410與互連層420上，且可暴露部分的互連層420。透過第二絕緣層430暴露的互連層420可被電性連接到外部電路。
圖10繪示形成外部連接端子500的製程剖面圖。
外部連接端子500被附著到第二絕緣層430且連接到互連層420的暴露部分。可使用導電膠材料使外部連接端子500被附著。
藉由外部連接端子500的附著，半導體晶片210以及安裝元件220與230可電性連接到外部電路(經由互連層420與外部連接端子500)。
圖11繪示根據本發明另一實施例的板110-1的平面圖。
根據本發明實施例的板110-1可包括開口，其中，半導體晶片210被插入在其中心部分。例如，板110-1可具有四角形狀，且通過板110-1(根據半導體晶片210的形狀)的開口112可在板110-1的中心部分形成。
形成半導體封裝1的製程可在高溫下進行。特別 是，形成互連部分400的製程通常在高溫下執行，可能會出現封裝膠300變形的情況。在此，可藉由以整合形式形成板110-1，而最小化封裝膠300的變形。因此，在形成互連層420的製程中，互連層420可被形成以匹配在半導體晶片210的墊211以及電路板100的導電填料120等的微小間距，其藉由封裝膠300暴露出來。
圖12繪示根據本發明另一實施例的半導體封裝2的結構剖面圖。
根據本發明實施例的半導體封裝2中，另一個安裝元件240可與半導體晶片210一起被加載在安裝塊之間的空間112。在此，安裝在電路板100上的元件稱為第一安裝元件220與230，以及加載在安裝塊之間的空間112中的安裝元件240被稱為第二安裝元件240。
第二安裝元件240可直接連接到互連層420，就像半導體晶片210一樣。也就是說，第二安裝元件240的墊241可被連接到經由第一絕緣層410暴露出的互連層420。
此外，封裝膠300可整合安裝塊與第二安裝元件240，安裝塊上安裝有半導體晶片210以及第一安裝元件220與230。例如，封裝膠300可填充在半導體晶片210與第二安裝元件240之間的空間以及第二安裝元件240與安裝塊之間的空間。
同時，第二安裝元件240的高度可以比第一安裝元件220與230的高度更高。藉由安裝相對矮的第一安裝元件220與230到電路板100上，且在互連部分400上安裝相對高 的第二安裝元件240，可降低半導體封裝2的總高度。與根據圖1所示的半導體封裝1相比，可以看出半導體封裝2的總高度小於半導體封裝1。
如從上述描述中，根據本發明實施例的半導體封裝及其製造方法顯而易見，其中，安裝元件與半導體晶片分開安裝。因此，可藉由降低基板(其上安裝有安裝塊)的價格而降低半導體封裝的總成本，以及減少安裝該些安裝元件的製程時間。
此外，由於半導體晶片被電性連接到安裝元件而沒有被安裝在基板上，可降低半導體封裝的高度，且可降低半導體封裝的重量與價格。
另外，由於較高的安裝元件被裝在由安裝塊(其中安裝有半導體晶片)所形成的空間中，可降低半導體封裝的總高度。
雖然本發明的幾個實施例已被繪示與說明，但對那些本領域技術人員而言，在不脫離本發明的原理與精神下，實施例的變化是可理解的。本發明的範疇定義在申請專利範圍及其等同物中。
1‧‧‧半導體封裝
100‧‧‧電路板
110‧‧‧板
120‧‧‧導電填料
130‧‧‧絕緣層
210‧‧‧半導體晶片
211‧‧‧墊
212‧‧‧主動面
213‧‧‧惰性面
220‧‧‧安裝元件
221‧‧‧墊
230‧‧‧安裝元件
231‧‧‧墊
300‧‧‧封裝膠
400‧‧‧互連部分
410‧‧‧第一絕緣層
420‧‧‧互連層
430‧‧‧第二絕緣層
500‧‧‧外部連接端子

Claims (12)

  1. 一種半導體封裝，包括：一半導體晶片；一安裝塊，在其上一第一安裝元件被安裝在一基板上，該基板包括形成在其上的一電路與一通孔，一導電材料通過該基板的該通孔，且該第一安裝元件被電性連接到該導電材料的一側，該安裝塊被設置在該半導體晶片的一外側，該第一安裝元件包括一被動元件；一封裝膠，模製在該半導體晶片與該安裝塊上，且填充在該半導體晶片與該安裝塊之間的一空間，以整合該半導體晶片與該安裝塊；以及一互連部分，電性連接該導電材料的另一側，配置為將該半導體晶片電性連接到該安裝塊，其中：該半導體晶片的一墊與該安裝塊的該導電材料，被暴露在該封裝膠的一表面上；以及該互連部分被電性連接到該半導體晶片的該墊與該安裝塊的該導電材料。
  2. 如申請專利範圍第1項的半導體封裝，其中：該基板包括佈置在其中心部分的一開口；以及該半導體晶片被容納在該開口中且被安裝在該互連部分上。
  3. 如申請專利範圍第1項的半導體封裝，其中該基板包括複數個基板，該些基板裝配為圍繞該半導體晶片。
  4. 如申請專利範圍第3項的半導體封裝，其中： 該第一安裝元件包括不同類型的安裝元件；以及該基板包括不同類型的基板，在其上安裝有不同類型的安裝元件。
  5. 如申請專利範圍第1項的半導體封裝，其中：該安裝塊被連接到該互連部分，該安裝塊被設置以形成一空間，該空間中容納該半導體晶片；以及該半導體晶片被容納在由該安裝塊所形成的該空間中且被連接到該互連部分。
  6. 如申請專利範圍第5項的半導體封裝，更包括一第二安裝元件，該第二安裝元件容納在由該安裝塊所形成的該空間中且被連接到該互連部件。
  7. 如申請專利範圍第6項的半導體封裝，更包括一封裝膠，該封裝膠模製在該半導體晶片、該安裝塊以及該第二安裝元件上，其中：該半導體晶片的一墊、該安裝塊的一導電材料以及該第二安裝元件的一導電材料被暴露在該封裝膠的一表面上；以及該互連部分被電性連接到該半導體晶片的該墊、該安裝塊的該導電材料以及該第二安裝元件的該導電材料。
  8. 一種製造半導體封裝的方法，包括：在一安裝塊上安裝一安裝元件，該安裝塊被裝配為形成一開口，該開口容納一半導體晶片；在該開口中裝載該半導體晶片，該開口由在載體上裝載的該安裝塊形成； 在該半導體晶片、該安裝塊以及該安裝元件上模製一封裝膠；以及在移除該載體的一表面上形成一互連部分，以電性連接該半導體晶片到該安裝塊。
  9. 如申請專利範圍第8項的方法，其中：該半導體晶片的裝載包括：附著該安裝塊的一表面到該載體，以及經由該安裝塊所形成的該開口將該半導體晶片裝載在該載體上；以及該封裝膠的該模製包括：整合配置在該載體上的該半導體晶片、該安裝塊以及該安裝元件。
  10. 如申請專利範圍第8項的方法，其中：該安裝塊是經由塗布一通孔而形成，該通孔以一導電材料形成在一基板中，該通孔電性連接該基板的一頂部到該基板的一底部；以及該安裝元件被安裝以電性連接到該安裝塊的該導電材料。
  11. 如申請專利範圍第8項的方法，其中，該安裝塊包括複數個安裝塊，且該些安裝塊被佈置成圍繞該開口，該開口中容納該半導體晶片。
  12. 如申請專利範圍第8項的方法，其中：一第一安裝元件被安裝在該安裝塊上；以及一第二安裝元件與該半導體晶片一起被安裝在該開口中，該開口經由在該載體上裝載該安裝塊而形成。
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