CN104064551A - 一种芯片堆叠封装结构和电子设备 - Google Patents

一种芯片堆叠封装结构和电子设备 Download PDF

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Publication number
CN104064551A
CN104064551A CN201410247207.9A CN201410247207A CN104064551A CN 104064551 A CN104064551 A CN 104064551A CN 201410247207 A CN201410247207 A CN 201410247207A CN 104064551 A CN104064551 A CN 104064551A
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China
Prior art keywords
chip
crystal grain
hole
wiring layer
package structure
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CN201410247207.9A
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CN104064551B (zh
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符会利
张晓东
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201410247207.9A priority Critical patent/CN104064551B/zh
Publication of CN104064551A publication Critical patent/CN104064551A/zh
Priority to PCT/CN2015/078968 priority patent/WO2015184948A1/zh
Priority to US14/729,316 priority patent/US9349708B2/en
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本发明实施例公开一种芯片堆叠封装结构和电子设备，所述芯片堆叠封装结构包括第一芯片和第二芯片，所述第二芯片与所述第一芯片堆叠设置，所述第二芯片包括封装层和第一布线层，所述封装层包括至少两个晶粒和用于固定所述至少两个晶粒的固定部，所述固定部上开设有多个通孔，所述多个通孔的一部分通孔设置于所述至少两个晶粒外围，所述多个通孔的另一部分通孔设置于所述至少两个晶粒之间；第一布线层，电性连接所述至少两个晶粒；所述封装层位于所述第一布线层和所述第一芯片之间，所述多个通孔内设置有导电材料，通过所述导电材料电性连接所述第一布线层和所述第一芯片，使得所述第一芯片和所述至少两个晶粒中的至少一个晶粒之间能够电性连接。

Description

一种芯片堆叠封装结构和电子设备
技术领域
本发明涉及电子技术领域，尤其涉及一种芯片堆叠封装结构和电子设备。
背景技术
随着半导体产业的发展，对半导体芯片的集成度与小型化要求越来越高。为满足半导体芯片的集成度与小型化的要求，封装技术亦不断精进，各种不同的堆叠封装技术也陆续被开发，并且越显得重要。
常见封装技术包括打线键合(Wire bonding)封装、覆晶键合(Flip-chip bonding)封装以及由此衍生出的层叠封装(Package On Package)、硅通孔(Through SiliconVia,TSV)封装、扇出型晶圆级封装(Fan Out Wafer Level Package，FOWLP)等。
现有的扇出型晶圆级封装的上芯片和下芯片是通过在下芯片的封装体外围开设通道，通过将下芯片上的晶粒的输入输出走线向四面扇出到外围的通孔，通过通孔内填入导电材料，从而实现上芯片和下芯片之间在堆叠方向上的互连。
现有技术中，下芯片内封装的晶粒可以为一个、两个、三个等多个。通孔开设于所述下芯片的封装体外围，晶粒上需要与上芯片连接的输入输出走线向四周扇出到封装体的外围通孔，通过通孔电性连接上芯片。
因此，在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数。
发明内容
本发明实施例提供一种芯片堆叠封装结构和电子设备，解决了现有技术中通孔开设于封装体的外围导致的走线困难问题。
本发明实施例第一方面提供一种芯片堆叠封装结构，所述芯片堆叠封装结构包括第一芯片和第二芯片，所述第二芯片与所述第一芯片堆叠设置，所述第二芯片包括封装层和第一布线层，所述封装层包括至少两个晶粒和用于固定所述至少两个晶粒的固定部，所述固定部上开设有多个通孔，所述多个通孔的一部分通孔设置于所述至少两个晶粒外围，所述多个通孔的另一部分通孔设置于所述至少两个晶粒之间；所述第一布线层电性连接所述至少两个晶粒；其中，所述封装层位于所述第一布线层和所述第一芯片之间，所述多个通孔内设置有导电材料，通过所述导电材料电性连接所述第一布线层和所述第一芯片，使得所述第一芯片和所述至少两个晶粒中的至少一个晶粒之间能够电性连接。
在第一方面第一种可能的实现方式中，所述固定部具体为用于封装所述至少两个晶粒的封装部。
在第一方面第二种可能的实现方式中，所述固定部包括封装部和至少一个通孔模组，所述至少一个通孔模组上开设有所述多个通孔，所述封装部用于封装所述至少一个通孔模组和所述至少两个晶粒。
结合第一方面的第二种可能的实现方式，在第一方面第三种可能的实现方式中，所述至少一个通孔模组具体为印制电路板块或者硅通孔模组。
结合第一方面、第一方面的第一种到第三种任一可能的实现方式，在第一方面第四种可能的实现方式中，所述第二芯片还包括第二布线层，所述第二布线层设置于所述封装层和所述第一芯片之间，所述第二布线层电性连接所述第一芯片和所述导电材料。
结合第一方面、第一方面的第一种到第四种任一可能的实现方式，在第一方面第五种可能的实现方式中，所述第一芯片为存储芯片、硅晶粒、覆晶封装结构、或被动元件。
结合第一方面、第一方面的第一种到第五种任一可能的实现方式，在第一方面第六种可能的实现方式中，所述第一芯片具有与第二芯片相同的结构。
结合第一方面、第一方面的第一种到第六种任一可能的实现方式，在第一方面第七种可能的实现方式中，所述第一芯片和所述至少两个晶粒中的每个晶粒通过所述多个通孔中至少两个通孔内设置的所述导电材料电性连接。
本发明实施例第二方面提供一种电子设备，所述电子设备包括电路板和设置于所述电路板上的芯片堆叠封装结构，所述第二芯片位于所述第一芯片和所述电路板之间。
在第二方面第一种可能的实现方式中，所述电子设备还包括设置于所述电路板和所述第二芯片之间并电性连接所述电路板和所述第二芯片的基板。
本发明实施例有益效果如下：
本申请通过在所述第二芯片的至少两个晶粒之间增加通孔，从而使得晶粒上向四周扇出输入输出走线可以直接通过该晶粒周围的通孔电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒与第一芯片之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例。
图1为本申请一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图2为图1中芯片堆叠封装结构的第二芯片的仰视图；
图3为本申请另一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图4为本申请又一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图5为本申请一较佳实施例提供的电子设备的结构示意图；
图6为本申请另一较佳实施例提供的电子设备的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。
实施例一
如图1所示，为本申请一较佳实施例提供的芯片堆叠封装结构100的结构示意图。所述芯片堆叠封装结构100包括第一芯片10和第二芯片20。
所述第一芯片10可以为存储芯片(Memory)、硅晶粒(Silicon Die)、覆晶封装结构(Flip Chip Package)、被动元件(Passive Device)等，也可以为集成单颗或多颗晶粒(Die)的扇出型晶圆级封装。所述第一芯片10上设置有焊球11，所述第一芯片10可以通过焊球11与其它电子元件电性连接。焊球11可以为钎料球(Solder Ball)、钎料凸点(Solder Bump)或铜柱(Cu Pillar)。
同时参阅图2，所述第二芯片20与所述第一芯片10堆叠设置，并相互固定。所述第二芯片20与所述第一芯片10的结构相同，也可以与第一芯片10的结构不相同。所述第二芯片20和第一芯片10可以采用热风重熔(Mass Reflow)或热压键合(Thermo Compression Bonding)的方法焊接在一起，之间可以根据需要选择是否填充底部填充胶(Underfill)来增强结构的强度和可靠性。所述第二芯片20包括封装层21和第一布线层22。
所述封装层21包括至少两个晶粒211和用于固定所述至少两个晶粒211的固定部212。在本实施方式中，附图仅以两个晶粒211为例进行说明，在其它实施方式中，所述晶粒211的个数可以不限于两个，可以为三个、四个、五个等任意个数，具体个数可以根据需要设置，晶粒与晶粒之间的间距和位置可以根据需要设置。
所述固定部212上开设有多个通孔213，所述多个通孔213中一部分通孔213设置于所述至少两个晶粒211的外围，另一部分通孔213设置于所述至少两个晶粒211之间的区域214。与现有技术中多个通孔213仅设置于所述至少两个晶粒211的外围不同，本实施例提供的方案在两晶粒211之间也可以设置至少一个通孔213，使得不必将全部通孔213都置于所述至少两个晶粒211的外围，减少了布局布线的难度。
所述第一布线层22电性连接所述至少两个晶粒211。所述第一布线层22的层数可以根据需要设置，可以为一层，也可以为多层。所述第一布线层22的介质层和金属层，可通过采用晶圆级的涂覆、曝光、显影、固化、溅射、电镀等工艺制作，所述金属层通常为导电线如铜线的材料制成。第一布线层22与晶粒211之间为可曝光显影的有机介质层，在该介质层内制作镀铜孔导通布线层与晶粒211上的焊盘。由于第一布线层22会覆盖在晶粒211上的区域以及晶粒211周围的区域，所以第一布线层22可以把晶粒211通过走线连接到晶粒211的外围区域。
其中，所述封装层21位于所述第一布线层22和所述第一芯片10之间，所述多个通孔213内的每个通孔内设置有导电材料。所述导电材料可以采用电镀的方式将导电金属如铜等电镀于通孔213的内壁上，再通过其它材料对通孔213进行填充，或者所述导电材料直接填充于通孔213内。通过所述导电材料电性连接所述第一布线层22和所述第一芯片10，使得所述第一芯片10和所述至少两个晶粒211中至少一个晶粒之间能够通过所述多个通孔213中至少两个通孔213内设置的所述导电材料电性连接，也就是说，使得所述第一芯片10和所述第二芯片20上所有的晶粒211电性连接，或者与所述第二芯片20上部分晶粒211电性连接，具体根据需要设置。
上述芯片堆叠封装结构100通过在所述第二芯片20的至少两个晶粒211之间增加通孔213，从而使得晶粒211上向四周扇出输入输出走线可以直接通过该晶粒211周围的通孔213电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒211与第一芯片10之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
开设通孔213的方式至少有如下两种：
第一种：直接将通孔213开设于封装晶粒211的封装部上。
即，所述固定部212具体为用于封装所述至少两个晶粒211的封装部。所述封装部可以为封装材料如模塑材料制成。此时，通孔213可以采用激光钻孔或深反应离子刻蚀在封装部上制作。所述至少两个晶粒211的正面与第一布线层22电性连接，所述至少两个晶粒211的背面和侧面可以完全被包裹在封装部内，也可以侧面被包裹，而背面外露于封装部，具体可以根据需要设置。
第二种：采用通孔模组的方式。
即，如图3所示，所述固定部212包括封装部2121和通孔模组2122。所述通孔模组2122为开设有多个所述通孔213单一元件。所述多个通孔213可以位于一个所述通孔模组2122上，也可以为于多个通孔模组2122上，也就是说，所述通孔模组2122的个数可以为一个，也可以为多个，具体根据实际情况进行设置。所述通孔模组2122设置于所述至少两个晶粒211，外围和所述至少两个晶粒211之间。所述通孔模组2122具体为印制电路板块(PCB Bar)或者硅通孔模组。
所述封装部2121用于封装所述通孔模组2122和所述至少两个晶粒211。所述封装部2121可以为封装材料如模塑材料制成。所述至少两个晶粒211的正面与第一布线层22电性连接，所述至少两个晶粒211的背面和侧面可以完全被包裹在封装部2121内，也可以侧面被包裹，背面外露于封装部，具体可以根据需要设置。通过使用设置有所述通孔213的所述通孔模组2122，从而可以降低通过激光钻孔或深反应离子刻蚀做孔时困难度，提高做孔效率。
进一步，在所述第一芯片10的焊球11位置与所述多个通孔213的位置对应时，所述第一芯片10可以直接通过所述多个通孔213内的导电材料与第二芯片20上的晶粒211电性连接。而在所述第一芯片10上的焊球11位置与所述多个通孔213的位置不对应时，就需要在所述第二芯片20与所述第一芯片10相对的表面上设置第二布线层23。具体地，所述第二布线层23设置于所述封装层21和所述第一芯片10之间，所述第二布线层23电性连接所述第一芯片10和所述通孔213内的导电材料。所述第二布线层23的层数可以根据需要设置，可以为一层，也可以为多层。所述第二布线层23采用晶圆级的溅射、电镀等工艺制作，通常为导电线如铜线的材料。
通过在所述第二芯片20与所述第一芯片10相对的表面上设置第二布线层23，从而使得在所述第一芯片10上的焊球11位置与所述多个通孔213的位置不对应时，所述第二布线层23可以电性连接所第一芯片10和所述通孔213内的导电材料。
另外，所述芯片堆叠封装结构100的芯片数目可以只包括第一芯片10和第二芯片20，如图1和图3所示，但，所述芯片堆叠封装结构100的芯片数目可以不限于两个。如图4所示，所述第二芯片20的数目为三个，也就是说，所述芯片堆叠封装结构100的芯片数目为四个。在其他实施方式中，所述第二芯片20的数目还可以为两个、四个等多个。
实施例二
基于同样的发明构思，本申请还提供一种电子设备。如图5所示，为本申请电子设备200的结构示意图。所述电子设备200包括电路板210和设置于所述电路板上的芯片堆叠封装结构220。所述芯片堆叠封装结构220与实施例一中的芯片堆叠封装结构100的结构和功能相同，在此不再赘述。所述芯片堆叠封装结构220的第二芯片20位于所述第一芯片10和所述电路板210之间。
上述电子设备200通过采用芯片堆叠封装结构220，在所述第二芯片20的至少两个晶粒211之间增加通孔213，从而使得晶粒211上向四周扇出输入输出走线可以直接通过该晶粒211周围的通孔213电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒211与第一芯片10之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
所述第二芯片20可以直接通过焊球电性连接于所述电路板210上，也可以如图6所示，在第二芯片20和所述电路板210之间设置一基板230，所述第二芯片20通过焊接凸点电性连接于所述基板230上，再通过焊球电性连接于所述电路板210上。所述基板230和所述第二芯片20之间可以根据需要选择是否填充底部填充胶(Underfill)来增强结构的强度和可靠性。通过在所述第二芯片20和所述电路板210之间设置所述基板230，可以通过基板230增加布线资源和封装的管脚数，改善第二芯片20的电源完整性，提高封装板级的可靠性。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。而且，本发明实施例中提到的“连接”一词如无特别结实应理解为是一种电性连接。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种芯片堆叠封装结构，其特征在于，所述芯片堆叠封装结构包括：
第一芯片；
第二芯片，与所述第一芯片堆叠设置，所述第二芯片包括：
封装层，所述封装层包括至少两个晶粒和用于固定所述至少两个晶粒的固定部，所述固定部上开设有多个通孔，所述多个通孔的一部分通孔设置于所述至少两个晶粒外围，所述多个通孔的另一部分通孔设置于所述至少两个晶粒之间；和
第一布线层，电性连接所述至少两个晶粒；
其中，所述封装层位于所述第一布线层和所述第一芯片之间，所述多个通孔内设置有导电材料，通过所述导电材料电性连接所述第一布线层和所述第一芯片，使得所述第一芯片和所述至少两个晶粒中的至少一个晶粒之间能够电性连接。
2.如权利要求1所述的芯片堆叠封装结构，其特征在于，所述固定部具体为用于封装所述至少两个晶粒的封装部。
3.如权利要求1所述的芯片堆叠封装结构，其特征在于，所述固定部包括封装部和至少一个通孔模组，所述至少一个通孔模组上开设有所述多个通孔，所述封装部用于封装所述至少一个通孔模组和所述至少两个晶粒。
4.如权利要求3所述的芯片堆叠封装结构，其特征在于，所述至少一个通孔模组具体为印制电路板块或者硅通孔模组。
5.如权利要求1-4中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第二芯片还包括第二布线层，所述第二布线层设置于所述封装层和所述第一芯片之间，所述第二布线层电性连接所述第一芯片和所述导电材料。
6.如权利要求1-5中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片为存储芯片、硅晶粒、覆晶封装结构、或被动元件。
7.如权利要求1-6中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片具有与第二芯片相同的结构。
8.如权利要求1-7中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片和所述至少两个晶粒中的每个晶粒通过所述多个通孔中至少两个通孔内设置的所述导电材料电性连接。
9.一种电子设备，其特征在于，所述电子设备包括：
电路板；
设置于所述电路板上的如权利要求1-8中任一权利要求所述芯片堆叠封装结构，所述第二芯片位于所述第一芯片和所述电路板之间。
10.如权利要求9所述的电子设备，其特征在于，所述电子设备还包括设置于所述电路板和所述第二芯片之间并电性连接所述电路板和所述第二芯片的基板。
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015184948A1 (zh) * 2014-06-05 2015-12-10 华为技术有限公司 一种芯片堆叠封装结构和电子设备
CN107104096A (zh) * 2017-05-19 2017-08-29 华为技术有限公司 芯片封装结构及电路结构
EP3255668A4 (en) * 2015-04-14 2018-07-11 Huawei Technologies Co., Ltd. Chip
CN108461487A (zh) * 2017-02-17 2018-08-28 联发科技股份有限公司 半导体装置
CN111128914A (zh) * 2019-12-25 2020-05-08 上海先方半导体有限公司 一种低翘曲的多芯片封装结构及其制造方法
WO2020133420A1 (zh) * 2018-12-29 2020-07-02 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
CN111968958A (zh) * 2016-12-30 2020-11-20 华为技术有限公司 一种封装芯片及基于封装芯片的信号传输方法
CN112996370A (zh) * 2021-04-25 2021-06-18 中国人民解放军海军工程大学 一种适用于高盐雾环境的功率电子设备封装结构
CN113632218A (zh) * 2019-03-28 2021-11-09 株式会社电装 电子装置
CN116344441A (zh) * 2023-02-03 2023-06-27 佛山市顺德区舜欣电子有限公司 一种芯片封装方法及计算机可读存储介质
US11908759B2 (en) 2016-10-06 2024-02-20 Mediatek Inc. Semiconductor device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105453261A (zh) * 2014-07-07 2016-03-30 英特尔Ip公司 封装上封装堆叠微电子结构
US9799628B2 (en) * 2015-03-31 2017-10-24 Qualcomm Incorporated Stacked package configurations and methods of making the same
US20180324955A1 (en) * 2015-12-23 2018-11-08 Intel Corporation No-flow adhesive for second and third level interconnects
DE102016110862B4 (de) * 2016-06-14 2022-06-30 Snaptrack, Inc. Modul und Verfahren zur Herstellung einer Vielzahl von Modulen
KR102509049B1 (ko) * 2016-08-22 2023-03-13 에스케이하이닉스 주식회사 수직 적층된 칩들을 포함하는 팬 아웃 패키지
US11158619B2 (en) * 2016-10-31 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US20190164948A1 (en) 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
US11393805B2 (en) * 2019-08-29 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor packages
US20230102167A1 (en) * 2021-09-24 2023-03-30 Qualcomm Incorporated Multiple (multi-) die integrated circuit (ic) packages for supporting higher connection density, and related fabrication methods

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1157790C (zh) * 2000-11-27 2004-07-14 矽品精密工业股份有限公司 芯片堆叠封装结构
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
CN101465341B (zh) * 2007-12-21 2011-07-06 南亚科技股份有限公司 堆叠式芯片封装结构
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US7838975B2 (en) 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US8093722B2 (en) 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US7659145B2 (en) 2008-07-14 2010-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device
US7825024B2 (en) * 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8535980B2 (en) 2010-12-23 2013-09-17 Stmicroelectronics Pte Ltd. Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8389333B2 (en) 2011-05-26 2013-03-05 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
CN102280440A (zh) * 2011-08-24 2011-12-14 北京大学 一种叠层封装结构及制造方法
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
CN202394968U (zh) * 2011-12-19 2012-08-22 日月光半导体制造股份有限公司 半导体封装结构
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9691706B2 (en) 2012-01-23 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip fan out package and methods of forming the same
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US20130249101A1 (en) 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US20130256883A1 (en) 2012-03-27 2013-10-03 Intel Mobile Communications GmbH Rotated semiconductor device fan-out wafer level packages and methods of manufacturing rotated semiconductor device fan-out wafer level packages
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8878360B2 (en) 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US8624376B1 (en) 2012-10-10 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure without through assembly vias
CN104064551B (zh) * 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015184948A1 (zh) * 2014-06-05 2015-12-10 华为技术有限公司 一种芯片堆叠封装结构和电子设备
EP3255668A4 (en) * 2015-04-14 2018-07-11 Huawei Technologies Co., Ltd. Chip
US10475741B2 (en) 2015-04-14 2019-11-12 Huawei Technologies Co., Ltd. Chip
US11908759B2 (en) 2016-10-06 2024-02-20 Mediatek Inc. Semiconductor device
CN111968958B (zh) * 2016-12-30 2022-08-19 华为技术有限公司 一种封装芯片及基于封装芯片的信号传输方法
CN111968958A (zh) * 2016-12-30 2020-11-20 华为技术有限公司 一种封装芯片及基于封装芯片的信号传输方法
CN108461487A (zh) * 2017-02-17 2018-08-28 联发科技股份有限公司 半导体装置
CN107104096A (zh) * 2017-05-19 2017-08-29 华为技术有限公司 芯片封装结构及电路结构
WO2020133420A1 (zh) * 2018-12-29 2020-07-02 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
CN113228268A (zh) * 2018-12-29 2021-08-06 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
CN113228268B (zh) * 2018-12-29 2023-09-29 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
CN113632218A (zh) * 2019-03-28 2021-11-09 株式会社电装 电子装置
CN111128914A (zh) * 2019-12-25 2020-05-08 上海先方半导体有限公司 一种低翘曲的多芯片封装结构及其制造方法
CN112996370A (zh) * 2021-04-25 2021-06-18 中国人民解放军海军工程大学 一种适用于高盐雾环境的功率电子设备封装结构
CN116344441B (zh) * 2023-02-03 2024-01-12 深圳华芯星半导体有限公司 一种芯片封装方法及计算机可读存储介质
CN116344441A (zh) * 2023-02-03 2023-06-27 佛山市顺德区舜欣电子有限公司 一种芯片封装方法及计算机可读存储介质

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