WO2015184948A1 - 一种芯片堆叠封装结构和电子设备 - Google Patents

一种芯片堆叠封装结构和电子设备 Download PDF

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Publication number
WO2015184948A1
WO2015184948A1 PCT/CN2015/078968 CN2015078968W WO2015184948A1 WO 2015184948 A1 WO2015184948 A1 WO 2015184948A1 CN 2015078968 W CN2015078968 W CN 2015078968W WO 2015184948 A1 WO2015184948 A1 WO 2015184948A1
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chip
package structure
holes
wiring layer
crystal grains
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PCT/CN2015/078968
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English (en)
French (fr)
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符会利
张晓东
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华为技术有限公司
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Definitions

  • Common packaging technologies include wire bonding, Flip-chip bonding, and package-on package, through-silicon via (TSV) packages. , Fan Out Wafer Level Package (FOWLP) and so on.
  • TSV through-silicon via
  • FOWLP Fan Out Wafer Level Package
  • the upper chip and the lower chip of the existing fan-out wafer level package are formed by opening a channel on the periphery of the package of the lower chip, and fan-outing the input and output lines of the die on the lower chip to the peripheral through holes.
  • the conductive material is filled in the through hole, thereby achieving interconnection in the stacking direction between the upper chip and the lower chip.
  • the number of dies in the lower chip package may be one, two, three, or the like.
  • the through hole is opened on the periphery of the package of the lower chip, and the input and output traces on the die that need to be connected to the upper chip are fanned out to the peripheral through hole of the package, and the upper chip is electrically connected through the through hole.
  • the input and output wires that need to be connected to the upper chip on the one die (especially when the input and output traces of the die are large) occupy the wiring layer.
  • Most of the wiring space resources will affect the interconnect traces between the die and the die of the lower chip and other traces in the wiring layer, thereby causing difficulty in routing or increasing the number of layers of the wiring layer.
  • the embodiment of the invention provides a chip stacking package structure and an electronic device, which solves the problem that the through hole is opened on the periphery of the package body in the prior art.
  • a first aspect of the embodiments of the present invention provides a chip stack package structure, where the chip stack package structure includes a first chip and a second chip, the second chip is stacked with the first chip, and the second chip includes An encapsulation layer and a first wiring layer, the encapsulation layer includes at least two crystal grains and a fixing portion for fixing the at least two crystal grains, and the fixing portion is provided with a plurality of through holes, the plurality of through holes a part of the through hole of the hole is disposed at the periphery of the at least two crystal grains, and another part of the plurality of through holes is disposed between the at least two crystal grains; the first wiring layer is electrically connected to the At least two dies; wherein the encapsulation layer is located between the first wiring layer and the first chip, and the plurality of via holes are provided with a conductive material, and the electrically conductive material is electrically connected to the The first wiring layer and the first chip enable electrical connection between the first chip and at least one of the at least two crystal grains.
  • the fixing portion is specifically a package portion for encapsulating the at least two crystal grains.
  • the fixing portion includes a package portion and at least one through hole module, and the at least one through hole module is provided with the plurality of through holes, and the package portion And a method for packaging the at least one via module and the at least two dies.
  • the at least one through hole module is specifically a printed circuit board block or a through silicon via module.
  • the second chip further includes a second wiring layer, The second wiring layer is disposed between the encapsulation layer and the first chip, and the second wiring layer is electrically connected to the first chip and the conductive material.
  • the first chip is a memory chip, a silicon die, and a Crystal package structure, or passive components.
  • the first chip has the same structure as the second chip.
  • any one of the first to sixth possible implementations of the first aspect in the seventh possible implementation manner of the first aspect, the first chip and the at least two dies Each of the dies is electrically connected through the conductive material disposed in at least two of the plurality of through holes.
  • a second aspect of the embodiments of the present invention provides an electronic device, where the electronic device includes a circuit board and a chip stack package structure disposed on the circuit board, where the second chip is located on the first chip and the circuit board between.
  • the electronic device further includes a substrate disposed between the circuit board and the second chip and electrically connecting the circuit board and the second chip.
  • the fan-out input and output traces on the die can be electrically connected to the chip directly through the through hole around the die.
  • FIG. 1 is a schematic structural diagram of a chip stack package structure according to a preferred embodiment of the present application.
  • FIG. 2 is a bottom view of the second chip of the chip stack package structure of FIG. 1;
  • FIG. 3 is a schematic structural diagram of a chip stack package structure according to another preferred embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a chip stack package structure according to still another preferred embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device according to a preferred embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an electronic device according to another preferred embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a chip stack package structure 100 according to a preferred embodiment of the present application.
  • the chip stacked package structure 100 includes a first chip 10 and a second chip 20.
  • the first chip 10 may be a memory chip, a silicon die, a flip chip package, a passive device, or the like, or may be integrated with single or multiple crystals. Die-out wafer level package for Die.
  • the first chip 10 is provided with solder balls 11 , and the first chip 10 can be electrically connected to other electronic components through the solder balls 11 .
  • the solder ball 11 may be a solder ball (Solder Ball), a solder bump (Solder Bump) or a copper pillar (Cu Pillar).
  • the second chip 20 is stacked with the first chip 10 and fixed to each other.
  • the second chip 20 has the same structure as the first chip 10, and may also be different from the structure of the first chip 10.
  • the second chip 20 and the first chip 10 may be soldered together by a method of Mass Reflow or Thermo Compression Bonding, and an underfill may be selected according to requirements.
  • the second chip 20 includes an encapsulation layer 21 and a first wiring layer 22.
  • the encapsulation layer 21 includes at least two crystal grains 211 and a fixing portion 212 for fixing the at least two crystal grains 211.
  • the drawing is described by taking only two crystal grains 211 as an example, in which
  • the number of the dies 211 may not be limited to two, and may be any number of three, four, five, etc., and the specific number may be set as needed, between the die and the die. The spacing and position can be set as needed.
  • a plurality of through holes 213 are defined in the fixing portion 212.
  • a part of the plurality of through holes 213 are disposed at a periphery of the at least two die 211, and another portion of the through holes 213 is disposed at the at least two A region 214 between the dies 211.
  • the solution provided in this embodiment may also be provided with at least one through hole 213 between the two dies 211, so that it is not necessary to All of the through holes 213 are placed on the periphery of the at least two crystal grains 211, which reduces the difficulty in layout and wiring.
  • the first wiring layer 22 is electrically connected to the at least two crystal grains 211.
  • the number of layers of the first wiring layer 22 may be set as needed, and may be one layer or multiple layers.
  • the dielectric layer and the metal layer of the first wiring layer 22 can be fabricated by using wafer level coating, exposure, development, curing, sputtering, electroplating, etc., and the metal layer is usually a conductive wire such as a copper wire. Made of materials.
  • An organic medium layer that can be exposed and developed is formed between the first wiring layer 22 and the die 211, and a copper-plated via wiring layer and a pad on the die 211 are formed in the dielectric layer. Since the first wiring layer 22 covers the region on the die 211 and the region around the die 211, the first wiring layer 22 can connect the die 211 to the peripheral region of the die 211 through the trace.
  • the encapsulation layer 21 is located between the first wiring layer 22 and the first chip 10, and a conductive material is disposed in each of the plurality of through holes 213.
  • the conductive material may be plated on the inner wall of the through hole 213 by electroplating, and the through hole 213 may be filled by other materials, or the conductive material may be directly filled in the through hole 213. Electrically connecting the first wiring layer 22 and the first chip 10 through the conductive material, so that at least one of the first chip 10 and the at least two crystal grains 211 can pass between
  • the conductive material disposed in at least two of the plurality of through holes 213 is electrically connected, that is, the first die 10 and the second die 20 are electrically connected to each other. Or with the second chip 20
  • the upper portion of the die 211 is electrically connected, and is specifically set as needed.
  • the chip-stacked package structure 100 increases the through-hole 213 between the at least two dies 211 of the second chip 20, so that the input and output traces fan-outs on the die 211 can pass directly around the die 211.
  • the through hole 213 is electrically connected to the upper chip, thereby reducing the wiring space resource occupying the wiring layer, improving the resource utilization of the wiring space, and reducing the trace between the die 211 and the first chip 10.
  • the length, the load of the signal is reduced, and the performance of the signal is improved, which solves the problem that in the prior art, when the die of the lower chip is two or more, one die (especially when the input and output traces of the die are large)
  • the input and output wires that need to be connected to the upper chip occupy most of the wiring space resources in the wiring layer, which will affect the interconnect traces between the die and the die of the lower chip and other traces in the wiring layer. This causes technical problems in that wiring is difficult or the number of layers of the wiring layer is increased.
  • the first type the through hole 213 is directly opened on the package portion of the package die 211.
  • the fixing portion 212 is specifically a package portion for encapsulating the at least two crystal grains 211.
  • the encapsulation portion may be made of a packaging material such as a molding material.
  • the through hole 213 can be fabricated on the package portion by laser drilling or deep reactive ion etching.
  • the front surface of the at least two die 211 is electrically connected to the first wiring layer 22, and the back surface and the side surface of the at least two die 211 may be completely wrapped in the package portion, or may be wrapped on the side, and the back surface is exposed on the back surface.
  • the package part can be specifically set as needed.
  • the second type the way of using the through hole module.
  • the fixing portion 212 includes a package portion 2121 and a through hole module 2122 .
  • the through hole module 2122 is a single component with a plurality of the through holes 213.
  • the plurality of through holes 213 may be located on one of the through hole modules 2122, or may be on the plurality of through hole modules 2122, that is, the number of the through hole modules 2122 may be one. It can also be multiple, depending on the actual situation.
  • the through hole module 2122 is disposed between the at least two die 211, the periphery and the at least two die 211.
  • the through hole module 2122 is specifically a printed circuit board block (PCB Bar) or a through silicon via hole module.
  • the encapsulation portion 2121 is configured to encapsulate the through hole module 2122 and the at least two crystal grains 211.
  • the encapsulation portion 2121 may be made of an encapsulation material such as a molding material.
  • the front surface of the at least two dies 211 is electrically connected to the first wiring layer 22, and the back surface and the side surface of the at least two dies 211 may be completely wrapped in the encapsulation portion 2121, or may be wrapped on the side and exposed on the back side. In the package part, it can be set as needed.
  • the through hole module 2122 provided with the through hole 213 it is possible to reduce the difficulty in making holes by laser drilling or deep reactive ion etching, and to improve the hole making efficiency.
  • the first chip 10 may directly pass through the conductive material in the plurality of through holes 213 and the second The die 211 on the chip 20 is electrically connected.
  • the position of the solder ball 11 on the first chip 10 does not correspond to the position of the plurality of through holes 213, it is required to set a surface on the surface of the second chip 20 opposite to the first chip 10.
  • Two wiring layers 23 Two wiring layers 23. Specifically, the second wiring layer 23 is disposed between the encapsulation layer 21 and the first chip 10, and the second wiring layer 23 is electrically connected to the first chip 10 and the through hole 213. Conductive material.
  • the number of layers of the second wiring layer 23 may be set as needed, and may be one layer or multiple layers.
  • the second wiring layer 23 is formed by a wafer level sputtering, electroplating or the like, and is usually a material such as a conductive wire such as a copper wire.
  • the second wiring layer 23 may electrically connect the conductive materials in the first chip 10 and the through holes 213.
  • the number of chips of the chip stack package structure 100 may include only the first chip 10 and the second chip 20, as shown in FIG. 1 and FIG. 3, but the number of chips of the chip stack package structure 100 may not be limited to two. One. As shown in FIG. 4, the number of the second chips 20 is three, that is, the number of chips of the chip stack package structure 100 is four. In other embodiments, the number of the second chips 20 may also be two, four, or the like.
  • FIG. 5 is a schematic structural diagram of an electronic device 200 of the present application.
  • the electronic device 200 includes a circuit board 210 and a chip stack package structure 220 disposed on the circuit board.
  • the chip stack package structure 220 has the same structure and function as the chip stack package structure 100 in the first embodiment, and details are not described herein again.
  • the second chip 20 of the chip stack package structure 220 is located between the first chip 10 and the circuit board 210.
  • the above-mentioned electronic device 200 adds a through hole 213 between at least two dies 211 of the second chip 20 by using the chip stack package structure 220, so that the input and output traces fan-out on the die 211 can pass directly through
  • the via 213 around the die 211 is electrically connected to the upper chip, thereby reducing the wiring space resources in the wiring layer, improving the resource utilization of the wiring space, and reducing the die 211 and the first chip 10.
  • the load of the signal is reduced, the performance of the signal is improved, and a single crystal (in particular, the input of the die) is solved in the prior art when the die of the lower chip is two or more
  • the output traces are large, the input and output wires that need to be connected to the upper chip occupy most of the wiring space resources in the wiring layer, which will affect the interconnection trace between the die and the die of the lower chip and in the wiring layer.
  • Other traces cause technical problems in routing difficulties or increasing the number of layers of the wiring layer.
  • the second chip 20 can be electrically connected to the circuit board 210 directly through a solder ball.
  • a substrate 230 is disposed between the second chip 20 and the circuit board 210.
  • the second chip 20 is electrically connected to the substrate 230 through solder bumps, and is electrically connected to the circuit board 210 through solder balls.
  • whether or not an underfill is filled may be selected as needed to enhance the strength and reliability of the structure.

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Abstract

提供了一种芯片堆叠封装结构和电子设备，所述芯片堆叠封装结构包括第一芯片（10）和第二芯片（20），所述第二芯片（20）与所述第一芯片（10）堆叠设置，所述第二芯片（20）包括封装层（21）和第一布线层（22），所述封装层（21）包括至少两个晶粒（211）和用于固定所述至少两个晶粒（211）的固定部（212），所述固定部（212）上开设有多个通孔（213），所述多个通孔（213）的一部分通孔设置于所述至少两个晶粒（211）外围，所述多个通孔（213）的另一部分通孔设置于所述至少两个晶粒（211）之间；第一布线层（22），电性连接所述至少两个晶粒（211）；所述封装层（21）位于所述第一布线层（22）和所述第一芯片（10）之间，所述多个通孔（213）内设置有导电材料，通过所述导电材料电性连接所述第一布线层（22）和所述第一芯片（10），使得所述第一芯片（10）和所述至少两个晶粒（211）中的至少一个晶粒之间能够电性连接。

Description

一种芯片堆叠封装结构和电子设备
本申请要求于2014年6月5日提交中国专利局、申请号为201410247207.9、发明名称为“一种芯片堆叠封装结构和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
背景技术
随着半导体产业的发展，对半导体芯片的集成度与小型化要求越来越高。为满足半导体芯片的集成度与小型化的要求，封装技术亦不断精进，各种不同的堆叠封装技术也陆续被开发，并且越显得重要。
常见封装技术包括打线键合(Wire bonding)封装、覆晶键合(Flip-chip bonding)封装以及由此衍生出的层叠封装(Package On Package)、硅通孔(Through Silicon Via,TSV)封装、扇出型晶圆级封装(Fan Out Wafer Level Package，FOWLP)等。
现有的扇出型晶圆级封装的上芯片和下芯片是通过在下芯片的封装体外围开设通道，通过将下芯片上的晶粒的输入输出走线向四面扇出到外围的通孔，通过通孔内填入导电材料，从而实现上芯片和下芯片之间在堆叠方向上的互连。
现有技术中，下芯片内封装的晶粒可以为一个、两个、三个等多个。通孔开设于所述下芯片的封装体外围，晶粒上需要与上芯片连接的输入输出走线向四周扇出到封装体的外围通孔，通过通孔电性连接上芯片。
因此，在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数。
发明内容
本发明实施例提供一种芯片堆叠封装结构和电子设备，解决了现有技术中通孔开设于封装体的外围导致的走线困难问题。
本发明实施例第一方面提供一种芯片堆叠封装结构，所述芯片堆叠封装结构包括第一芯片和第二芯片，所述第二芯片与所述第一芯片堆叠设置，所述第二芯片包括封装层和第一布线层，所述封装层包括至少两个晶粒和用于固定所述至少两个晶粒的固定部，所述固定部上开设有多个通孔，所述多个通孔的一部分通孔设置于所述至少两个晶粒外围，所述多个通孔的另一部分通孔设置于所述至少两个晶粒之间；所述第一布线层电性连接所述至少两个晶粒；其中，所述封装层位于所述第一布线层和所述第一芯片之间，所述多个通孔内设置有导电材料，通过所述导电材料电性连接所述第一布线层和所述第一芯片，使得所述第一芯片和所述至少两个晶粒中的至少一个晶粒之间能够电性连接。
在第一方面第一种可能的实现方式中，所述固定部具体为用于封装所述至少两个晶粒的封装部。
在第一方面第二种可能的实现方式中，所述固定部包括封装部和至少一个通孔模组，所述至少一个通孔模组上开设有所述多个通孔，所述封装部用于封装所述至少一个通孔模组和所述至少两个晶粒。
结合第一方面的第二种可能的实现方式，在第一方面第三种可能的实现方式中，所述至少一个通孔模组具体为印制电路板块或者硅通孔模组。
结合第一方面、第一方面的第一种到第三种任一可能的实现方式，在第一方面第四种可能的实现方式中，所述第二芯片还包括第二布线层，所述第二布线层设置于所述封装层和所述第一芯片之间，所述第二布线层电性连接所述第一芯片和所述导电材料。
结合第一方面、第一方面的第一种到第四种任一可能的实现方式，在第一方面第五种可能的实现方式中，所述第一芯片为存储芯片、硅晶粒、覆晶封装结构、或被动元件。
结合第一方面、第一方面的第一种到第五种任一可能的实现方式，在第一方面第六种可能的实现方式中，所述第一芯片具有与第二芯片相同的结构。
结合第一方面、第一方面的第一种到第六种任一可能的实现方式，在第一方面第七种可能的实现方式中，所述第一芯片和所述至少两个晶粒中的每个晶粒通过所述多个通孔中至少两个通孔内设置的所述导电材料电性连接。
本发明实施例第二方面提供一种电子设备，所述电子设备包括电路板和设置于所述电路板上的芯片堆叠封装结构，所述第二芯片位于所述第一芯片和所述电路板之间。
在第二方面第一种可能的实现方式中，所述电子设备还包括设置于所述电路板和所述第二芯片之间并电性连接所述电路板和所述第二芯片的基板。
本发明实施例有益效果如下：
本申请通过在所述第二芯片的至少两个晶粒之间增加通孔，从而使得晶粒上向四周扇出输入输出走线可以直接通过该晶粒周围的通孔电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒与第一芯片之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例。
图1为本申请一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图2为图1中芯片堆叠封装结构的第二芯片的仰视图；
图3为本申请另一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图4为本申请又一较佳实施例提供的芯片堆叠封装结构的结构示意图；
图5为本申请一较佳实施例提供的电子设备的结构示意图；
图6为本申请另一较佳实施例提供的电子设备的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。
实施例一
如图1所示，为本申请一较佳实施例提供的芯片堆叠封装结构100的结构示意图。所述芯片堆叠封装结构100包括第一芯片10和第二芯片20。
所述第一芯片10可以为存储芯片(Memory)、硅晶粒(Silicon Die)、覆晶封装结构(Flip Chip Package)、被动元件(Passive Device)等，也可以为集成单颗或多颗晶粒(Die)的扇出型晶圆级封装。所述第一芯片10上设置有焊球11，所述第一芯片10可以通过焊球11与其它电子元件电性连接。焊球11可以为钎料球(Solder Ball)、钎料凸点(Solder Bump)或铜柱(Cu Pillar)。
同时参阅图2，所述第二芯片20与所述第一芯片10堆叠设置，并相互固定。所述第二芯片20与所述第一芯片10的结构相同，也可以与第一芯片10的结构不相同。所述第二芯片20和第一芯片10可以采用热风重熔(Mass Reflow)或热压键合(Thermo Compression Bonding)的方法焊接在一起，之间可以根据需要选择是否填充底部填充胶(Underfill)来增强结构的强度和可靠性。所述第二芯片20包括封装层21和第一布线层22。
所述封装层21包括至少两个晶粒211和用于固定所述至少两个晶粒211的固定部212。在本实施方式中，附图仅以两个晶粒211为例进行说明，在其 它实施方式中，所述晶粒211的个数可以不限于两个，可以为三个、四个、五个等任意个数，具体个数可以根据需要设置，晶粒与晶粒之间的间距和位置可以根据需要设置。
所述固定部212上开设有多个通孔213，所述多个通孔213中一部分通孔213设置于所述至少两个晶粒211的外围，另一部分通孔213设置于所述至少两个晶粒211之间的区域214。与现有技术中多个通孔213仅设置于所述至少两个晶粒211的外围不同，本实施例提供的方案在两晶粒211之间也可以设置至少一个通孔213，使得不必将全部通孔213都置于所述至少两个晶粒211的外围，减少了布局布线的难度。
所述第一布线层22电性连接所述至少两个晶粒211。所述第一布线层22的层数可以根据需要设置，可以为一层，也可以为多层。所述第一布线层22的介质层和金属层，可通过采用晶圆级的涂覆、曝光、显影、固化、溅射、电镀等工艺制作，所述金属层通常为导电线如铜线的材料制成。第一布线层22与晶粒211之间为可曝光显影的有机介质层，在该介质层内制作镀铜孔导通布线层与晶粒211上的焊盘。由于第一布线层22会覆盖在晶粒211上的区域以及晶粒211周围的区域，所以第一布线层22可以把晶粒211通过走线连接到晶粒211的外围区域。
其中，所述封装层21位于所述第一布线层22和所述第一芯片10之间，所述多个通孔213内的每个通孔内设置有导电材料。所述导电材料可以采用电镀的方式将导电金属如铜等电镀于通孔213的内壁上，再通过其它材料对通孔213进行填充，或者所述导电材料直接填充于通孔213内。通过所述导电材料电性连接所述第一布线层22和所述第一芯片10，使得所述第一芯片10和所述至少两个晶粒211中至少一个晶粒之间能够通过所述多个通孔213中至少两个通孔213内设置的所述导电材料电性连接，也就是说，使得所述第一芯片10和所述第二芯片20上所有的晶粒211电性连接，或者与所述第二芯片20 上部分晶粒211电性连接，具体根据需要设置。
上述芯片堆叠封装结构100通过在所述第二芯片20的至少两个晶粒211之间增加通孔213，从而使得晶粒211上向四周扇出输入输出走线可以直接通过该晶粒211周围的通孔213电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒211与第一芯片10之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
开设通孔213的方式至少有如下两种：
第一种：直接将通孔213开设于封装晶粒211的封装部上。
即，所述固定部212具体为用于封装所述至少两个晶粒211的封装部。所述封装部可以为封装材料如模塑材料制成。此时，通孔213可以采用激光钻孔或深反应离子刻蚀在封装部上制作。所述至少两个晶粒211的正面与第一布线层22电性连接，所述至少两个晶粒211的背面和侧面可以完全被包裹在封装部内，也可以侧面被包裹，而背面外露于封装部，具体可以根据需要设置。
第二种：采用通孔模组的方式。
即，如图3所示，所述固定部212包括封装部2121和通孔模组2122。所述通孔模组2122为开设有多个所述通孔213单一元件。所述多个通孔213可以位于一个所述通孔模组2122上，也可以为于多个通孔模组2122上，也就是说，所述通孔模组2122的个数可以为一个，也可以为多个，具体根据实际情况进行设置。所述通孔模组2122设置于所述至少两个晶粒211，外围和所述至少两个晶粒211之间。所述通孔模组2122具体为印制电路板块(PCB Bar)或者硅通孔模组。
所述封装部2121用于封装所述通孔模组2122和所述至少两个晶粒211。所述封装部2121可以为封装材料如模塑材料制成。所述至少两个晶粒211的正面与第一布线层22电性连接，所述至少两个晶粒211的背面和侧面可以完全被包裹在封装部2121内，也可以侧面被包裹，背面外露于封装部，具体可以根据需要设置。通过使用设置有所述通孔213的所述通孔模组2122，从而可以降低通过激光钻孔或深反应离子刻蚀做孔时困难度，提高做孔效率。
进一步，在所述第一芯片10的焊球11位置与所述多个通孔213的位置对应时，所述第一芯片10可以直接通过所述多个通孔213内的导电材料与第二芯片20上的晶粒211电性连接。而在所述第一芯片10上的焊球11位置与所述多个通孔213的位置不对应时，就需要在所述第二芯片20与所述第一芯片10相对的表面上设置第二布线层23。具体地，所述第二布线层23设置于所述封装层21和所述第一芯片10之间，所述第二布线层23电性连接所述第一芯片10和所述通孔213内的导电材料。所述第二布线层23的层数可以根据需要设置，可以为一层，也可以为多层。所述第二布线层23采用晶圆级的溅射、电镀等工艺制作，通常为导电线如铜线的材料。
通过在所述第二芯片20与所述第一芯片10相对的表面上设置第二布线层23，从而使得在所述第一芯片10上的焊球11位置与所述多个通孔213的位置不对应时，所述第二布线层23可以电性连接所第一芯片10和所述通孔213内的导电材料。
另外，所述芯片堆叠封装结构100的芯片数目可以只包括第一芯片10和第二芯片20，如图1和图3所示，但，所述芯片堆叠封装结构100的芯片数目可以不限于两个。如图4所示，所述第二芯片20的数目为三个，也就是说，所述芯片堆叠封装结构100的芯片数目为四个。在其他实施方式中，所述第二芯片20的数目还可以为两个、四个等多个。
实施例二
基于同样的发明构思，本申请还提供一种电子设备。如图5所示，为本申请电子设备200的结构示意图。所述电子设备200包括电路板210和设置于所述电路板上的芯片堆叠封装结构220。所述芯片堆叠封装结构220与实施例一中的芯片堆叠封装结构100的结构和功能相同，在此不再赘述。所述芯片堆叠封装结构220的第二芯片20位于所述第一芯片10和所述电路板210之间。
上述电子设备200通过采用芯片堆叠封装结构220，在所述第二芯片20的至少两个晶粒211之间增加通孔213，从而使得晶粒211上向四周扇出输入输出走线可以直接通过该晶粒211周围的通孔213电性连接上芯片，从而减小占用布线层中的布线空间资源，提高布线空间的资源利用率，而且还会减小所述晶粒211与第一芯片10之间的走线长度，降低信号的负载，提高信号的性能，解决了现有技术中在所述下芯片的晶粒为两个或者两个以上时，一个晶粒(尤其该晶粒的输入输出走线较多时)上需要与上芯片连接的输入输出导线会占用布线层中的大部分布线空间资源，会影响下芯片的晶粒与晶粒之间的互连走线以及在布线层中的其它走线，从而造成走线困难或者增加布线层的层数的技术问题。
所述第二芯片20可以直接通过焊球电性连接于所述电路板210上，也可以如图6所示，在第二芯片20和所述电路板210之间设置一基板230，所述第二芯片20通过焊接凸点电性连接于所述基板230上，再通过焊球电性连接于所述电路板210上。所述基板230和所述第二芯片20之间可以根据需要选择是否填充底部填充胶(Underfill)来增强结构的强度和可靠性。通过在所述第二芯片20和所述电路板210之间设置所述基板230，可以通过基板230增加布线资源和封装的管脚数，改善第二芯片20的电源完整性，提高封装板级的可靠性。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要 求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。而且，本发明实施例中提到的“连接”一词如无特别结实应理解为是一种电性连接。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种芯片堆叠封装结构，其特征在于，所述芯片堆叠封装结构包括：
    第一芯片；
    第二芯片，与所述第一芯片堆叠设置，所述第二芯片包括：
    封装层，所述封装层包括至少两个晶粒和用于固定所述至少两个晶粒的固定部，所述固定部上开设有多个通孔，所述多个通孔的一部分通孔设置于所述至少两个晶粒外围，所述多个通孔的另一部分通孔设置于所述至少两个晶粒之间；和
    第一布线层，电性连接所述至少两个晶粒；
    其中，所述封装层位于所述第一布线层和所述第一芯片之间，所述多个通孔内设置有导电材料，通过所述导电材料电性连接所述第一布线层和所述第一芯片，使得所述第一芯片和所述至少两个晶粒中的至少一个晶粒之间能够电性连接。
  2. 如权利要求1所述的芯片堆叠封装结构，其特征在于，所述固定部具体为用于封装所述至少两个晶粒的封装部。
  3. 如权利要求1所述的芯片堆叠封装结构，其特征在于，所述固定部包括封装部和至少一个通孔模组，所述至少一个通孔模组上开设有所述多个通孔，所述封装部用于封装所述至少一个通孔模组和所述至少两个晶粒。
  4. 如权利要求3所述的芯片堆叠封装结构，其特征在于，所述至少一个通孔模组具体为印制电路板块或者硅通孔模组。
  5. 如权利要求1-4中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第二芯片还包括第二布线层，所述第二布线层设置于所述封装层和所述第一芯片之间，所述第二布线层电性连接所述第一芯片和所述导电材料。
  6. 如权利要求1-5中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片为存储芯片、硅晶粒、覆晶封装结构、或被动元件。
  7. 如权利要求1-6中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片具有与第二芯片相同的结构。
  8. 如权利要求1-7中任一权利要求所述的芯片堆叠封装结构，其特征在于，所述第一芯片和所述至少两个晶粒中的每个晶粒通过所述多个通孔中至少两个通孔内设置的所述导电材料电性连接。
  9. 一种电子设备，其特征在于，所述电子设备包括：
    电路板；
    设置于所述电路板上的如权利要求1-8中任一权利要求所述芯片堆叠封装结构，所述第二芯片位于所述第一芯片和所述电路板之间。
  10. 如权利要求9所述的电子设备，其特征在于，所述电子设备还包括设置于所述电路板和所述第二芯片之间并电性连接所述电路板和所述第二芯片的基板。
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