CN114450785A - 一种多芯片堆叠封装及制作方法 - Google Patents

一种多芯片堆叠封装及制作方法 Download PDF

Info

Publication number
CN114450785A
CN114450785A CN201980100933.9A CN201980100933A CN114450785A CN 114450785 A CN114450785 A CN 114450785A CN 201980100933 A CN201980100933 A CN 201980100933A CN 114450785 A CN114450785 A CN 114450785A
Authority
CN
China
Prior art keywords
chip
layer
conductive
hole
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980100933.9A
Other languages
English (en)
Inventor
李珩
张晓东
王思敏
戚晓芸
王正波
牛瑞
伍青青
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN114450785A publication Critical patent/CN114450785A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种多芯片堆叠封装及制作方法，涉及芯片技术领域，能够解决多芯片的应力集中问题，能够以进行更多层芯片的堆叠。该多芯片堆叠封装包括：沿第一方向堆叠设置的第一芯片(101)和第二芯片(102)，其中所述第一芯片(101)内沿所述第一方向开设有第一导电通孔(31)，所述第二芯片(102)内沿所述第一方向开设有第二导电通孔(32)；设置于所述第一芯片(101)和所述第二芯片(102)之间的第一再布线层(21)，且所述第一再布线层(21)的两侧分别与所述第一芯片(101)的表面和所述第二芯片(102)的表面固定，其中所述第一导电通孔(31)和所述第二导电通孔(32)通过所述第一再布线层(21)导通，所述第一导电通孔(31)和所述第二导电通孔(32)错开设置。所述多芯片堆叠封装及制作方法用于芯片的制造。

Description

PCT国内申请，说明书已公开。

Claims (15)

  1. PCT国内申请，权利要求书已公开。
CN201980100933.9A 2019-11-20 2019-11-20 一种多芯片堆叠封装及制作方法 Pending CN114450785A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/119799 WO2021097730A1 (zh) 2019-11-20 2019-11-20 一种多芯片堆叠封装及制作方法

Publications (1)

Publication Number Publication Date
CN114450785A true CN114450785A (zh) 2022-05-06

Family

ID=75980360

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980100933.9A Pending CN114450785A (zh) 2019-11-20 2019-11-20 一种多芯片堆叠封装及制作方法

Country Status (2)

Country Link
CN (1) CN114450785A (zh)
WO (1) WO2021097730A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117936459A (zh) * 2022-10-17 2024-04-26 长鑫存储技术有限公司 半导体切割方法
CN117976653A (zh) * 2022-10-21 2024-05-03 长鑫存储技术有限公司 一种封装结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311464A (ja) * 2003-04-01 2004-11-04 Renesas Technology Corp 半導体装置
CN104350593B (zh) * 2012-06-25 2017-12-05 英特尔公司 具有居间垂直侧边芯片的多管芯半导体结构及其半导体封装
US9087821B2 (en) * 2013-07-16 2015-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding with through substrate via (TSV)
KR102430496B1 (ko) * 2017-09-29 2022-08-08 삼성전자주식회사 이미지 센싱 장치 및 그 제조 방법

Also Published As

Publication number Publication date
WO2021097730A1 (zh) 2021-05-27

Similar Documents

Publication Publication Date Title
TWI399827B (zh) 堆疊晶粒的形成方法
US8970047B2 (en) Method for creating a 3D stacked multichip module
US20210125967A1 (en) Fully Interconnected Heterogeneous Multi-layer Reconstructed Silicon Device
US8421193B2 (en) Integrated circuit device having through via and method for preparing the same
US7951647B2 (en) Performing die-to-wafer stacking by filling gaps between dies
TW201822311A (zh) 用於散熱的封裝結構的製造方法
KR101107858B1 (ko) 반도체 기판을 위한 도전 필러 구조 및 그 제조 방법
US9559061B2 (en) Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
US11721663B2 (en) Multi-level stacking of wafers and chips
CN113257778B (zh) 一种3d堆叠且背部导出的扇出型封装结构及其制造方法
TW201310586A (zh) 半導體結構及其製造方法
US20230352439A1 (en) Multi-Level Stacking of Wafers and Chips
WO2021134940A1 (zh) 一种键合结构及其制造方法
CN111293109A (zh) 一种键合结构及其制造方法
CN114450785A (zh) 一种多芯片堆叠封装及制作方法
US20120193809A1 (en) Integrated circuit device and method for preparing the same
US20120168933A1 (en) Wafer level molding structure
EP2672511A1 (en) Method for creating a 3D stacked multichip module
CN115579324A (zh) 中介层结构及其制作方法
CN111834312A (zh) 一种基于tsv工艺的三维堆叠结构及制作方法
CN110828430A (zh) 一种封装结构及其制备方法
Maeda et al. Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications
WO2022160102A1 (zh) 芯片堆叠结构及其制备方法、芯片堆叠封装、电子设备
US20240153911A1 (en) Method for forming semiconductor device and semiconductor device fabricated thereby
WO2022261806A1 (zh) 芯片堆叠结构以及制作方法、晶圆堆叠结构、电子设备

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination