TW201310586A - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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Publication number
TW201310586A
TW201310586A TW101110511A TW101110511A TW201310586A TW 201310586 A TW201310586 A TW 201310586A TW 101110511 A TW101110511 A TW 101110511A TW 101110511 A TW101110511 A TW 101110511A TW 201310586 A TW201310586 A TW 201310586A
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Taiwan
Prior art keywords
wafer
substrate
distance
edge
wafers
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TW101110511A
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English (en)
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TWI528505B (zh
Inventor
Jing-Cheng Lin
Szu-Wei Lu
Ying-Ching Shih
ying-da Wang
Li-Chung Kuo
Long-Hua Lee
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201310586A publication Critical patent/TW201310586A/zh
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

本發明揭示一種半導體結構，其包括一基底、一第一晶片及一第二晶片。基底具有一第一表面及相對於第一表面的一第二表面，且基底具有一基底通孔電極，其自第一表面朝第二表面延伸。第一晶片貼附於基底，且第一晶片耦接至基底的第一表面。第二晶片貼附於基底，且第二晶片耦接至基底的第一表面。一第一距離位於第一晶片的一第一邊緣與第二晶片的一第一邊緣之間，第一距離位於平行基底的第一表面的一方向上，且第一距離等於或小於200微米。本發明亦揭示一種半導體結構之製造方法。

Description

半導體結構及其製造方法
本發明係有關於一種半導體技術，特別是有關於一種半導體結構及其製造方法。
隨著積體電路(integrated circuit,IC)的發展，使半導體業由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進而持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。增加的密度及對應減少的積體電路面積通常勝於將積體電路晶片直接接合至基底上。
使用不同封裝技術以利用額外的尺寸之便而獲得不同的目的。一種封裝為晶片或多晶片位於中介板(interposer)上。中介板已使用於將晶片的球接觸區域重佈於中介板的較大區域。另一發展形式係晶片堆疊位於主動晶片(active die)上。上述形式容許一封裝體包括多重晶片及縮小封裝尺寸(package footprint)。
在製程期間，封裝體中的中介板或底部主動晶片通常包括基底通孔電極(through substrate via,TSV)，其也稱為半導體通孔電極或矽通孔電極，且其他晶片通常在分割晶圓上的中介板或底部主動晶片之前，貼附於中介板或底部主動晶片上。
在進行貼附晶片步驟之後，具有中介板或底部主動晶片的晶圓通常會進一步加工，包括不同的熱製程。底膠(underfill)的熱膨脹係數(coefficient of thermal expansion,CTE)或收縮會在熱製程期間造成晶圓彎曲變形。此彎曲變形會提供一應力至TSV或封裝體的其他部件，例如底膠材料或凸塊(bump)。此應力會在TSV內造成裂縫、在凸塊內造成裂縫或使底膠材料發生剝離(delamination)。
在本發明一實施例中，一種半導體結構，包括：一基底，具有一第一表面及相對於第一表面的一第二表面，且基底具有一基底通孔電極，其自第一表面朝第二表面延伸；一第一晶片，貼附於基底，且第一晶片耦接至基底的第一表面；以及一第二晶片，貼附於基底，且第二晶片耦接至基底的第一表面，其中一第一距離位於第一晶片的一第一邊緣與第二晶片的一第一邊緣之間，第一距離位於平行基底的第一表面的一方向上，且第一距離等於或小於200微米。
在本發明另一實施例中，一種半導體結構包括：一基底，具有一第一表面及相對於第一表面的一第二表面，且基底具有一基底通孔電極，其自第一表面朝第二表面延伸；一第一晶片，貼附於基底，且第一晶片耦接至基底的第一表面；一第二晶片，貼附於基底，且第二晶片耦接至基底的第一表面，其中一第一距離位於第一晶片的一第一邊緣與第二晶片的一第一邊緣之間，第一晶片的第一邊緣與第二晶片的第一邊緣為第一相鄰晶片邊緣，且第一距離等於或大於380微米；以及一底膠材料，位於第一晶片的第一邊緣與第二晶片的一第二邊緣之間。
在本發明又一實施例中，一種半導體結構之製造方法包括：將至少二個晶片貼附於一基底的一第一表面，基底具有一基底通孔電極自第一表面延伸，上述晶片具有一平均間隔，位於上述晶片之間，其中平均間隔位於平行基底的第一表面的一方向上，且平均間隔等於或小於200微米；以及在貼附上述晶片之後，對基底的一第二表面進行加工，其中第二表面係相對於第一表面。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下實施例對照一特定背景進行說明。亦即2.5維積體電路(2.5 dimensional IC,2.5DIC)結構，其具有晶片貼附於被動(passive)中介板。其他實施例也可實施於3維積體電路(3DIC)，其具有堆疊的主動晶片或實施於具有晶片貼附於被動(passive)中介板的2.5DIC結構等等。
請參照第1A及1B圖，其分別繪示出根據本發明一實施例之4晶片式2.5維積體電路(2.5DIC)結構10的剖面及平面佈局示意圖。4晶片式2.5DIC結構10包括一被動(passive)中介板12，其具有分別透過第一連接器26、第二連接器28、第三連接器30及第四連接器32而貼附於其上的第一晶片18、第二晶片20、第三晶片22及第四晶片24。連接器26、28、30及32可為導電凸塊，例如微凸塊，且將各自的晶片18、20、22及24電性及實體耦接至被動中介板12。被動中介板12包括位於一基底13內的基底通孔電極(TSV)14(其在習知技藝中也稱作半導體通孔電極或矽通孔電極)以及位於基底13的前側表面上的重佈線層(redistribution layer,RDL)16。不同的凸塊接墊位於重佈線層16上(未繪示)，且連接至各自的連接器26、28、30及32。不同的凸塊接墊經由重佈線層16而電性耦接至各自的基底通孔電極14。一底膠材料34位於連接器26、28、30及32之間及其周圍，且位於被動中介板12與各個晶片18、20、22及24之間。底膠材料34也位於相鄰的晶片之間，例如位於第一晶片18與第二晶片20之間；位於第二晶片20與第三晶片22之間以及位於第三晶片22與第四晶片24之間。
值得注意的是另一實施例採用一主動晶片(包括基底通孔電極及主動裝置)，取代被動中介板12而形成3DIC結構。再者，被動中介板12可具有一裝置，其位於基底13內，使被動中介板12成為一主動中介板。
中介板12上的晶片之間距有三個間隙。第一間隙位於第一晶片18與第二晶片20之間，且具有一第一距離40。第二間隙位於第二晶片20與第三晶片22之間，且具有一第二距離42。第三間隙位於第三晶片22與第四晶片24之間，且具有一第三距離44。
三個間隙具有一距離值，其控制2.5DIC結構10的彎曲變形。該值可敘述為相鄰晶片之間的間隙的一平均距離。平均距離可定為晶片數量的函數，且平均距離可控制4晶片式2.5DIC結構10的臨界彎曲變形值。更特別的是平均距離可以第5圖的曲線圖來表示，以下有更詳細的說明。需注意的是間隙的距離雖然可彼此相等，但不一定要彼此相等。上述的距離可具有不同值，但在實施例中，所有距離的總合相等或小於平均距離與間隙數量的乘積。
在本實施例中，假定具有基底13的12吋晶圓中彎曲變形的撓曲度(deflection)為600微米，因其在該撓曲度有顯著的底膠剝離、凸塊破裂及/或基底通孔電極破裂發生，且在該撓曲度時，會影響到基底13的背側製程的進行。第一晶片18、第二晶片20、第三晶片22及第四晶片24各具有一厚度，例如在垂直中介板12的前側表面的方向上，其為770微米。中介板12具有一連結的晶片貼附區(其約為680平方毫米(square millimeter))供中介板12的前側表面上的第一晶片18、第二晶片20、第三晶片22及第四晶片24之用。在這些條件下，2.5DIC結構10中三個間隙的平均距離為50微米或以下，例如，每一間隙的距離為50微米或以下。因此，三個間隙的距離總合為50微米或以下，且三個間隙的距離可具有相等或不等的配置。如第2圖所示，只要平均晶片對晶片間隔(第1A及1B圖中的距離40、42及44)維持在50微米或以下，彎曲變形(例如，4晶片式2.5DIC結構10在製程期間的晶圓撓曲度)不會超過600微米。
假設所有其他條件如以上所述，在具有超過4個晶片的結構中，平均間隔的極限為50微米或以下。因此，在具有4個間隙的5晶片式結構中，間隙距離的總合為200微米或以下。如以上所述，間隙距離可相等或不等。
請參照第3A及3B圖，其分別繪示出根據本發明另一實施例之3晶片式2.5DIC結構70的剖面及平面佈局示意圖。3晶片式2.5DIC結構70的結構相似於第1A及1B圖中的4晶片式2.5DIC結構10。3晶片式2.5DIC結構70包括分別透過第一連接器26、第二連接器28及第三連接器30而貼附至中介板12的第一晶片18、第二晶片20及第三晶片22。在此3晶片式2.5DIC結構70中，具有二個間隙，其位於對應的相鄰晶片之間。一間隙位於第一晶片18與第二晶片20之間，且具有一第一距離72，且另一間隙位於第二晶片20與第三晶片22之間，且具有一第二距離74。
如以上所述，間隙具有一距離值以控制具有基底13的晶圓的彎曲變形，且該值可為一平均距離，其取決於晶片數量。在相同於對照先前第1A及1B圖中的4晶片式2.5DIC結構10的尺寸下，中介板上因具有較少的晶片，而具有不同的晶片面積。3晶片式2.5DIC結構70中晶片之間的間隙的平均距離約為125微米或以下，例如，每一間隙的距離可為125微米或以下。
請參照第4A及4B圖，其分別繪示出根據本發明另一實施例之2晶片式2.5DIC結構80的剖面及平面佈局示意圖。2晶片式2.5DIC結構80的結構相似於第1A及1B圖中的4晶片式2.5DIC結構10。2晶片式2.5DIC結構80包括分別透過第一連接器26及第二連接器28而貼附至中介板12的第一晶片18及第二晶片20。在此2晶片式2.5DIC結構80中，具有一個間隙位於相鄰晶片之間。間隙位於第一晶片18與第二晶片20之間，且具有一第一距離82。
如以上所述，間隙具有一距離值以控制具有基底13的晶圓的彎曲變形，且該值可為一距離，其取決於晶片數量。在相同於對照先前第1A及1B圖中的4晶片式2.5DIC結構10的尺寸下，中介板上具有不同的晶片面積。2晶片式2.5DIC結構80中晶片之間的間隙的平均距離約為200微米或以下。
第5圖係繪示出結構在不同晶片數量下，對應的平均間隙距離，以控制結構的彎曲變形。如先前所述，在4晶片式或以上的結構中，平均間隙距離具有一平均間隙距離值為50微米或以下。在4晶片式或以上的結構中，平均距離的極限約為50微米或以下。在3晶片式的結構中，平均間隙距離的極限約為125微米或以下。在2晶片式的結構中，間隙距離的極限約為200微米或以下。如以上所述，平均間隙距離可小於上述這些數值。因此，結構中相鄰晶片之間的間隙可分別小於上述對應結構的數值。
第6圖係繪示出實施例進一步的特徵。第6圖係繪示出從一加工晶圓切割而成的晶片90。每一晶片90包括一主動區92，其被一密封環94所圍繞。在實施例中，一切割刀具的寬度縮小，造成分割的晶片90之間形成較窄的切口寬度96。晶片90在密封環94與晶片邊緣之間可具有多餘的晶圓基底材料，例如具有一距離98或100。舉例來說，各個距離98及100可等於或大於15微米。
透過使用較窄的切割刀具或是設計較寬的切割道，可將實施例整合至現行的製程中。舉例來說，可不修正晶圓的製程而獲得在密封環94與晶片邊緣之間具有多餘的基底材料的晶片。再者，中介板12或主動晶片上用來連接晶片90的連接器，其尺寸可不需改就可達到以上所述的間隙距離。多餘的材料可使晶片具有較大的面積，以降低相鄰晶片之間的距離。
第7圖係繪示出2晶片式2.5DIC結構110的剖面示意圖。2晶片式2.5DIC結構110相似於第4A圖中2晶片式2.5DIC結構80。在第7圖的2晶片式2.5DIC結構110中，2晶片式2.5DIC結構80的第一晶片18取代為晶片90。晶片90貼附於中介板12的前側，其具有尺寸小於晶片90面積的連接器112。沿著晶片90外部區域的多餘材料具有距離98，其縮減晶片90與第二晶片20之間的間隙距離，而得到第4A圖中所揭示的距離。可以理解的是實施例中可將晶片90的特徵使用於結構中所有的晶片、某些晶片或無晶片被使用，且可使用於具有任何數量的晶片的結構中。
請再參照第2圖，透過在晶片之間形成較大的平均距離，可控制結構的彎曲變形，例如撓曲度低於600微米。在這些實施例中，間片對晶片間隔可大於380微米，例如在380至600微米範圍。晶片對晶片間隔可為具有任何數量的晶片的結構中平均間隙距離。
再者，在這些實施例中，底膠材料連結了相鄰晶片之間的間隙。第8A及8B圖係繪示出具有不同間隙距離的相鄰晶片，且具有底膠材料連結間隙的局部影像圖。除了平均間隙距離在380微米至600微米之外，具有第8A及8B圖所示間隙的結構可相似於第1A、1B、3A、3B、4A及4B圖所示的結構。在第8A圖中，結構包括貼附於一基底101上的一第一晶片102及一第二晶片103。一底膠材料104位於第一晶片102與第二晶片103之間而連結間隙距離105。在本實施例中，間隙距離105約為400微米，例如397微米。在第8B圖中，結構相似於第8A圖中的結構，且間隙距離107約為500微米，例如497微米。一底膠材料106位於第一晶片102與第二晶片103之間而連結間隙距離107。
第9A至9H圖係繪示出根據一實施例之半導體結構製造方法剖面示意圖，例如第4A圖中2晶片式結構80或是第8A或8B圖中的結構。可以理解的是圖式中步驟順序僅作為解釋之用，然而也可使用其他步驟順序。再者，任何所屬技術領域中具有通常知識者可以理解可對上述製造方法進行修正而形成其他結構以及在其他實施例中的結構。
請參照第9A圖，一基底13，其為晶圓的一部分，且具有基底通孔電極14穿過基底13的前側。基底13可具有主動裝置形成於基底13的前側表面內，因而構成用於3DIC結構的晶片。基底13可不具有主動裝置，因而構成用於2.5DIC結構的被動中介板。在其他實施例中，基底13可具有主動裝置形成於基底13內，且為用於2.5DIC結構的主動中介板。
基底13通常包括一材料，其相似於形成晶片所使用的基底且貼附於中介板，例如矽。同時，基底13也可為其他材料。使用矽基底作為中介板或晶片可減少應力，其原因在於矽基底與用於晶片的矽之間的熱膨脹係數(coefficient of thermal expansion,CTE)不匹配是低於由其他材料所構成的基底。
基底通孔電極(TSV)14的製做是透過蝕刻、鑽孔、雷射技術或其組合等，在基底13內形成凹口。可透過化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)、物理氣相沉積(physical vapor deposition,PVD)、熱氧化或其組合等等而在基底13的前側上及開口內順應性地沉積一薄阻障層。阻障層可包括一氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢或其組合等等。一導電材料沉積於薄阻障層上及開口內。導電材料可透過電化學電鍍(electrochemical plating,ECP)、CVD、ALD、PVD或其組合等等而形成。導電材料可為銅、鎢、鋁、銀、金或其組合等等。可透過化學機械研磨(chemical mechanical polishing,CMP)自基底13的前側去除多餘的導電材料及阻障層。因此，基底通孔電極14包括導電材料及位於導電材料與基底13之間的薄阻障層。
請參照第9B圖，繼續進行前側製程，以製做重佈線層(RDL)16。重佈線層16可包括任何數量或組合的金屬化層、金屬層間介電(inter-metal dielectric,IMD)層、介層窗(via)及鈍化保護層。繪示於第9B圖的重佈線層16包括位於IMD層內的3層金屬化層，例如一第一金屬化層(M1)120、一第二金屬化層(M2)122及一第三金屬化層(M3)124。介層窗形成於IMD層內金屬化層之間。金屬化層的製做是透過沉積IMD層、利用可接受的微影技術蝕刻出IMD層內的膜層金屬化圖案、在IMD層內沉積用以金屬化的導電材料以及利用CMP去除任何多餘的導電材料。特別的是當形成的介層窗穿過IMD層至下方的金屬化層時，微影技術可包括單鑲嵌製程或雙鑲嵌製程。
IMD層可為氧化界墊層，例如硼磷矽玻璃(borophosphosilicate glass,BPSG)或其他介電材料。金屬化層的導電材料可為銅、鎳、鋁、銅鋁合金、鎢、鈦、及其組合等等。金屬化層可包括位於導電材料與IMD層之間的阻障層(例如氮化鈦、氮化鉭等等或其組合)，且其他介電層，例如蝕刻終止層(其可由氮化矽所構成)，可形成於IMD層之間。
在形成頂部金屬化層(第9B圖的第三金屬化層124)之後，一或多個鈍化保護層形成於金屬化層上。鈍化保護層可為聚亞醯胺(polyimide)、BPSG、氮化矽或其組合等等，且可透過旋塗技術、CVD、ALD、PVD或其組合等等而形成。形成穿過鈍化保護層的開口126，以露出頂層金屬化層(第9B圖的第三金屬化層124)，以在金屬化層上製做凸塊接合墊。可透過可接後的微影及蝕刻技術形成開口126。
請參照第9C圖，凸塊接合墊128經由開口126形成於頂部金屬層上，且導電凸塊130形成於凸塊接合墊128上。導電凸塊130通常對應於第一連接器26及第二連接器28。凸塊接合墊128可透過在開口126內沉積一導電材料並圖案化導電材料而形成凸塊接合墊128。導電材料可包括銅、鋁、錫、鈦、鎢或其組合等等，且可透過PVD、CVD、ALD或其組合等等而形成。可透過可接受的微影及蝕刻技術來進行凸塊接合墊128的圖案化。可透過ECP等，在凸塊接合墊128上導電凸塊130，且其包括銅、錫、鎳或其組合等。
請參照第9D圖，第一晶片18及第二晶片20透過導電凸塊130來進行貼附。第一晶片18與第二晶片20之間具有間隙，第一晶片18與第二晶片20之間的每一間隙具有距離82，如第4A及4B圖或第8A及8B圖所述。底膠材料34位於凸塊130周圍以及第一晶片18及第二晶片20與中介板12或主動晶片之間。底膠材料34也位於第一晶片18與第二晶片20之間的間隙內。
可根據可接受的半導體製程技術及裝置需求來製做第一晶片18及第二晶片20。在實施例中，第一晶片18及第二晶片20其中一或二者是根據第6圖來製做，其具有多餘的晶圓基底材料位於晶片邊緣與密封環之間。第一晶片18及第二晶片20可為習知良好晶片，利用拾放(pick-and-place)工具來進行貼附，且可在放置底膠材料34之前，對導電凸塊130進行回流(reflow)製程。底膠材料34可為液態環氧樹脂、可變形膠(deformable gel)、矽膠、乾膜或其組合等，且可使用可接受的噴塗或塗佈設備來製做。
請參照第9E圖，在固化底膠材料34之後，透過成形材料(molding compound)134及可使用壓縮成型來封裝晶片18及20。若成形材料134位於晶片18及20的上表面上，成形材料134可透過CMP來進行研磨，以露出晶片18及20的表面。
第9F圖係繪示出基底13的背側製程。在背側製程期間，第9E圖的晶圓上晶片(chip on wafer,CoW)貼附至一承載基底136。承載基底136可使用黏著劑而貼附於晶片18及20及/或成形材料134。一般來說，在後續製程步驟期間，承載基底136提供暫時性的物理及結構支撐。在此方式中，可降低或防止中介板或晶片的損害。承載基底136可包括玻璃、氧化矽、氧化鋁或其組合等等。黏著劑可為任何適當的黏著劑，例如紫外光(UV)膠，其在照射UV光後失去黏性。
在第9F圖中，基底通孔電極14透過基底13薄化製程而突出於基底13的背側。此薄化製程可透過蝕刻製程及/或平坦化製程(例如，CMP)來進行。舉例來說，一開始先進行平坦化製程，例如CMP，以露出基底通孔電極14的阻障層。之後，進行一或多道濕蝕刻製程，其在阻障層的材料與基底之間具有高蝕刻選擇比，藉以留下突出於基底13的背側的基底通孔電極14。蝕刻製程也可為乾蝕刻製程。一或多層介電層，例如第9F圖所示的介電層138及140，可沉積於基底13的背側。介電層138及140可為氧化矽、氮化矽、氮氧化矽或其組合等等。接著可透過CMP進行背側平坦化，而露出位於背側的基底通孔電極14。
第9G圖係繪示出鈍化保護層142、球接合墊144及導電接球146的製做。鈍化保護層142形成於介電層138及140的背側，且可為聚亞醯胺、BPSG、聚苯並噁唑(polybenzoxazole,PBO)或其組合等等，其可藉由旋轉塗佈技術、CVD、ALD或其組合等等而形成。形成穿過鈍化保護層142的開口，以露出基底通孔電極14來製做球接合墊144。可透過可接受的微影及蝕刻技術來製做開口。可透過沉積一導電材料於開口內並圖案化導電材料來製做球接合墊144，例如一或多層的鉻、鉻銅合金、銅、金、鈦、鈦鎢合金、鎳或其組合等等。可透過ECP及印刷等等來沉積導電材料，且可透過可接受的微影及蝕刻技術來進行圖案化。可透過ECP及印刷等等將導電接球146形成於球接合墊144上，且導電接球146可包括銅、錫、共晶(eutectic)焊料、鎳或其組合等等。
需注意的是第9G圖繪示出球接合墊144直接耦接於基底通孔電極14。然而，一或多層金屬化層及IMD層可形成於基底13的背側，以將球接合墊144電性耦接至基底通孔電極14。背側金屬化層可由任何適當的導電材料所形成，例如銅、銅合金、鋁、銀、金或其組合等等，且可任何適當的技術來製做，例如ECP、無電電鍍(electroless plating)或其他沉積方法，例如濺鍍、印刷、CVD、PVD或其組合等等。
接著將上述組件的導電接球146貼附至切割框(dicing frame)148，且去除承載基底136，如第9H圖所示。接著沿切割道150來切割上述組件成各個封裝體，其具有中介板及任何數量的晶片，例如第4A、8A或8B圖所示的結構80。
上述實施例可獲得以下的優點。在進行晶片貼附製程之後的製程期間，晶圓彎曲變形控制可透過控制晶片對晶片間隔而實現。此降低晶圓彎曲變形，其可降低結構中的應力，藉以減少TSV及/或凸塊發生破裂及/或發生底膠材料剝離。上述實施例因而可提供較大的製程容許度(process window)及良率。同樣地，因為降低彎曲變形而引發問題的風險，晶圓的管理更為容易。再者，上述實施例中晶片之間的電性導線更為縮短而提供較小的電阻值及電容值。
在一實施例中，一種半導體結構包括：一基底、一第一晶片及一第二晶片。基底具有一第一表面及相對於第一表面的一第二表面，且基底具有一基底通孔電極，其自第一表面朝第二表面延伸。第一晶片貼附於基底，且第一晶片耦接至基底的第一表面。第二晶片貼附於基底，且第二晶片耦接至基底的第一表面。一第一距離位於第一晶片的一第一邊緣與第二晶片的一第一邊緣之間，第一距離位於平行基底的第一表面的一方向上，且第一距離等於或小於200微米。
在另一實施例中，一種半導體結構包括：一基底及至少二個晶片。基底具有一基底通孔電極自基底的一第一表面延伸。上述晶片分別耦接至基底的第一表面，且上述晶片具有一平均間隔，位於上述晶片之間。平均間隔位於平行基底的第一表面的一方向上，且平均間隔等於或小於200微米。
在另一實施例中，一種半導體結構包括：一基底、第一晶片、第二晶片及一底膠材料。基底具有一第一表面及相對於第一表面的一第二表面，且基底具有一基底通孔電極，其自第一表面朝第二表面延伸。第一晶片貼附於基底，且第一晶片耦接至基底的第一表面。第二晶片貼附於基底，且第二晶片耦接至基底的第一表面。一第一距離位於第一晶片的一第一邊緣與第二晶片的一第一邊緣之間，且第一晶片的第一邊緣與第二晶片的第一邊緣為第一相鄰晶片邊緣。第一距離等於或大於380微米。底膠材料位於第一晶片的第一邊緣與第二晶片的一第二邊緣之間。
又一實施例中，一種半導體結構之製造方法包括：將至少二個晶片貼附於一基底的一第一表面。基底具有一基底通孔電極自第一表面延伸。上述晶片具有一平均間隔，位於上述晶片之間，其中平均間隔位於平行基底的第一表面的一方向上。平均間隔等於或小於200微米。上述方法更包括在貼附上述晶片之後，對基底的一第二表面進行加工，其中第二表面係相對於第一表面。
雖然本發明實施例及其優點已詳細揭露如上，然而可以理解的是其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
10．．．4晶片式2.5維積體電路結構
12．．．被動中介板
13、101．．．基底
14．．．基底通孔電極
16．．．重佈線層
18、102．．．第一晶片
20、103．．．第二晶片
22．．．第三晶片
24．．．第四晶片
26．．．第一連接器
28．．．第二連接器
30．．．第三連接器
32．．．第四連接器
34、104、106．．．底膠材料
40、72、82．．．第一距離
42、74．．．第二距離
44．．．第三距離
70．．．3晶片式2.5維積體電路結構
80、110．．．2晶片式2.5維積體電路結構
90．．．晶片
92．．．主動區
94．．．密封環
82、98、100．．．距離
105、107．．．間隙距離
112．．．連接器
120．．．第一金屬化層
122．．．第二金屬化層
124．．．第三金屬化層
126．．．開口
128．．．凸塊接合墊
130．．．導電凸塊
134．．．成形材料
136．．．承載基底
138、140．．．介電層
142．．．鈍化保護層
144．．．球接合墊
146．．．導電接球
148．．．切割框
150．．．切割道
第1A及1B圖係分別繪示出根據本發明一實施例之四晶片式2.5維積體電路(2.5DIC)結構的剖面及平面佈局示意圖；
第2圖係繪示出晶圓的彎曲變形與具有第1A及1B圖中結構的晶片對晶片間隔之間關係曲線圖；
第3A及3B圖係分別繪示出根據本發明另一實施例之三晶片式2.5DIC結構的剖面及平面佈局示意圖；
第4A及4B圖係分別繪示出根據本發明又另一實施例之二晶片式2.5DIC結構的剖面及平面佈局示意圖；
第5圖係繪示出根據本發明一實施例之結構上的晶片數量與平均間隙距離的函數曲線圖；
第6圖係繪示出根據本發明一實施例之將晶圓分割成晶片的示意圖；
第7圖係繪示出根據本發明一實施例之具有第6圖中晶片的二晶片式2.5DIC結構剖面示意圖；
第8A及8B圖係繪示出根據本發明實施例之結構的局部影像圖；以及
第9A至9H圖係繪示出根據本發明一實施例之半導體結構之製造方法剖面示意圖。
10．．．4晶片式2.5維積體電路結構
12．．．被動中介板
13．．．基底
14．．．基底通孔電極
16．．．重佈線層
18．．．第一晶片
20．．．第二晶片
22．．．第三晶片
24．．．第四晶片
26．．．第一連接器
28．．．第二連接器
30．．．第三連接器
32．．．第四連接器
34．．．底膠材料
40．．．第一距離
42．．．第二距離
44．．．第三距離

Claims (10)

  1. 一種半導體結構，包括：一基底，具有一第一表面及相對於該第一表面的一第二表面，且該基底具有一基底通孔電極，其自該第一表面朝該第二表面延伸；一第一晶片，貼附於該基底，且該第一晶片耦接至該基底的該第一表面；以及一第二晶片，貼附於該基底，且該第二晶片耦接至該基底的該第一表面，其中一第一距離位於該第一晶片的一第一邊緣與該第二晶片的一第一邊緣之間，該第一距離位於平行該基底的該第一表面的一方向上，且該第一距離等於或小於200微米。
  2. 如申請專利範圍第1項所述之半導體結構，更包括一第三晶片，貼附於該基底，且該第三晶片耦接至該基底的該第一表面，其中一第二距離位於該第二晶片的一第二邊緣與該第三晶片的一第一邊緣之間，該第二距離位於平行該基底的該第一表面的一方向上，且該第一距離與該第二距離的總合等於或小於250微米。
  3. 如申請專利範圍第2項所述之半導體結構，更包括一第四晶片，貼附於該基底，且該第四晶片耦接至該基底的該第一表面，其中一第三距離位於該第三晶片的一第二邊緣與該第四晶片的一第一邊緣之間，該第三距離位於平行該基底的該第一表面的一方向上，且該第二距離及該第三距離等於或小於150微米。
  4. 如申請專利範圍第1項所述之半導體結構，其中該基底為一中介板或一主動晶片基底。
  5. 一種半導體結構，包括：一基底，具有一第一表面及相對於該第一表面的一第二表面，且該基底具有一基底通孔電極，其自該第一表面朝該第二表面延伸；一第一晶片，貼附於該基底，且該第一晶片耦接至該基底的該第一表面；一第二晶片，貼附於該基底，且該第二晶片耦接至該基底的該第一表面，其中一第一距離位於該第一晶片的一第一邊緣與該第二晶片的一第一邊緣之間，該第一晶片的該第一邊緣與該第二晶片的該第一邊緣為第一相鄰晶片邊緣，且該第一距離等於或大於380微米；以及一底膠材料，位於該第一晶片的該第一邊緣與該第二晶片的一第二邊緣之間。
  6. 如申請專利範圍第5項所述之半導體結構，更包括一第三晶片，貼附於該基底，且該第三晶片耦接至該基底的該第一表面，其中一第二距離位於該第二晶片的該第二邊緣與該第三晶片的一第一邊緣之間，該第二晶片的該第二邊緣與該第三晶片的該第一邊緣為第二相鄰晶片邊緣，且該第二距離的大於380微米。
  7. 如申請專利範圍第6項所述之半導體結構，更包括一第四晶片，貼附於該基底，且該第三晶片耦接至該基底的該第一表面，其中一第三距離位於該第三晶片的一第二邊緣與該第四晶片的一第一邊緣之間，該第三晶片的該第二邊緣與該第四晶片的該第一邊緣為第三相鄰晶片邊緣，且該第三距離的大於380微米。
  8. 如申請專利範圍第5項所述之半導體結構，其中該基底為一中介板、一主動晶片基底或其組合。
  9. 一種半導體結構之製造方法，包括：將至少二個晶片貼附於一基底的一第一表面，該基底具有一基底通孔電極自該第一表面延伸，該等晶片具有一平均間隔，位於該等晶片之間，其中該平均間隔位於平行該基底的該第一表面的一方向上，且該平均間隔等於或小於200微米；以及在貼附該等晶片之後，對該基底的一第二表面進行加工，其中該第二表面係相對於該第一表面。
  10. 如申請專利範圍第9項所述之半導體結構之製造方法，其中該加工步驟包括經由該基底的該第二表面露出該基底通孔電極。
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TWI528505B (zh) 2016-04-01
US20130049216A1 (en) 2013-02-28
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CN102969305A (zh) 2013-03-13
DE102012100796B4 (de) 2020-03-12
DE102012100796A1 (de) 2013-02-28
US20150125994A1 (en) 2015-05-07
KR101420855B1 (ko) 2014-07-18
US10157879B2 (en) 2018-12-18
US8963334B2 (en) 2015-02-24

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