TWI455263B - 晶片封裝結構及晶片封裝方法 - Google Patents

晶片封裝結構及晶片封裝方法 Download PDF

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Publication number
TWI455263B
TWI455263B TW098104827A TW98104827A TWI455263B TW I455263 B TWI455263 B TW I455263B TW 098104827 A TW098104827 A TW 098104827A TW 98104827 A TW98104827 A TW 98104827A TW I455263 B TWI455263 B TW I455263B
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Taiwan
Prior art keywords
package structure
electrodes
chip package
substrate
bumps
Prior art date
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TW098104827A
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English (en)
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TW201032303A (en
Inventor
Tao Chih Chang
Su Tsai Lu
Chau Jie Zhan
Chun Chih Chuang
Jing Ye Juang
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Ind Tech Res Inst
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Priority to TW098104827A priority Critical patent/TWI455263B/zh
Priority to US12/426,967 priority patent/US20100207266A1/en
Publication of TW201032303A publication Critical patent/TW201032303A/zh
Application granted granted Critical
Publication of TWI455263B publication Critical patent/TWI455263B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Description

晶片封裝結構及晶片封裝方法
本發明是有關於一種電子元件及封裝方法(package method)，且特別是有關於一種晶片封裝結構(chip package structure)及晶片封裝方法。
半導體晶片通常不單獨存在，而是透過輸出入系統與其他晶片、電路相互連接，且半導體晶片及內部電路非常複雜，需要晶片封裝體來保護及攜帶。晶片封裝的主要功能包括：(1)提供電流路徑以驅動晶片上的電路；(2)分佈晶片進出之訊號；(3)將電路產生的熱能發散至外界；以及(4)在具破壞性的環境中保護晶片。
現今應用於晶片封裝的承載器種類琳瑯滿目，包括導線架(lead frame)、線路基板(circuit substrate)等等，而可以形成各式各樣的封裝結構。近年來，半導體晶片的積集度逐漸提高，多功能、高容量、高處理速度但面積極小的產品相形增加，相對地，晶片封裝技術的發展也朝向高密度、高腳數(high pin count)、高頻率及高效能的趨勢發展。
在各種晶片封裝技術中，覆晶接合技術(flip chip bonding technology，簡稱FC)特別適合應用於高階之晶片封裝領域，其主要是利用面陣列(area array)的方式，將多個凸塊墊(bumping pad)配置於晶片之主動表面(active surface)上，並在凸塊墊上形成凸塊(bump)。接著，將晶片翻覆(flip)之後，再透過這些凸塊使晶片表面之凸塊墊分別電性(electrically)及結構性(structurally)連接至承載器上的接點(contact)，使得晶片可經由凸塊而電性連接至承載器，並經由承載器之內部線路而電性連接至外界之電子裝置。
覆晶接合技術可適用於高腳數之晶片封裝結構，並同時具有縮小晶片封裝面積及縮短訊號傳輸路徑等諸多優點。隨著晶片封裝技術朝高腳數發展，接點的可靠度便越來越重要，其對晶片封裝結構的製造良率及可靠度會有很大的影響。因此，如何提升接點的可靠度便成為晶片封裝技術的重要課題之一。
本發明提供一種晶片封裝結構，其基板上的電極與凸塊之間的接合可靠度較高。
本發明提供一種晶片封裝方法，其可提升凸塊與基板上的電極之間的接合可靠度。
本發明之一實施例提出一種晶片封裝結構，其包括一基板、多個電極、一晶片及多個凸塊。每一電極具有一底部及一環狀元件。底部配置於基板上，而環狀元件配置於底部上，其中底部與環狀元件定義出一容置凹陷。晶片配置於基板上方，並具有一面向基板的主動表面及位於主動表面上的多個第一接墊。這些凸塊分別配置於這些第一接墊上，並分別嵌入這些容置凹陷中，其中這些電極的熔點大於這些凸塊的熔點。
在本發明之一實施例中，基板例如是線路載板(circuit board)。
在本發明之一實施例中，晶片封裝結構更包括多個凸塊下金屬層(under bump metal,UBM)，其分別連接這些凸塊和這些第一第一接墊。
在本發明之一實施例中，凸塊與主動表面平行的方向上之寬度等於環狀元件之內徑。
在本發明之一實施例中，這些凸塊的熱膨脹係數(coefficient of thermal expansion)大於這些電極的熱膨脹係數。
在本發明之一實施例中，環狀元件為多邊形環狀元件、圓形環狀元件或橢圓形環狀元件。
在本發明之一實施例中，每一電極更包括一導電柱，其配置於底部上，並位於容置凹陷中，且導電柱與環狀元件之間保持間隔。導電柱例如呈一幾何形狀。
在本發明之一實施例中，晶片封裝結構更包括一封裝膠體，其配置於基板與晶片之間，並包覆這些電極及這些凸塊。
在本發明之一實施例中，基板具有相對之一第一表面及一第二表面，而這些電極是配置於第一表面。晶片封裝結構可更具有多個導電貫通孔道(conducting via)，這些導電貫通孔道貫穿基板，並由第一表面延伸至第二表面。這些導電貫通孔道電性連接這些電極。
在本發明之一實施例中，晶片封裝結構更包括一第一圖案化導電層、一第二圖案化導電層及多個錫球。第一圖案化導電層配置於基板之第一表面上，其中部分第一圖案化導電層構成這些電極之這些底部，且這些導電貫通孔道與第一圖案化導電層連接，以使這些導電貫通孔道與這些電極電性連接。第二圖案化導電層配置於基板之第二表面上，其中第二圖案化導電層形成多個第二接墊，且這些第二接墊與這些導電貫通孔道電性連接。這些錫球分別配置於這些第二接墊上。
在本發明之一實施例中，這些凸塊分別與這些電極以化學鍵結接合。這些電極的材質可包括銅及鎳至少其中之一，且這些凸塊的材質可包括錫。
在本發明之一實施例中，這些凸塊分別與這些電極以物理接觸接合。這些電極的材質可包括鉑、銅及鈦至少其中之一，且這些凸塊的材質可包括金及鎳本發明之另一實施例提出一種晶片封裝結構，其包括一基板、多個電極、一晶片及多個凸塊。每一電極具有一底部及一環狀元件。底部配置於基板上。環狀元件包括一第一金屬環及一第二金屬環。第一金屬環配置於底部上。第二金屬環配置於底部上，並連接至第一金屬環的內側。第二金屬環與底部定義出一容置凹陷。晶片配置於基板上方，並具有一面向基板的主動表面及位於主動表面上的多個第一接墊。這些凸塊分別配置於這些第一接墊上，並分別嵌入這些容置凹陷中，其中這些電極的熔點大於這些凸塊的熔點。
在本發明之一實施例中，每一電極之第一金屬環的熱膨脹係數小於此電極之第二金屬環的熱膨脹係數。第一金屬環與第二金屬環的材質例如為形狀記憶合金。
本發明之又一實施例提出一種晶片封裝結構，其包括一基板、多個電極、一晶片、多個凸塊及一封裝膠體。每一電極具有一底部及一環狀元件。底部配置於基板上，而環狀元件配置於底部上，其中底部與環狀元件定義出一容置凹陷。晶片配置於基板上方，並具有一面向基板的主動表面及位於主動表面上的多個第一接墊。這些凸塊分別配置於這些第一接墊上，並分別嵌入這些容置凹陷中。封裝膠體配置於基板與晶片之間，並包覆這些電極及這些凸塊。封裝膠體對每一環狀元件施加壓力，以使環狀元件之遠離底部的一端往對應的凸塊彎曲而夾持之。
本發明之再一實施例提出一種晶片封裝方法，其包括下列步驟。首先，提供一基板。接著，形成多個電極，其中每一電極具有一底部及一環狀元件。底部位於基板上，環狀元件配置於底部上，且底部與環狀元件定義出一容置凹陷。再來，充填一封裝膠體於基板。封裝膠體包覆這些電極，且封裝膠體的平均液面高度低於每一電極的環狀元件之自由端的高度。此外，提供一晶片。接著，形成多個第一接墊於晶片之主動表面，這些第一接墊上分別配置有多個凸塊。之後，使晶片的主動表面朝向基板，並使這些凸塊分別置入這些容置凹陷中，其中主動表面會擠壓封裝膠體，以使封裝膠體對每一環狀元件施加壓力，進而使環狀元件之自由端往對應的凸塊彎曲而夾持之。
在本發明之一實施例中，當在基板上形成封裝膠體時，封裝膠體在鄰接每一環狀元件之處的液面高度與環狀元件之遠離底部的自由端之高度實質上相等，且封裝膠體的液面高度由這些電極往這些電極之間的位置遞減。
在本發明之一實施例中，在使這些凸塊分別置入這些容置凹陷之後，晶片封裝方法更包括使該封裝膠體固化。
基於上述，在本發明之實施例的晶片封裝結構中，由於凸塊是位於電極之環狀元件內，因此可藉由熱應力或封裝膠體對環狀元件所施加的液壓，而使電極之環狀元件對凸塊施以夾持力。如此一來，便可提升電極與凸塊之間的接合可靠度。此外，本發明之實施例之晶片封裝方法藉由封裝膠體對環狀元件所施加的液壓，而使電極之環狀元件對凸塊施以夾持力，因此電極與凸塊之間的接合可靠度可被提升。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A為本發明之一實施例之晶片封裝結構的剖面示意圖，而圖1B為圖1A中之電極的上視示意圖。請參照圖1A與圖1B，本實施例之晶片封裝結構100包括一基板110及多個電極120。基板110例如為一線路載板。每一電極120具有一底部122及一環狀元件124。底部122配置於基板110上，而環狀元件124配置於底部122上，其中底部122與環狀元件124定義出一容置凹陷R。
晶片封裝結構100更包括一晶片130及多個凸塊140。晶片130配置於基板110上方，並具有一面向基板110的主動表面132及位於主動表面132上的多個接墊134。這些凸塊140分別配置於這些接墊134上，具體而言，這些凸塊140可經由多個凸塊下金屬層(under bump metal,UBM)136分別配置於接墊134上，亦即這些凸塊下金屬層136分別連接這些凸塊140和這些接墊134。此外，這些凸塊140分別嵌入這些容置凹陷R中。
當這些凸塊140與電極120接合之前，凸塊140在與主動表面132平行的方向上之寬度可小於或等於環狀元件124的內徑。在本實施例中，這些凸塊140的熱膨脹係數大於這些電極120的熱膨脹係數，換言之，凸塊140的熱膨脹係數大於環狀元件124的熱膨脹係數。因此，當進行凸塊140與電極120的接合製程，而使晶片封裝結構100的溫度上升時，凸塊140會因受熱膨脹而將環狀元件124往外撐，亦即環狀元件124會對凸塊140施以一夾持之反作用力，而此時凸塊140在與主動表面132平行的方向上之寬度等於環狀元件124的內徑。如此一來，凸塊140與電極120之間的接合可靠度便能夠有效提升，進而提升晶片封裝結構100的製造良率及電性品質。
此外，在本實施例中，電極120的熔點大於凸塊140的熔點，此有助於凸塊140與電極120的接合製程之進行。另外，在本實施例中，這些凸塊140分別與這些電極120以化學鍵結接合，其中電極120的材質可包括銅及鎳至少其中之一，且凸塊140的材質可包括錫。然而，在其他實施例中，這些凸塊140亦可分別與這些電極120以物理接觸接合，其中電極120的材質可包括鉑、銅及鈦至少其中之一，且凸塊140的材質可包括金及鎳。
在本實施例中，環狀元件124為圓形環狀元件，如圖1B所繪示。然而，在另外四個實施例中，如圖2A、圖2B、圖2C及圖2D所繪示，電極120a、120b、120c、120d的環狀元件124a、124b、124c、124d亦可以分別為正方形環狀元件、長方形環狀元件、橢圓形環狀元件及三角形環狀元件。此外，在其他實施例中，環狀元件124亦可以用其他多邊形環狀元件或其他幾何形狀的環狀元件來取代。
在本實施例中，晶片封裝結構100更包括一封裝膠體150，其配置於基板110與晶片130之間，並包覆電極120與凸塊140。封裝膠體150可用以保護電極120與凸塊140。
在本實施例中，基板110具有相對之一第一表面112及一第二表面114，而電極120是配置於第一表面112。此外，在本實施例中，晶片封裝結構100更具有多個導電貫通孔道160，這些導電貫通孔道160貫穿基板110，並由第一表面112延伸至第二表面114。此外，這些導電貫通孔道160電性連接這些電極120。
具體而言，基板110之第一表面112上可配置有一第一圖案化導電層170，部分第一圖案化導電層170構成電極120之底部122，而導電貫通孔道160與第一圖案化導電層170連接，以使導電貫通孔道160與電極120電性連接。此外，基板110之第二表面114上可配置有第二圖案化導電層180，第二圖案化導電層180可形成多個接墊182，而接墊182與導電貫通孔道160電性連接。這些接墊182上可配置有多個錫球190，而這些錫球190可與另一線路載板(未繪示)連接。導電貫通孔道160係為一孔內充填有導電材料所構成。
圖3A為本發明之另一實施例之晶片封裝結構的剖面示意圖，而圖3B為圖3A中之電極的上視示意圖。請參照圖3A與圖3B，本實施例之晶片封裝結構100e與上述晶片封裝結構100(如圖1A所繪示)類似，而兩者的差異如下所述。在晶片封裝結構100e中，每一電極120e更包括一導電柱126，其配置於底部122上，並位於環狀元件124之容置凹陷R中，且導電柱126與環狀元件124之間保持間隔。導電柱126可增加凸塊140與電極120e之間的接合強度，進而提升晶片封裝結構100e的製造良率及電性品質。
在本實施例中，導電柱126是呈圓柱狀，然而，在其他未繪示的實施例中，導電柱亦可以呈正方形柱狀、長方形柱狀、橢圓柱狀、三角柱狀或其他幾何形狀的柱狀。
圖4A為本發明之又一實施例之晶片封裝結構的剖面示意圖，而圖4B為圖4A中之電極的上視示意圖。請參照圖4A與圖4B，本實施例之晶片封裝結構100f與上述晶片封裝結構100(如圖1A所繪示)類似，而兩者的差異如下所述。在晶片封裝結構100f中，電極120f之環狀元件124f包括一第一金屬環125a及一第二金屬環125b。第一金屬環125a配置於底部122上。第二金屬環125b配置於底部122上，並連接至第一金屬環125a的內側。
第二金屬環125b與底部122定義出容置凹陷R’。在本實施例中，第一金屬環125a的熱膨脹係數小於第二金屬環125b的熱膨脹係數。此外，在本實施例中，第一金屬環125a與第二金屬環125b的材質例如為形狀記憶合金。
當晶片封裝結構100f由製程溫度回覆至室溫的過程中，由於第一金屬環125a的熱膨脹係數小於第二金屬環125b的熱膨脹係數，因此第二金屬環125b收縮的程度會大於第一金屬環125a收縮的程度，這會導致環狀元件124f之遠離底部122的自由端朝向對應的凸塊140f彎曲，進而對凸塊140f施以夾持力。由於凸塊140f被環狀元件124f所夾持，因此凸塊140f與電極120f之間的接合可靠度便能夠有效提升，進而提升晶片封裝結構100f的製造良率及電性品質。
在本實施例中，環狀元件124f為圓形環狀元件，如圖4B所繪示。然而，在其他實施例中，環狀元件124f亦可以是正方形環狀元件(類似圖2A所繪示者)、長方形環狀元件(類似圖2B所繪示者)、橢圓形環狀元件(類似圖2C所繪示者、三角形環狀元件(類似圖2D所繪示者)或其他幾何形狀之環狀元件。此外，電極120f亦可包括如圖3A及圖3B所繪示之導電柱126，在此不再重述。
圖5A為本發明之再一實施例之晶片封裝結構在晶片與基板接合前的剖面示意圖，而圖5B為圖5A之晶片封裝結構在晶片與基板接合後的剖面示意圖。請參照圖5A及圖5B，本實施例之晶片封裝結構100g與上述晶片封裝結構100(如圖1A所繪示)類似，而兩者的差異如下所述。在晶片封裝結構100g中，封裝膠體150g對每一環狀元件124g之側壁施加壓力，以使環狀元件124g之遠離底部122的側壁自由端往對應的凸塊140g彎曲而夾持之，亦即使電極120g與凸塊140g產生物理接觸接合。
在本實施例中，晶片封裝結構100g的晶片封裝方法包括下列步驟。首先，請參照圖5A，提供上述基板110。接著，形成多個電極120g於基板110上，其中這些電極120g與圖1A所繪示的電極120相同。然後，填充一封裝膠體150g於基板110，封裝膠體150g包覆這些電極120g，且封裝膠體150g的平均液面高度低於每一電極120g的環狀元件124g之遠離底部122的自由端的高度。在本實施例中，封裝膠體150g在鄰接每一環狀元件124g之處的液面高度與環狀元件124g之遠離底部122的側壁自由端之高度實質上相等，且封裝膠體150g的液面高度由這些電極120往這些電極120之間的位置遞減。此外，提供上述晶片130。接著，形成多個上述接墊134於晶片130之主動表面132，晶片130的這些接墊134上分別配置有多個上述凸塊140g。
接著，使晶片130的主動表面132朝向基板110，並使這些凸塊140g分別置入這些容置凹陷R中，換言之，即是使晶片130與基板110壓合。此時，主動表面132會擠壓封裝膠體150g，以使封裝膠體150g對每一環狀元件124g施加壓力。環狀元件124g在受到壓力後會彎曲而成為圖5B之形狀，亦即封裝膠體150g對環狀元件124g所施加的壓力會使環狀元件124g之遠離底部122的自由端往對應的凸塊140g彎曲而夾持之。如此一來，凸塊140g與電極120g之間的接合可靠度便能夠有效提升，進而提升晶片封裝結構100g的製造良率及電性品質。之後，使封裝膠體150g固化，以完成晶片130之封裝。
圖6為本發明之另一實施例之晶片封裝結構的剖面示意圖。請參照圖6，本實施例之晶片封裝結構200的部分結構類似於圖1A所繪示之晶片封裝結構100，而兩者的差異如下所述。在晶片封裝結構200中，多個晶片封裝結構100h配置於一線路載板210上，而晶片封裝結構100h與圖1A之晶片封裝結構100之差異僅在於晶片封裝結構100h不包含晶片封裝結構100之封裝膠體150。在本實施例中，線路載板210例如是多層線路電路板。具體而言，晶片封裝結構100h之錫球190配置於線路載板210之電極212上，以使晶片封裝結構100h與線路載板210電性連接。晶片封裝結構100h更包括一封裝膠體220，其配置於基板110上，並包覆凸塊140與電極120。由於晶片封裝結構100h具有較佳的製造良率及較高的電性品質，因此晶片封裝結構200的製造良率及電性品質亦能夠被提升。
值得注意的是，晶片封裝結構200中之晶片封裝結構100h亦可以用上述其他實施例之晶片封裝結構(例如晶片封裝結構100e、100f、100g)取代，以形成不同之晶片封裝結構。
綜上所述，在本發明之實施例的晶片封裝結構中，由於凸塊是位於電極之環狀元件內，因此可藉由凸塊與環狀元件之熱膨脹係數之不同，而使環狀元件對凸塊施以夾持力。如此一來，便可提升電極與凸塊之間的接合可靠度，進而提升晶片封裝結構之製造良率及電性品質。
在本發明之實施例的晶片封裝結構中，由於構成環狀元件之第一金屬環與第二金屬環之熱膨脹係數不同，因此環狀元件之遠離基板的自由端在降溫後會朝向對應的凸塊彎曲，以夾持凸塊，如此便可提升電極與凸塊之間的接合可靠度。
在本發明之實施例的晶片封裝結構及晶片封裝方法中，由於封裝膠體對每一環狀元件施加壓力，以使環狀元件之遠離底部之自由端往對應的凸塊彎曲而夾持之，因此電極與凸塊之間的接合可靠度較高。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100e、100f、100g、100h、200．．．晶片封裝結構
110．．．基板
112．．．第一表面
114．．．第二表面
120、120e、120f、212．．．電極
122．．．底部
124、124a、124b、124c、124d、124f、124g．．．環狀元件
125a．．．第一金屬環
125b．．．第二金屬環
126．．．導電柱
130．．．晶片
132．．．主動表面
134、182．．．接墊
136．．．凸塊下金屬層
140、140g．．．凸塊
150、150g、220．．．封裝膠體
160．．．導電貫通孔道
170．．．第一圖案化導電層
180．．．第二圖案化導電層
190．．．錫球
210．．．線路載板
R、R’容置凹陷
圖1A為本發明之一實施例之晶片封裝結構的剖面示意圖。
圖1B為圖1A中之電極的上視示意圖。
圖2A、圖2B、圖2C及圖2D為另外四個實施例之電極的上視示意圖。
圖3A為本發明之另一實施例之晶片封裝結構的剖面示意圖。
圖3B為圖3A中之電極的上視示意圖。
圖4A為本發明之又一實施例之晶片封裝結構的剖面示意圖。
圖4B為圖4A中之電極的上視示意圖。
圖5A為本發明之再一實施例之晶片封裝結構的剖面示意圖。
圖5B為圖5A中之晶片與基板在接合前的剖面示意圖。
圖6為本發明之另一實施例之晶片封裝結構的剖面示意圖。
100．．．晶片封裝結構
110．．．基板
112．．．第一表面
114．．．第二表面
120．．．電極
122．．．底部
124．．．環狀元件
130．．．晶片
132．．．主動表面
134．．．接墊
136．．．凸塊下金屬層
140．．．凸塊
150．．．封裝膠體
160．．．導電貫通孔道
170．．．第一圖案化導電層
180．．．第二圖案化導電層
R．．．容置凹陷

Claims (43)

  1. 一種晶片封裝結構，包括：一基板；多個電極，其中每一該電極具有：一底部，配置於該基板上；以及一環狀元件，配置於該底部上，其中該底部與該環狀元件定義出一容置凹陷；一晶片，配置於該基板上方，並具有一面向該基板的主動表面及位於該主動表面上的多個第一接墊；以及多個凸塊，分別配置於該些第一接墊上，並分別嵌入該些容置凹陷中，其中該些凸塊直接接觸該些環狀元件，該些電極的熔點大於該些凸塊的熔點。
  2. 如申請專利範圍第1項所述之晶片封裝結構，其中該基板是線路載板。
  3. 如申請專利範圍第1項所述之晶片封裝結構，更包括多個凸塊下金屬層，分別連接該些凸塊和該些第一接墊。
  4. 如申請專利範圍第1項所述之晶片封裝結構，其中該凸塊與該主動表面平行的方向上之寬度等於該環狀元件之內徑。
  5. 如申請專利範圍第1項所述之晶片封裝結構，其中該些凸塊的熱膨脹係數大於該些電極的熱膨脹係數。
  6. 如申請專利範圍第1項所述之晶片封裝結構，其中該環狀元件為多邊形環狀元件、圓形環狀元件或橢圓形 環狀元件。
  7. 如申請專利範圍第1項所述之晶片封裝結構，其中每一該電極更包括一導電柱，配置於該底部上，並位於該容置凹陷中，且該導電柱與該環狀元件之間保持間隔。
  8. 如申請專利範圍第7項所述之晶片封裝結構，其中該導電柱呈一幾何形狀。
  9. 如申請專利範圍第1項所述之晶片封裝結構，更包括一封裝膠體，配置於該基板與該晶片之間，並包覆該些電極及該些凸塊。
  10. 如申請專利範圍第1項所述之晶片封裝結構，其中該基板具有相對之一第一表面及一第二表面，而該些電極是配置於該第一表面，該晶片封裝結構更具有多個導電貫通孔道，該些導電貫通孔道貫穿該基板，並由該第一表面延伸至該第二表面，且該些導電貫通孔道電性連接該些電極。
  11. 如申請專利範圍第10項所述之晶片封裝結構，更包括：一第一圖案化導電層，配置於該基板之該第一表面上，其中部分該第一圖案化導電層構成該些電極之該些底部，且該些導電貫通孔道與該第一圖案化導電層連接，以使該些導電貫通孔道與該些電極電性連接；一第二圖案化導電層，配置於該基板之該第二表面上，其中該第二圖案化導電層形成多個第二接墊，且該些第二接墊與該些導電貫通孔道電性連接；以及 多個錫球，分別配置於該些第二接墊上。
  12. 如申請專利範圍第1項所述之晶片封裝結構，其中該些凸塊分別與該些電極以化學鍵結接合。
  13. 如申請專利範圍第12項所述之晶片封裝結構，其中該些電極的材質包括銅及鎳至少其中之一，且該些凸塊的材質包括錫。
  14. 如申請專利範圍第1項所述之晶片封裝結構，其中該些凸塊分別與該些電極以物理接觸接合。
  15. 如申請專利範圍第14項所述之晶片封裝結構，其中該些電極的材質包括鉑、銅及鈦至少其中之一，且該些凸塊的材質包括金及鎳。
  16. 一種晶片封裝結構，包括：一基板；多個電極，其中每一該電極具有：一底部，配置於該基板上；以及一環狀元件，包括：一第一金屬環，配置於該底部上；以及一第二金屬環，配置於該底部上，並連接至該第一金屬環的內側，其中該第二金屬環與該底部定義出一容置凹陷；一晶片，配置於該基板上方，並具有一面向該基板的主動表面及位於該主動表面上的多個第一接墊；以及多個凸塊，分別配置於該些第一接墊上，並分別嵌入該些容置凹陷中，其中該些凸塊直接接觸該些環狀元件， 該些電極的熔點大於該些凸塊的熔點。
  17. 如申請專利範圍第16項所述之晶片封裝結構，其中每一該電極之該第一金屬環的熱膨脹係數小於該電極之該第二金屬環的熱膨脹係數。
  18. 如申請專利範圍第16項所述之晶片封裝結構，其中該第一金屬環與該第二金屬環的材質為形狀記憶合金。
  19. 如申請專利範圍第16項所述之晶片封裝結構，其中該基板是線路載板。
  20. 如申請專利範圍第16項所述之晶片封裝結構，更包括多個凸塊下金屬層，分別連接該些凸塊和該些第一接墊。
  21. 如申請專利範圍第16項所述之晶片封裝結構，其中該凸塊與該主動表面平行的方向上之寬度等於該環狀元件之內徑。
  22. 如申請專利範圍第16項所述之晶片封裝結構，其中該環狀元件為多邊形環狀元件、圓形環狀元件或橢圓形環狀元件。
  23. 如申請專利範圍第16項所述之晶片封裝結構，其中每一該電極更包括一導電柱，配置於該底部上，並位於該容置凹陷中，且該導電柱與該環狀元件之間保持間隔。
  24. 如申請專利範圍第23項所述之晶片封裝結構，其中該導電柱呈一幾何形狀。
  25. 如申請專利範圍第16項所述之晶片封裝結構，更包括一封裝膠體，配置於該基板與該晶片之間，並包覆該 些電極及該些凸塊。
  26. 如申請專利範圍第16項所述之晶片封裝結構，其中該基板具有相對之一第一表面及一第二表面，而該些電極是配置於該第一表面，該晶片封裝結構更具有多個導電貫通孔道，該些導電貫通孔道貫穿該基板，並由該第一表面延伸至該第二表面，且該些導電貫通孔道電性連接該些電極。
  27. 如申請專利範圍第26項所述之晶片封裝結構，更包括：一第一圖案化導電層，配置於該基板之該第一表面上，其中部分該第一圖案化導電層構成該些電極之該些底部，且該些導電貫通孔道與該第一圖案化導電層連接，以使該些導電貫通孔道與該些電極電性連接；一第二圖案化導電層，配置於該基板之該第二表面上，其中該第二圖案化導電層形成多個第二接墊，且該些第二接墊與該些導電貫通孔道電性連接；以及多個錫球，分別配置於該些第二接墊上。
  28. 如申請專利範圍第16項所述之晶片封裝結構，其中該些凸塊分別與該些電極以化學鍵結接合。
  29. 如申請專利範圍第28項所述之晶片封裝結構，其中該些電極的材質包括銅及鎳至少其中之一，且該些凸塊的材質包括錫。
  30. 如申請專利範圍第16項所述之晶片封裝結構，其中該些凸塊分別與該些電極以物理接觸接合。
  31. 如申請專利範圍第30項所述之晶片封裝結構，其中該些電極的材質包括鉑、銅及鈦至少其中之一，且該些凸塊的材質包括金及鎳。
  32. 一種晶片封裝結構，包括：一基板；多個電極，其中每一該電極具有：一底部，配置於該基板上；以及一環狀元件，配置於該底部上，其中該底部與該環狀元件定義出一容置凹陷；一晶片，配置於該基板上方，並具有一面向該基板的主動表面及位於該主動表面上的多個第一接墊；多個凸塊，分別配置於該些第一接墊上，並分別嵌入該些容置凹陷中，其中該些凸塊直接接觸該些環狀元件；以及一封裝膠體，配置於該基板與該晶片之間，並包覆該些電極及該些凸塊，其中該封裝膠體對每一該環狀元件施加壓力，以使該環狀元件之遠離該底部的自由端往該對應的凸塊彎曲而夾持之。
  33. 如申請專利範圍第32項所述之晶片封裝結構，其中該基板是線路載板。
  34. 如申請專利範圍第32項所述之晶片封裝結構，更包括多個凸塊下金屬層，分別連接該些凸塊和該些第一接墊。
  35. 如申請專利範圍第32項所述之晶片封裝結構，其 中該凸塊與該主動表面平行的方向上之寬度等於該環狀元件之內徑。
  36. 如申請專利範圍第32項所述之晶片封裝結構，其中該環狀元件為多邊形環狀元件、圓形環狀元件或橢圓形環狀元件。
  37. 如申請專利範圍第32項所述之晶片封裝結構，其中該基板具有相對之一第一表面及一第二表面，而該些電極是配置於該第一表面，該晶片封裝結構更具有多個導電貫通孔道，該些導電貫通孔道貫穿該基板，並由該第一表面延伸至該第二表面，且該些導電貫通孔道電性連接該些電極。
  38. 如申請專利範圍第37項所述之晶片封裝結構，更包括：一第一圖案化導電層，配置於該基板之該第一表面上，其中部分該第一圖案化導電層構成該些電極之該些底部，且該些導電貫通孔道與該第一圖案化導電層連接，以使該些導電貫通孔道與該些電極電性連接；一第二圖案化導電層，配置於該基板之該第二表面上，其中該第二圖案化導電層形成多個第二接墊，且該些第二接墊與該些導電貫通孔道電性連接；以及多個錫球，分別配置於該些第二接墊上。
  39. 如申請專利範圍第32項所述之晶片封裝結構，其中該些凸塊分別與該些電極以物理接觸接合。
  40. 如申請專利範圍第39項所述之晶片封裝結構，其 中該些電極的材質包括鉑、銅及鈦至少其中之一，且該些凸塊的材質包括金及鎳。
  41. 一種晶片封裝方法，包括：提供一基板；形成多個電極於該基板上，其中每一該電極具有一底部及一環狀元件，該底部位於該基板上，該環狀元件配置於該底部上，且該底部與該環狀元件定義出一容置凹陷；充填一封裝膠體於該基板，該封裝膠體包覆該些電極，且該封裝膠體的平均液面高度低於每一電極的環狀元件之自由端的高度；提供一晶片；形成多個接墊於該晶片之主動表面，該些接墊上分別配置有多個凸塊；以及使該晶片的該主動表面朝向該基板，並使該些凸塊分別置入該些容置凹陷中而直接接觸該些環狀元件，其中該主動表面會擠壓該封裝膠體，以使該封裝膠體對每一該環狀元件施加壓力，進而使該環狀元件之該自由端往該對應的凸塊彎曲而夾持之。
  42. 如申請專利範圍第41項所述之晶片封裝方法，其中當在基板上形成該封裝膠體時，該封裝膠體在鄰接每一該環狀元件之處的液面高度與該環狀元件之該自由端之高度實質上相等，且該封裝膠體的液面高度由該些電極往該些電極之間的位置遞減。
  43. 如申請專利範圍第41項所述之晶片封裝方法，在 使該些凸塊分別置入該些容置凹陷之後，更包括使該封裝膠體固化。
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