TWI571985B - 扇出晶圓級封裝及其製作方法 - Google Patents

扇出晶圓級封裝及其製作方法 Download PDF

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TWI571985B
TWI571985B TW105104397A TW105104397A TWI571985B TW I571985 B TWI571985 B TW I571985B TW 105104397 A TW105104397 A TW 105104397A TW 105104397 A TW105104397 A TW 105104397A TW I571985 B TWI571985 B TW I571985B
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layer
passivation layer
fan
wafer level
out wafer
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TW105104397A
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TW201725670A (zh
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羅翊仁
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華亞科技股份有限公司
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Description

扇出晶圓級封裝及其製作方法
本發明概括而言係關於半導體封裝領域，特別是關於一種扇出晶圓級封裝（fan-out wafer level packaging，FOWLP）及其製作方法。
隨著半導體製造技術的進步，微電子元件的尺寸變得更小，元件中的電路也變得更密集。為了得到更小尺寸的微電子元件，其封裝與安裝至電路板上的結構都必須變得更緊密。
半導體封裝領域中所熟知的嵌入晶圓球柵陣列（embedded wafer ball grid array, eWLB）或扇出晶圓級封裝(FOWLP)，是藉由位於基底上的重佈線層(RDL)，例如位於具有穿矽通孔(TSV)的基底，將原本半導體晶粒的接墊重新佈線分配至一較大的區域。
重佈線層是在晶圓表面上形成介電層與金屬導線的疊層，將晶片原本的輸入/輸出(I/O)接墊重新佈線分配至一個間距較寬鬆的佈局範圍。上述重佈線的製作通常使用薄膜高分子聚合物，例如苯併環丁烯（benzocyclobutene, BCB）、聚亞醯胺(polyimide, PI)，或其他有機高分子聚合物作為介電層材料，再以金屬化製程，例如鋁或銅，形成金屬導線，將晶片周圍的接墊重新佈線分配成陣列狀連接墊。
由於製程繁複，具有穿矽通孔的中介層基底成本較高，因此，使用具有穿矽通孔中介層的扇出晶圓級封裝也會比較昂貴，並不利於特定的應用場合。
此外，晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數（CTE）差異，容易導致封裝翹曲變形，也使得封裝整體的厚度增加。晶圓翹曲一直是該領域關注的問題。
晶圓翹曲使晶片與晶圓間的接合不易維持，使“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製，問題更為嚴重。因此，業界仍需要一個改良的晶圓級封裝方法，可以解決上述先前技術的問題。
本發明的主要目的在提供一種改良的半導體裝置及其製作方法，以解決先前技藝的不足與缺點。
根據本發明一實施例，提供一種扇出晶圓級封裝，包含有一重佈線層，包含至少一介電層以及至少一第一金屬層；一被動元件，設於該重佈線層的該第一金屬層中；一第一鈍化層，覆蓋該重佈線層的一上表面；一第二鈍化層覆蓋該重佈線層的一下表面；至少一晶粒安置在該第一鈍化層上，其中該晶粒包含一接點，直接接觸該第一鈍化層；一成型模料，設於該晶粒周圍以及該第一鈍化層上；一導孔，貫穿該第一鈍化層、該介電層以及該第二鈍化層，以顯露出該接點；一接觸洞，設於該第二鈍化層中，顯露出該被動元件的一電極；以及一第二金屬層，設於該導孔以及該接觸洞中，以電連接該被動元件的該電極至該晶粒的該接點。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。
下面的描述須參照相關附圖以便徹底理解本發明，其中相同或類似的特徵通常以相同的附圖標記描述，而且描述的結構並不必然按比例繪製。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”等詞具有相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層(RDL)。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖，其為依據本發明一實施例所繪示的扇出晶圓級封裝（fan-out wafer level packaging，FOWLP）的剖面示意圖。如第1圖所示，扇出晶圓級封裝1包含一重佈線層（redistribution layer, RDL）410。重佈線層410包含至少一介電層412以及至少一金屬層（第一金屬層）414。介電層412可以包含無機材料，例如，氮化矽、氧化矽等，但不限於此。金屬層414可以包含鋁、銅、鎢、鈦、氮化鈦等。需理解的是，金屬層414可以包含多層的金屬繞線，且介電層412可以包含多層的介電堆疊結構。
根據本發明一實施例，扇出晶圓級封裝1可以另包含至少一被動元件700，例如，金屬-絕緣-金屬（metal-insulator-metal, MIM）電容，其製作於重佈線層410中。根據本發明一實施例，被動元件700係嵌入埋設在介電層412中。
根據本發明一實施例，一鈍化層413（或一黏著層）係層疊在重佈線層410的上表面。鈍化層413係直接接觸到重佈線層410的介電層412，並且覆蓋部分的金屬層414。例如，鈍化層413可以包含聚合物，例如，苯併環丁烯（benzocyclobutene, BCB），但不限於此。根據本發明一實施例，在安置貼合晶片之後，可以對鈍化層413進行一固化製程。含有如苯併環丁烯等聚合物的鈍化層413可以被部分固化，例如，60%至80%的固化程度。
扇出晶圓級封裝1另包含個別的覆晶晶片或晶粒420a及420b，其主動面朝下面對著重佈線層410。所述晶粒420a及420b係被安置貼合在鈍化層413上。所述晶粒420a及420b包含接點421，其包括，但不限於，設在輸出/輸入（input/output, I/O）墊上的金屬凸塊。這些輸出/輸入墊係分佈在所述晶粒420a及420b的主動面上。為簡化說明，在各個晶粒420a及420b上僅繪示出一個接點421。
另外，可選擇在各個晶粒420a及420b下方形成一層間介電層512。所述層間介電層512可以形成在各個晶粒420a及420b與鈍化層413之間，並且圍繞接點421。
根據本發明一實施例，另包含一成型模料500，其包覆晶粒420a及420b以及鈍化層413的上表面。可以對所述成型模料500進行一固化製程。所述成型模料500可以包含環氧樹脂以及矽土填料，但不限於此。
根據本發明一實施例，在重佈線層410的一底表面上層疊有一鈍化層310。所述鈍化層310係直接接觸到重佈線層410的介電層412，並且覆蓋部分的金屬層414。所述鈍化層310可以包含有機材料，例如，聚醯亞胺（polyimide, PI），或者無機材料，例如，氮化矽、氧化矽等。根據本發明一實施例，重佈線層410、鈍化層（第一鈍化層）310及鈍化層（第二鈍化層）413構成一中介層（或一中介層基板）400。
根據本發明一實施例，扇出晶圓級封裝1另包含貫通中介層導孔（through-interposer-vias）480，設於鈍化層310、介電層412及鈍化層413中。所述貫通中介層導孔480貫穿中介層400的整個厚度，包括鈍化層310、介電層412及鈍化層413。所述貫通中介層導孔480係分別對準接點421。
根據本發明一實施例，所述貫通中介層導孔480係透過金屬層（第二金屬層）482金屬化。例如，所述金屬層482可以是一銅層，其可以利用電鍍製程或濺鍍製程形成，但不限於此。所述金屬層482可以是共形的沉積在貫通中介層導孔480的內壁上，且可以包含一焊接墊482a在鈍化層310上。
根據本發明一實施例，在鈍化層310中可以形成一接觸洞310a，顯露出被動元件700的一電極702。金屬層482可以填入接觸洞310a中，以電連接被動元件700的電極702。在金屬層482的焊接墊482a上可以形成有錫球520，以供進一步連結到，例如，一主機板或一電路板。金屬層482及414，以及金屬化的貫通中介層導孔480，共同構成晶粒420a及晶粒420b之間的晶片內連結。
值得注意的是，根據本發明一實施例，在重佈線層410上不需要形成任何的微凸塊（micro-bumps）。換言之，晶粒420a及420b並不是透過微凸塊電連結至重佈線層410。根據本發明一實施例，晶粒420a及420b係透過金屬化的貫通中介層導孔480以及金屬層482電連結至重佈線層410及/或被動元件700。藉由去除微凸塊，扇出晶圓級封裝的整體厚度可以被降低。
請參閱第2圖至第9圖，其為依據本發明一實施例所繪示的製作晶圓級封裝的方法示意圖。
如第2圖所示，首先提供一載板300，其中載板300可以是一晶圓或一基板材料，其上具有一黏著層（圖未明示），但不限於此。例如，載板300可以包含一玻璃基板或一矽基板。接著，於載板300的一上表面形成至少一介電層或一鈍化層310。所述鈍化層310可以包含有機材料，例如，聚醯亞胺，或者無機材料，例如，氮化矽、氧化矽等。
接著，在鈍化層310上形成一重佈線層410。所述重佈線層410可以包含至少一介電層412以及至少一金屬層414。介電層412可以包含無機材料，例如，氮化矽、氧化矽等，但不限於此。
金屬層414可以包含鋁、銅、鎢、鈦、氮化鈦等。重佈線層410中包含至少一被動元件700，例如，金屬-絕緣-金屬（metal-insulator-metal, MIM）電容，其嵌入埋設在介電層412中。
根據本發明一實施例，一鈍化層413（或一黏著層）係層疊在重佈線層410的上表面。鈍化層413係直接接觸到重佈線層410的介電層412，並且覆蓋部分的金屬層414。例如，鈍化層413可以包含聚合物，例如，苯併環丁烯（benzocyclobutene, BCB），但不限於此。根據本發明一實施例，在安置貼合晶片之後，可以對鈍化層413進行一固化製程。含有如苯併環丁烯等聚合物的鈍化層413可以被部分固化，例如，60%至80%的固化程度。重佈線層410、鈍化層310及413構成一中介層（或一中介層基板）400。
如第3圖所示，接著，將個別的覆晶晶片或晶粒420a及420b，使其主動面朝下面對著重佈線層410，安置貼合在鈍化層413上，如此構成一晶片對晶圓堆疊（chip-to-wafer, C2W）結構。所述晶粒420a及420b包含接點421，其包括，但不限於，設在輸出/輸入墊上的金屬凸塊。這些輸出/輸入墊係分佈在所述晶粒420a及420b的主動面上。
為簡化說明，在各個晶粒420a及420b上僅繪示出一個接點421。此時，接點421係直接接觸到鈍化層413，且被鈍化層413所覆蓋。
另外，可選擇在各個晶粒420a及420b下方形成一層間介電層512。所述層間介電層512可以形成在各個晶粒420a及420b與鈍化層413之間，並且圍繞接點421。
如第4圖所示，在貼合晶片之後，可以形成一成型模料500。成型模料500包覆晶粒420a及420b以及鈍化層413的上表面。可以對所述成型模料500進行一固化製程。所述成型模料500可以包含環氧樹脂以及矽土填料，但不限於此。此外，可選擇對成型模料500的上表面進行一研磨製程，以去除部分的成型模料500。
此時，根據本發明一實施例，晶粒420a及420b的上表面係與成型模料500的上表面齊平。根據本發明一實施例，在上述研磨製程中，晶粒420a及420b的一上部可以選擇被研磨掉。
如第5圖所示，接著可以進行另一研磨製程，例如，化學機械研磨（chemical mechanical polishing, CMP）製程，以研磨掉載板300，直到鈍化層310被顯露出來。需理解的是，去除載板300的方法不限於研磨方式，也可以使用其它方法。
如第6圖所示，接著在鈍化層310上形成一光阻圖案600。光阻圖案600包含一第一開口602，其定義出後續將形成於中介層400內的一貫通中介層導孔的圖案及位置，以及一第二開口604，其定義出後續用以顯露出被動元件700的電極的一接觸洞的圖案及位置。
如第7圖所示，進行一非等向性乾蝕刻製程，經由該第一開口602及該第二開口604蝕刻該中介層400，在鈍化層310、介電層412及鈍化層413中形成至少一貫通中介層導孔480，以及在鈍化層310中形成一接觸洞310a。所述貫通中介層導孔480貫穿中介層400的整個厚度，包括鈍化層310、介電層412及鈍化層413。所述貫通中介層導孔480係分別對準接點421並且顯露出部分的接點421。接觸洞310a顯露出被動元件700的部分的電極702。
根據本發明一實施例，上述製程步驟可以被稱為「導孔後製（via-last）」製程，因為所述貫通中介層導孔480係在中介層400形成後、晶粒或晶片安置貼合製程、以及成型製程後，始開始製作。
如第8圖所示，進行一電鍍製程，例如，一濺射電鍍（sputter plating）製程，將貫通中介層導孔480以及接觸洞310a金屬化。在上述電鍍製程中，金屬層482，例如，銅層，被共形的沉積到貫通中介層導孔480的內壁上，並且可以填滿接觸洞310a，如此使接點421電連接至被動元件700的電極702。金屬層482可以包含一焊接墊482a，設於鈍化層310上。
如第9圖所示，在金屬層482的焊接墊482a上形成錫球520，以供進一步連結到，例如，一主機板或一電路板。金屬層482及414，以及金屬化的貫通中介層導孔480，共同構成晶粒420a及晶粒420b之間的晶片內連結。最後，圖中的晶圓級封裝再被切割形成個別的晶片封裝。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧扇出晶圓級封裝
300‧‧‧載板
310‧‧‧鈍化層
310a‧‧‧接觸洞
400‧‧‧中介層
410‧‧‧重佈線層
412‧‧‧介電層
413‧‧‧鈍化層
414‧‧‧金屬層
420a、420b‧‧‧晶粒
421‧‧‧接點
480‧‧‧貫通中介層導孔
482‧‧‧金屬層
482a‧‧‧焊接墊
500‧‧‧成型模料
520‧‧‧錫球
512‧‧‧層間介電層
600‧‧‧光阻圖案
602‧‧‧第一開口
604‧‧‧第二開口
700‧‧‧被動元件
702‧‧‧電極
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。   第1圖為依據本發明一實施例所繪示的扇出晶圓級封裝的剖面示意圖。   第2圖至第9圖為依據本發明一實施例所繪示的製作第1圖中扇出晶圓級封裝的方法示意圖。
1‧‧‧扇出晶圓級封裝
310‧‧‧鈍化層
310a‧‧‧接觸洞
400‧‧‧中介層
410‧‧‧重佈線層
412‧‧‧介電層
413‧‧‧鈍化層
414‧‧‧金屬層
420a、420b‧‧‧晶粒
421‧‧‧接點
480‧‧‧貫通中介層導孔
482‧‧‧金屬層
482a‧‧‧焊接墊
500‧‧‧成型模料
520‧‧‧錫球
512‧‧‧層間介電層
700‧‧‧被動元件
702‧‧‧電極

Claims (11)

  1. 一種扇出晶圓級封裝，包含有： 一重佈線層，包含至少一介電層以及至少一第一金屬層； 一被動元件，設於該重佈線層的該第一金屬層中； 一第一鈍化層，覆蓋該重佈線層的一上表面； 一第二鈍化層覆蓋該重佈線層的一下表面； 至少一晶粒安置在該第一鈍化層上，其中該晶粒包含一接點，直接接觸該第一鈍化層； 一成型模料，設於該晶粒周圍以及該第一鈍化層上； 一導孔，貫穿該第一鈍化層、該介電層以及該第二鈍化層，以顯露出該接點； 一接觸洞，設於該第二鈍化層中，顯露出該被動元件的一電極；以及 一第二金屬層，設於該導孔以及該接觸洞中，以電連接該被動元件的該電極至該晶粒的該接點。
  2. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該介電層包含無機材料。
  3. 如申請專利範圍第2項所述的扇出晶圓級封裝，其中該無機材料包含氮化矽或氧化矽。
  4. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該被動元件包含一金屬-絕緣-金屬電容。
  5. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該第一鈍化層包含苯併環丁烯。
  6. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該第一金屬層包含鋁、銅、鎢、鈦或氮化鈦。
  7. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該第二金屬層包含銅。
  8. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該第二金屬層另包含一焊接墊，設於該第二鈍化層上。
  9. 如申請專利範圍第8項所述的扇出晶圓級封裝，其中另包含一錫球，設於該焊接墊上。
  10. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該接點包含設在該晶粒的主動面上的一輸出/輸入墊以及設於該輸出/輸入墊上的一金屬凸塊。
  11. 如申請專利範圍第1項所述的扇出晶圓級封裝，其中該重佈線層、該第一鈍化層及該第二鈍化層構成一中介層。
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