TW200921889A - Package on package structure for semiconductor devices and method of the same - Google Patents

Package on package structure for semiconductor devices and method of the same Download PDF

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Publication number
TW200921889A
TW200921889A TW097141429A TW97141429A TW200921889A TW 200921889 A TW200921889 A TW 200921889A TW 097141429 A TW097141429 A TW 097141429A TW 97141429 A TW97141429 A TW 97141429A TW 200921889 A TW200921889 A TW 200921889A
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TW
Taiwan
Prior art keywords
layer
package
substrate
die
level
Prior art date
Application number
TW097141429A
Other languages
Chinese (zh)
Inventor
Wen-Kun Yang
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from US11/933,703 external-priority patent/US20080157327A1/en
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200921889A publication Critical patent/TW200921889A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package on package structure for semiconductor devices comprises at least one first level package having at least first level semiconductor die therein, wherein the package having first level contact pads formed on a first upper and lower surfaces of the first level package, the first level package having a first level upper build up layers and/or a first level lower build up layer to couple to bonding pads of the first level semiconductor die to contact first level pads on the both upper and lower surfaces of the first level package; a second level package having at least one second semiconductor die contained therein, wherein the second level package has a second level contact pads on a second upper and lower surfaces of the second level package, and conductive connecting through holes; wherein the second level package have a second level upper build up layer and/or second level lower build up layer to couple second level bonding pads of the second semiconductor die to contact second level pads and the conductive connecting through holes on the upper and lower surface of the second level package, conductive through holes being coupled to the first level pads of upper and lower surfaces of the first level package and the second level pads of upper and lower surface of the second level package; and adhesion materials attached on lower surface of the first level package and the upper surface of the second level package.

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200921889 六、發明說明： 【發明所屬之技術領域】 元件屬於一種半導體封裝，特別是關於-種半導體 π件之層疊封裝結構。 干導體 【先前技術】 3電路⑽晶粒或^是自半導體㈣（ 、切下的小型、約呈長方形的IC元件。一般而…圓) 被包覆在晶粒封裝結構中 。，稞晶會 杜嫌保4匕們不被腐蝕。這類钮酤 、二β效保護1C晶粒，但對於某些小型的 封裝： 用而言，抖驻4士 4技u a粒封裝應 與電性对^ 期的更佔空間。增加元件的熱發散 一 >此以及減少體積與製造成本等工業需求為曰二 ==封力裝1業發展的原因。在半導體領域中’騎的= 互連二:：尺寸不斷縮小，故對於高密度元件的封裝與 迷技術（uuerconnect)需求亦不斷增加以因庫 =接材料可形成辉錫凸塊⑽derb— ^曰曰技術（fhP-chip)可將晶粒電性連接至黏合基底處，如 丄電路板。晶粒封裝的功能包含了電能分佈、訊號分佈、 ‘:考散、提供保護與支撐等等。當半導體元件變得越來越 稷漳，傳統的封褒技術，例如導線架封裝〇ead加邮 PaCkage)、軟質封裝（flexible package)、硬質封裝（rigid Package)技術等已不能滿足高元件密度小型晶片之製作需 '' 叙而5 ’如球閘陣列（BGA，Gall Grid Array)式的陣 封震結構能在封裴表面區域提供高密度的互連配置。一般 的球閘陣列封裝具有迂迴的訊號路徑，會使阻抗升高，且 200921889 因其熱傳導不善而使散熱機制變差 加，分散封裝結構内元件所產 ^者封裝密度的增 為了滿足新世代電子產品 中:月匕就變得格外重要。 力投注在開發可靠、符成本效研究人員將許多心 封裝結構上。舉例而言，1 ::尘化、以及高效能的 之訊號延遲、全體封裝構件所佔少】：訊號傳輸時 出入接墊⑽)配置。 ^域、及更具彈性的輸 Γ: 近年來，積體電路# 積體電路的發展瓶頸，微型化盘T；:斬成為一 」，、 夕日曰片拉組（multi-chir^ module,MCM)之封裝結構已普遍使用於與電子裝置中。^ ^片模組封裝主要包含了兩顆以上的晶、 升封裝的電性與效能。 伋以美 :國專：第__公㈣揭露了一種多晶粒封 f 如圖六所示。在半導體元件中，通孔㈣通常會 在封褒所埋的晶粒四周形成。通孔内會填入導體材質，且 其-端為棵露在外的接墊部位所覆蓋’另—端則盘佈線層 (Μ 一〇連接。該導線層對應導體材質之部位（即^ 部位）會自保護層中裸露出來’或—外部連接端會與該接塾 部位焊接。晶粒的電極端會與該導線層連接，而另一面則 會裸露在外。半導體元件傷（圖六）係為—堆疊結構:其: 別的晶粒結構106疊為三層以分別模組化。每個半導體元 件406巾，兩垂直相鄰的晶粒結構1〇6會藉由其頂部盘底 部的接墊236來與外部的連接端（如銲錫凸塊266)相連 結，並使用底部填充（underfill)樹脂416填入兩元件間的空 200921889 隙。再者’封裝結構 與246會分別從封裝的兩面;露;來4封;236 防，㈣蓋在導_ 料，會使並==計中含有太多堆叠的介電層與密封材 介電層不具:二差非 的問題;再者，部分結構:欠二;=脹係數不合 其钟蚪认偁^人缺了可釋放應力之緩衝層， 、叹° ; ί裝結構的熱循環與運作期間並不可靠。 題，本發明提出了—種疊層封裝結構以克服上述問 碭，且具有更佳的元件效能。 【發明内容】 元件提供—具有晶粒與導電佈線之半導體 靠度之2^。裝）’可降低成本，並提供高效能及高可 姓構(tfk明之另一目的為提出一種半導體元件之疊層封裳 、、口 構（Package on package，p〇p)。 ^發明之又—目的為提出—種方便、符成本效 導體疊層封裝結構之製造方法。 牛 在本發明的觀點中，半導體元件之叠層封裝結構包含 =第-層封裝，其内具有一個以上的第一層半導體晶 w第-層封裝的上表面與下表面上有第—層接墊形成。 ^弟一層封裝還具有一第一層上增層與/或一第一層下辦 層輕口至其第-層半導體晶粒之鮮墊以連接第一層封裳上 下表面的第一層接墊；第二層封裝内具有至少一個第二半 200921889 導體晶粒，且其上表面與下表面上有第二層接塾以及導電 連接通孔；其中第二層封裂具有一第二層上增層與/或第二 層下增層轉合第二半導體晶粒之第二層銲塾以連接第二廣 封裝上下表面的第二層接塾與導電連結通孔。導電通孔: 耦合至第-層封裝上下表面的第—層接塾及第二層封裝上 下表面的第二層接墊；而黏著材料係黏附在第一層封裝的 下表面及第二層封裝的上表面上。 其第-半導體封裝與第二半導體封震的尺寸相同，而 错!一半導體晶粒的尺寸較第二半導體晶粒為大。封裝结 構中更包含一隔離底座形成在該第一層封裝上 以環氧樹脂（epoxy)、FR4/FR5 Λ低厓係 ㈣細机ΡΙ)或雙馬來5亞H乳基板雜聚醯亞胺 (B職aleimide Triazine, —亂=本樹脂 維。/ )寺材貝形成，且内摻玻璃纖 :層封裝的下方形成。錫球/錫塊的 目較= ί物。第二層封裝上導電連接通孔之數 ::被動元件。第-層與第二層的上下增層中包二； l V線核心膠形成在該第一半導體a 4盥笛_ 粒旁邊，而假銲錫球/錫換Μ ”第—半V體晶 衣賜龙（dummy bump)係供作播只士 p 以避免受到外力損壞。 P)料、作機械支撐 =1二述之形式、目的、觀點、特徵及優點將隨著 Μ下卓父佳實施例中 w丨逍有 顯，其細節描述與圖式僅伴；1之圖式而愈見明 轉將由隨附之專利請求項來定義。纟明。而本發明之範 200921889 【實施方式】 此處本發明將針對發明具體實施例及其觀 描述，此類描述為解釋本發明之結構或步驟流程， 二之用而非予以本發明申請專利範圍限制之實二 i ㈣書+之具體實施例與較佳實施例外 可廣泛施行於其他不同的實施例中。 *月亦 了-導體元件之多層封裝結構其提出 結構，如圖-〜圖五所干細士 —線及金屬互連 " 所不。發明中每-獨立封裝大部分的 行描^ 構皆相同。實施例會使用最上層的封裝來進 植每個獨立封裝都包含一晶粒211，其為核心膠材4所圍 =，二t有互連通孔18結構穿過核心膠材4。晶粒2n盘 H㈣4的側壁間會形成周圍材料8。互連通孔18會藉 佈層⑽1StdbutiGn layer，舰)㈣合至晶粒〜的^ 。上增層（bUlld_up layer，舰）】2係形成於晶粒^、核 =:4及重佈層1〇的上方。下增層2。亦同 ‘ 表面上。黏者材料16係塗佈於晶粒2n下方及上增声Μ 献^提供黏著效果。可使用具有彈性的黏著材料以吸收 / %所產生之應力。數個接塾32形成在下增層下方 :::互連通孔18位置對齊。接墊32可為銅/鎳/金或盆 質。所堆疊的增層係形成於晶粒^與核心膠材4 膠材4係形成於晶粒h旁以提供黏著與保護 文果。重佈層10則形成在上增層12内部。 200921889 黏著材料16上方有形成一隔離底座14，該 Μ係黏附在上增们2上。舉例而言，隔離底座= =成一、Μ、，脂等材質’其内部還有破； 義維形成。在一實施例中，隔離底座14包含了黏著層16 :成在下表面。重佈層10係以電鍍或蝕刻方法形成。；(與 〆鎳）之電鍍步驟會一直持續到銅鍍層達到理想的厚戶、 ，會延伸出區域外以容納晶粒，即所謂的擴散式； (n_〇Ut)。核心膠材4包覆著晶粒2η。其可以樹脂、化人 物、矽膠、FR5、ΒΤ或環氧樹脂形成。 下層封裝與上層封裝類似，但下層封裝 底座Η。且其上增層12上有接㈣形成。第= 二焊接金屬互連24結構或是導電連接通孔耦合 至第（η-1)層的上接塾。 本實知例中至少含有三排的接塾/坪接金屬互士 構。墊與塾之間的夾層結構可作為機械支8 裝層間所產生之扣隙 町相鄰封 ^生H6可予以封裝結構較佳的散熱性。此 外’母層晶粒與其他層封裝之晶粒可為不同的類型，例如 閃刪、被動元件等晶粒類型。底層的封裝 、口冓更匕3 了產干錫凸塊3〇耦合至下接墊％。 構外圖本發明之另一實施例。除了其上層封裝結 :外，：广的結構皆與上述實施例中相似。請參照 :::裝在隔離底座14内更含有一通孔結構 被動7G件40。 此外’於圖三的實施例中，隔離底座則是被移除。對 200921889 於層疊晶粒結構而t，甘么π β -其愈下層晶粒之尺寸就愈小，如圖 一中晶粒2η與晶粒2夕兰μ η 之差別。日日粒愈小，其核心膠材所佔 勺工間就愈大。此種架構下的底層封裝核心膠區域會較其 ^類型之封|⑦計架構為大，故可加強整 械支擇以承載其上層的封裝。 稱之機 2四說明了本發明之另一實施例，與第二實施例類 '。為了形成一穿過封裝中各層的通孔18b(如第-層互連 通孔），被動元件40須形成於黏著材料16a上方，而非原 本圖—中之位置。導電材料18d會塗佈在通孔娜表面，' 、真充材料18c會填回通孔18b巾，較之通孔⑽， 通孔18a則為單層的通孔結構。 、a圖五a至圖五c表示了本發明上層、中間層與下層之 封波結構。上層封|僅含單面的增層，而巾間層與下層封 裝則兩面皆有增層結構。 9 層疊封裝係為一種堆疊式結構設計。其各層級封裝板 之堆疊流程係使用焊接方式將各金屬1連結構連接，或是 _出通孔再$成導電互連結構。每層封裝板都可進行封裝 =的最終測言式（final testing)，且擴散式結構伽_〇叫之封 破製程可用在每層封裝板上。其封裝中亦提供可修復式結 ^係藉由解銲步驟（de_soldering)來修復。在本發明封裝 結構中’其被動元件係以表面黏著技術（8犯&“瓜⑽价丨％ technology，SMT)堆疊在頂面上。此外于本發明而言，並排 式封震與堆疊式封裝結構並行之設計亦是可能的。由於本 發明每一封裝與印刷電路板有相同的熱膨脹係數（使用相 200921889 =的核心膠材-BT或FR5)，故可獲得更佳的封裝測試可 罪度。 本發明還提出一種形成半導體晶粒封裝互連結構之方 法’其包含下列步驟： 準備一第一層基底（基底的材料以Βτ或FR5為佳）， 該基底具有第一層晶粒容納通孔與第一層導電連接通孔； 々將黏著材料黏附在該第一晶粒四周與底部並將至少— 個第一晶粒嵌入該第一層基底之晶粒容納通孔中； ，、在該第一晶粒與第一層基底的上表面與/或下表面上 形成第一層增層，透過該第一層導電連接通孔將該第—晶 粒之第一層銲墊與第一層增層之第一焊接金屬墊耦合； ^ ★準備一第二層基底（基底之材質以BT或FR5為佳）， 。亥第一層基底具有一第二層晶粒容納通孔與第二層導電連 將黏著材料黏附在該第 晶粒四周與底部並將 第一曰曰粒肷入該第二層基底之晶粒容納通孔中； 形成Π 一晶粒與第二層基底的上表面與/或下表面上 二層增層’透過該第二層導電連接通孔 拉之第^層料與第二層增層之第二焊接金屬_合:曰曰 亦可在封裝上表面的第二焊接金屬墊上印上錫膏； 在其上形成=2表㈣第—焊接金4墊上印上”以 的下:=::i:(;Tntingsy，將該第-層封裝 11 200921889 對錫贫施以迴銲（re_flow)形成互連結構。 务月方法更包括了沿切割道（scribe Hne)切割面板 之步驟卩⑯®層封裝（PoP)分離並以銅羯基板（laminated PPer f01i)、金屬濺鍍、銅/鎳/金電鍍之方式在第一層與 第一層封装上形成重佈層（位於增層内）。 .本么明另一方法亦包含形成疊層封裝互連結構之步 :·將封襞板形式的第一層封裝與第二層封裝對準並以黏 :材料黏結堆疊；更包含以機械鑽孔的方式形成互連通孔 構，邊互連通孔係自第一層封裝的第一層金屬接墊處穿 過核^膠材至第二層封裝的第二層金屬接墊處（亦可穿過 =- ^封I中的核心膠材）；填入導電材料（可藉由銅/錄/ 金成分之電鍍製程）形成兩金屬接墊間的互連結構。該第二 層封裝部分的第二層金屬接墊與該第一層封裝的第一層接 墊互連而第一層封裝金屬接墊之其他部位則與第二層封 裝的導電連接通孔連結。 由於本發明核心膠材與隔離底座之熱膨脹係數與接合 =印刷電路板相符，故本發明封裝結構可提供較佳的熱循 ^^^(temperature cycling test, TCT)可靠度、摔落測試 (P test)、錫球剪力試驗（Shear test)。再者，具有彈性/ 伸展f·生的增層亦可吸收熱循環期間所產生的機械性埶廡 为。 *、、、‘ 由於本發明之隔離底座内部含有玻璃纖維。其強度大 ^頂部的介電層，故可避免增層結構（特別是封裝邊緣區域） 又到外力而損壞。拔銲流程（rew〇rk)可簡單地替換錫球/錫 12 200921889 塊：由於封裝具有隔離底座 驟不會損傷到封裝的上表面。，卜般的錫球拔銲步 粒封者，其表示與說明了本發明—創新的半導體晶 t述㈣2構及其方法。儘管上面已就本發明之實施例 =讓=之熟習技藝者得以製作與使用本發明，但其 ΓΓ 無侷限本㈣之心。在不料本發明精神與 提下，得授允對於树日歧其描述所作之各類修 ，亦如本領域熟習技藝者所認知者，本發明之範 嚀將由以下所列請求項定義之。 【圖式簡單說明】 本發明可藉由說明書巾若干較佳實施例與其詳細敘述 及隨附圖式得以瞭解。然而，此領域之技藝者應得以領會 所有本發明之較佳實施例係用以說明而非就本發明之申請 專利範圍予以限定，其中： 圖一為根據先前技術中一半導體晶粒封裝之截面圖； 圖二為根據本發明實施例中一半導體晶粒封裝之截面 圖三為根據本發明實施例中半導體晶粒封裝之截面 圖； 圖四為根據本發明另一實施例中半導體晶粒封裝之截 面圖； 圖五為根據本發明又一實施例中半導體晶粒封裝之截 面圖；及 圖六為根據先前技術中一半導體晶粒封裝之截面圖。 13 200921889 【主要元件符號說明】 2 晶粒 236 接墊 2η 晶粒 246 接墊 4 核心膠材 266 焊接凸塊 6 銲墊 406 半導體元件 8 周圍材料 10 重佈層 12 上增層 14 隔離底座 16 黏著層 16a 黏著材料 18 通孑L 18a 通孔 18b 通孔 18c 填充材料 20 下增層 24 金屬互連 26 空隙 28 機械支撐 30 銲錫凸塊 32 接墊 34 通孔結構 40 被動元件 106 晶粒結構 14200921889 VI. Description of the Invention: [Technical Field to Be Invented] The component belongs to a semiconductor package, and more particularly to a laminated package structure of a semiconductor π device. Dry conductor [Prior Art] 3 circuit (10) die or ^ is a semiconductor (four) (cut, small, approximately rectangular IC component. Generally...round) is encapsulated in a die package structure. , 稞晶会 Du suspected that 4 we are not corroded. This type of button and two beta protects the 1C die, but for some small packages: For use, the package should be more space-consuming than the electrical one. Increasing the thermal divergence of the components > This and the industrial demand for reducing the volume and manufacturing costs are the reasons for the development of the industry. In the field of semiconductors, 'riding = interconnection 2:: the size is shrinking, so the demand for high-density components and uuerconnect is increasing. The library can be used to form a tin-tin bump (10) derb—^曰The germanium technology (fhP-chip) electrically connects the die to the bonding substrate, such as a germanium circuit board. The function of the die package includes the distribution of power, signal distribution, ‘: test, provide protection and support, and so on. As semiconductor components become more and more sturdy, traditional packaging technologies, such as lead frame packaging, ePaac, flexible package, rigid package technology, etc., can not meet the high component density. The fabrication of the wafer requires a ''synthesis 5', such as a Ball Grid Array (BGA) array structure to provide a high-density interconnect configuration in the surface area of the package. The general ball grid array package has a roundabout signal path, which will increase the impedance, and the heat dissipation mechanism will be worsened due to poor heat conduction in 200921889. The package density of the components in the distributed package structure is increased to meet the new generation of electronics. In the product: the new moon has become extraordinarily important. Force betting is on the development of reliable, cost-effective researchers who will have many heart-packaged structures. For example, 1: dusting, and high-efficiency signal delay, and less of all package components: configuration of the access pad (10) during signal transmission. ^ Domain, and more flexible transmission: In recent years, the development of the integrated circuit # integrated circuit bottleneck, miniaturized disk T;: 斩 become a", 夕日曰片组 (multi-chir^ module, MCM The package structure has been commonly used in electronic devices. ^ ^ Chip module package mainly contains the electrical and performance of more than two crystal and liter packages. Yan Yimei: National College: The first __ public (four) revealed a multi-die seal f as shown in Figure 6. In the semiconductor element, the via hole (4) is usually formed around the die buried by the package. The through hole is filled with the conductor material, and the end is covered by the exposed pad portion. The other end is the disk wiring layer (the connection is made. The wire layer corresponds to the conductor material (ie, the ^ part) Will be exposed from the protective layer' or - the external connection will be soldered to the interface. The electrode end of the die will be connected to the wire layer, and the other side will be exposed. The semiconductor component damage (Figure 6) is - Stack structure: It: The other grain structure 106 is stacked into three layers to be separately modularized. Each semiconductor element 406, two vertically adjacent grain structures 1〇6 will be connected by the bottom of the top plate. 236 is connected to an external connection (such as solder bump 266), and an underfill resin 416 is used to fill the gap between the two components of the 200921889 gap. Further, the package structure and the 246 are separately from both sides of the package; Dew; to 4; 236, (4) cover in the guide, will make == meter contains too many stacked dielectric layers and sealing material dielectric layer does not have: two problems; second, part of the structure : Under two; = expansion coefficient does not match its clock 蚪 偁 ^ people lack of buffer for releasing stress The thermal cycle of the structure is not reliable during operation. The present invention proposes a stacked package structure to overcome the above problems and has better component performance. - The semiconductor with the die and the conductive wiring can be reduced in cost, and provides high efficiency and high surname (tfk is another purpose to propose a laminate of semiconductor components, port) Package on package (p〇p). In addition, the invention aims to propose a method for manufacturing a convenient and cost-effective conductor laminated package structure. In the viewpoint of the present invention, a stacked package structure of a semiconductor element Including a = first layer package having more than one first layer of semiconductor crystal w. The upper surface and the lower surface of the first layer package have a first layer of pads formed thereon. a layer and/or a first layer of the lower layer to a fresh pad of the first layer of semiconductor grains to connect the first layer of the first layer of the upper and lower surfaces; the second layer of the package has at least one second半200921889 Conductor grain, And a second layer connection and a conductive connection via hole on the upper surface and the lower surface; wherein the second layer sealing has a second layer upper layer and/or a second layer lower layer layer bonding second semiconductor grain The second layer of solder joints is connected to the second layer of the upper and lower surfaces of the second wide package and the conductive connection vias. The conductive vias are coupled to the first layer of the upper and lower surfaces of the first layer package and the second layer of the package a second layer of the surface; the adhesive material is adhered to the lower surface of the first layer package and the upper surface of the second layer package. The first semiconductor package is the same size as the second semiconductor package, and the wrong one The size of the semiconductor die is larger than that of the second semiconductor die. The package structure further includes an isolation base formed on the first layer package with epoxy, FR4/FR5, low cliff (four) fine machine) Or double Malay 5 sub-H emulsion substrate heteropolyimine (B job aleimide Triazine, - chaos = this resin dimension. / ) Temple material is formed, and is filled with glass fiber: formed under the layer package. The tin ball / tin block is compared to ί. The number of conductive connection vias on the second package: :: Passive components. The upper and lower layers of the first layer and the second layer are coated with two; l the V-line core glue is formed beside the first semiconductor a 4 flute _ grain, and the dummy solder ball/tin is replaced by the first half V body crystal coat Dummy bump is used for broadcasting p to avoid damage from external forces. P) Material, mechanical support = 1 The form, purpose, viewpoint, characteristics and advantages of the two will follow the example of the company. The details of the description are only accompanied by the drawings; the schema of Figure 1 will be defined by the accompanying patent claims. The invention of the invention 200921889 [Embodiment] Here The present invention will be described with respect to the specific embodiments of the invention and the description thereof, which are intended to explain the structure or the steps of the present invention, and the specific embodiments of the invention are not limited to the scope of the invention. The preferred embodiment can be widely implemented in other different embodiments. * Month is also - the multi-layer package structure of the conductor element has its proposed structure, as shown in Figure -5 Figure 5. The wire and the metal interconnection are not. In the invention, most of the line drawings of each of the individual packages are the same. The embodiment will use the topmost package to implant each individual package to include a die 211, which is surrounded by the core glue 4, and has two interconnected vias 18 through the core glue 4. The die 2n The surrounding material 8 is formed between the sidewalls of the disk H (four) 4. The interconnecting via 18 is formed by the layer (10) 1 StdbutiGn layer, the ship (4) is bonded to the die ~. The upper layer (bUlld_up layer, ship) is formed in the grain ^, nucleus =: 4 and the top of the redistribution layer 1 下. The lower layer 2 is also the same as the surface. The 16-layer adhesive material is applied under the crystal grain 2n and the sound is added to the surface to provide an adhesive effect. A resilient adhesive material is used to absorb the stress generated by %. A plurality of joints 32 are formed below the lower buildup layer::: the interconnect vias 18 are aligned. The pads 32 may be copper/nickel/gold or pots. The stacked buildup system is formed on the die and the core glue 4, and the glue 4 is formed beside the die h to provide adhesion and protection. The redistribution layer 10 is formed inside the upper buildup layer 12. 200921889 Adhesive material Above the 16 is formed an isolation base 14, which is attached to the upper reinforcement 2. For example, the isolation base = = one, one, one, and the like 'The inside is also broken; the dimension is formed. In an embodiment, the isolation base 14 includes an adhesive layer 16: formed on the lower surface. The redistribution layer 10 is formed by electroplating or etching. The steps will continue until the copper coating reaches the desired thickness, and will extend out of the area to accommodate the grains, the so-called diffusion type; (n_〇Ut). The core glue 4 is coated with the grains 2η. Resin, varnish, silicone, FR5, bismuth or epoxy. The lower package is similar to the upper package, but the lower package is Η, and the upper layer 12 is formed with a connection (4). The second = solder metal interconnection 24 structure Or the conductive connection via is coupled to the upper interface of the (n-1)th layer. In this embodiment, there are at least three rows of joint/ply metal structures. The sandwich structure between the mat and the crucible can be used as a crease between the layers of the mechanical support 8 and the adjacent H6 can be packaged to better heat dissipation. In addition, the mother crystal grains and other layers of the packaged crystal grains may be of different types, such as flash type, passive elements, and the like. The underlying package and the port are more 匕3. The dry tin bumps 3〇 are coupled to the lower pads. An external view of another embodiment of the present invention. Except for the upper package: the wide structure is similar to that in the above embodiment. Please refer to ::: mounted in the isolation base 14 to include a through-hole structure passive 7G member 40. Further, in the embodiment of Fig. 3, the isolation base is removed. For 200921889 in the laminated grain structure and t, the smaller the size of the lower layer grain, the difference between the grain 2η and the grain 2 兰兰μ η in Fig. 1 . The smaller the daily granules, the larger the core glue will occupy. Under this architecture, the core package area of the underlying package will be larger than that of the ^7 type of the package, so that the mechanical support can be strengthened to carry the package of the upper layer. Another embodiment of the present invention is described with respect to the second embodiment. In order to form a via 18b (e.g., a via-level via) through each of the layers in the package, the passive component 40 must be formed over the adhesive material 16a rather than in the original figure. The conductive material 18d is coated on the surface of the through-hole, ', the true filling material 18c will be filled back into the through-hole 18b, and the through-hole 18a is a single-layer through-hole structure compared to the through hole (10). Fig. 5a to Fig. 5c show the sealing structure of the upper layer, the intermediate layer and the lower layer of the present invention. The upper seal has only one side of the build-up layer, while the towel and the lower layer have a build-up structure on both sides. 9 The package is a stacked structure design. The stacking process of each level of the package board is to connect the metal 1 structure by soldering, or to make the via hole and then form a conductive interconnect structure. Each layer of package board can be packaged for final testing, and a diffusion structure gamma squeaking process can be used on each package board. A repairable junction is also provided in the package to be repaired by a de-soldering step (de_soldering). In the package structure of the present invention, the passive components are stacked on the top surface by surface adhesion technology (8 amps & "10", "SMT". In addition, in the present invention, side-by-side sealing and stacking Parallel design of the package structure is also possible. Since each package of the present invention has the same thermal expansion coefficient as the printed circuit board (using the core rubber of the phase 200921889 = BT or FR5), it is punishable to obtain a better package test. The present invention also provides a method of forming a semiconductor die package interconnect structure comprising the steps of: preparing a first layer substrate (the material of the substrate is preferably Βτ or FR5), the substrate having a first layer of die accommodating The through hole is electrically connected to the first layer through the through hole; the adhesive material is adhered to the periphery and the bottom of the first die and at least one first die is embedded in the die receiving through hole of the first layer substrate; Forming a first build-up layer on the upper surface and/or the lower surface of the first die and the first layer substrate, and passing the first layer of the first die of the first die through the first conductive connection via First welding of a layer Metal pad coupling; ^ ★ Prepare a second layer substrate (the material of the substrate is preferably BT or FR5). The first layer of the substrate has a second layer of grain receiving through holes and a second layer of conductive bonding to adhere the adhesive material. Forming a through hole in the periphery and the bottom of the first die and breaking the first particle into the die receiving through hole of the second layer; forming a die and a second layer on the upper surface and/or the lower surface The layer buildup layer 'through the second layer of conductive connection vias and the second layer of the second solder layer 曰曰: 曰曰 can also be printed on the second solder metal pad on the upper surface of the package Paste; on the formation = 2 table (four) - welding gold 4 pad printed on the following: =:: i: (; Tntingsy, the first layer package 11 200921889 tin reflow (re_flow) Forming the interconnect structure. The monthly method further includes the step of cutting the panel along the scribe Hne 卩16® layer package (PoP) separation and copper-plated substrate (laminated PPer f01i), metal sputtering, copper/nickel/ The gold plating method forms a redistribution layer (in the buildup layer) on the first layer and the first layer package. It also includes the steps of forming a stacked package interconnect structure: aligning the first layer package in the form of a sealing plate with the second layer package and bonding the material by adhesive bonding; further comprising forming an interconnection through mechanical drilling The hole structure, the edge interconnection through hole is from the first metal pad of the first layer package through the core material to the second layer metal pad of the second layer package (may also pass through the =- ^ seal The core rubber in I); filled with a conductive material (which can be formed by a copper/recording/gold plating process) to form an interconnection structure between the two metal pads. The second layer of metal pads of the second package portion The first layer of the first layer of the metal pad is interconnected with the first layer of the first layer of the package, and the other portion of the first layer of the metal pad is connected to the conductive via of the second package. Since the thermal expansion coefficient of the core rubber and the isolation base of the present invention is consistent with the bonding = printed circuit board, the package structure of the present invention can provide better thermal cycling test (TCT) reliability and drop test (P Test), Shear test. Furthermore, the build-up layer having elasticity/stretching can also absorb mechanical enthalpy generated during thermal cycling. *, , , ‘ Since the isolated base of the present invention contains glass fibers. Its high strength ^ top dielectric layer, can avoid the buildup structure (especially the edge area of the package) and damage to external forces. The soldering process (rew〇rk) can simply replace the solder ball/tin 12 200921889 Block: Since the package has an isolated base, it does not damage the upper surface of the package. , a solder ball soldering step, which represents and describes the invention - an innovative semiconductor crystal structure and method. Although the present invention has been made and used by those skilled in the art of the present invention, it is not limited to this (4). Unexpectedly, the spirit and scope of the present invention may be granted to various modifications of the description of the tree, and as will be appreciated by those skilled in the art, the scope of the invention will be defined by the claims listed below. BRIEF DESCRIPTION OF THE DRAWINGS The invention can be understood by the following detailed description of the preferred embodiments of the invention and the accompanying drawings. However, those skilled in the art should understand that the preferred embodiments of the present invention are intended to be illustrative and not to limit the scope of the present invention, wherein: FIG. 1 is a cross section of a semiconductor die package according to the prior art. 2 is a cross-sectional view of a semiconductor die package in accordance with an embodiment of the present invention; FIG. 4 is a semiconductor die package in accordance with another embodiment of the present invention; 5 is a cross-sectional view of a semiconductor die package in accordance with yet another embodiment of the present invention; and FIG. 6 is a cross-sectional view of a semiconductor die package in accordance with the prior art. 13 200921889 [Main component symbol description] 2 die 236 pad 2η die 246 pad 4 core glue 266 solder bump 6 pad 406 semiconductor component 8 surrounding material 10 redistribution layer 12 upper layer 14 isolation base 16 adhesion Layer 16a Adhesive material 18 Via L 18a Via 18b Via 18c Filler material 20 Lower buildup layer 24 Metal interconnect 26 Space 28 Mechanical support 30 Solder bump 32 Pad 34 Via structure 40 Passive component 106 Grain structure 14

Claims (1)

200921889 七、申請專利範圍·· 1.::::體:件，層叠封裝結構，包含： 晶粒，該第一=^’=2有至少—個的第一層半導體 層下增#以耦人層上增層與/或一第一 席卜項層以耦合該第—層半 ^ 層封《上下表面之第一層接塾，•及 ^ 一第二層封裝，其内具有至少— 第一 Μ㈣U R 個苐—層半導體晶粒與 第:=，=二_的上表面與下表面有 弟-層接墊形成，其中第二層封裝具有 與/或第二層下增層以耦合 θ言層 料笛-層切體晶粒之銲墊 與石玄第—層封裝上下表面之第二層接塾及第 通孔，而該第一層導雷诵；?丨总4人 曰¥電 4料電通孔係耦合至該第一層 表面的第一層接墊及該第二 戒上下 接墊。 S封裝上下表面的第二層 2. 如請求項！所述之層叠封裝結構，其中該第— 尺寸與該第二層封裝之尺寸相同。 胃 ^ 3. 如請求項“斤述之層疊封裝結構’更包含黏著材料黏附 在该第一層封裝的下表面上盘該第-爲私莊 一為弟—層封裝的上表面 上。 4.如請求項1所述之層疊封裝結構，其中該第—層晶粒的 15 200921889 尺寸比該第二層晶粒的尺寸大。 5.如請求項丨所述之層疊封裝結構，更包含一隔離底座形 成在該第一層封裝上方。 6.如凊求項5所述之層疊封裝結構，其中該隔離底座係以 環氧樹脂（epoxy)、FR4/FR5玻纖環氧基板、聚醯亞胺 (P〇lyimide, PI)或雙馬來亞醯胺三氮雜苯樹脂 (B1SmaleimideTriazine，BT)等材質形成，且内摻玻璃纖 構’其—-層封裝與 8.如請求項丨所述之層疊封裝結構， 結構位於該第一層封裝與該第_ 匕3至> 一個支撐 、^ 層封骏之間。 9_如請求項丨所述之層疊封裝結 成在該第二層封裝下方。 更包含錫球/錫塊形 10.如請求項9所述之層疊封裝結 包含無鉛材質之組成。 其中該錫球/錫塊係 該第二層封裝 11 ·如請求項1所述之層疊封裝 16 200921889 導電連接通孔數目比該第一層封裝的通孔數目為多。 12. 如請求項丨所述之層疊封裝結構，更包含一個以上的被 動元件銲在該第一層封裴的上增層上。 13. 如請求項1所述之層疊封裝結構，其中該第一層與第二 層之上下增層包含複數條導線。 如請求項i所述之層疊封裝結構，更包含核心膠形成在 該第一半導體晶粒與第二半導體晶粒旁。 5.々。月求項1所述之層叠封裝結構，更包含假錫球/錫塊 供作機械支撐以避免受外力損傷。 「種形成半導體元件層疊封裝結構之方法，包含： ;備第層基底，该基底具有第一層晶粒容納通孔與 第—層導電連接通孔； /、 將黏著材料黏附在該第一晶粒四周與底部並將至少一 2第—晶㈣人該第-層基底之第—層晶粒容納通孔 I ， :該第-晶粒與第一層基底的上表面與/或下表面上形 層增層，並透過該第—層導電連接通孔將該第一 2逆之第-層銲墊與第—層增層之第—焊接金屬塾搞 17 200921889 苐一層晶粒容 準備一第二層基底，該第二層基底具有 納通孔與第二層導電連接通孔； 黏附在該第二晶粒四周與底部並將至少— 第-日日粒嵌人該第二層基底之晶粒容納通孔中； 2第Γ晶粒與第二層基底的上表面與/或下表面上形 成弟-層增層’透過導電連接通孔將該第二晶粒 層鲜墊與第二層增層之第二焊接金屬墊耦合； j第二層封裝上表面的第二焊接金屬墊上印上錫膏； 错由對準架裝系統將該第一層封裝的下表面農接在，亥 錫膏上；及 〜 對該錫膏施以迴銲（re_fl〇w)形成互連結構。 17.如請求項16所述之方法，更包含沿切割道切割封裝板 以分離該層疊封裝結構。 、 18.如請求項16所述之方法，更包含以銅箔基板、濺鍍金 屬、銅/鎳/金電鍍等方式在該第一層封裝與第二層封裝 上形成重佈層。 19.如請求項16所述之方法，更包含在該第一層封裝上形 成隔離底座’該隔離底座係以環氧樹脂（ep〇xy)、 FR4/FR5玻纖環氧基板、聚醯亞胺（p〇iyimide, ρι)或雙 馬來亞酿胺三氣雜苯樹脂（Bismaleimide Triazine，BT) 等材質形成。 18 200921889 2〇.如請求項19所述之方法，其巾該隔離底座内含玻璃纖 維。 21.—種形成半導體元件層疊封裝結構之方法，包含： 準備第—層基底，該基底具有第一層晶粒容納通孔， 且其上下表面上具有一第一層焊接金屬墊； 2黏著材料黏附在該第一晶粒四周與底部並將該至少 一個第一晶粒嵌入該第一層基底的第一層晶粒容 孔中； 在該至少—第一晶粒與第一層基底的上表面與/或下表 面上形成第一層增層，並將該第一晶粒之銲墊與該第一 層基底上下表面上的第一焊接金屬墊轉合； 準備一第二層基底，該第二層基底具有一第二層晶粒容 納通孔與第二層導電連接通孔； 將黏著材料黏附在該第二晶粒四周與底部並將至少一 個第一 a曰粒嵌入該第二層基底之晶粒容納通孔中； 在該第二晶粒與第二層基底的上表面與/或下表面上形 成第二層增層，透過該第二層導電連接通孔將該第二晶 粒之銲墊與該第二層增層的第二焊接金屬墊與該第: 層基底上下表面的部分第二焊接金屬墊耦合；及 以黏著材料對準並堆疊該第一層封裝與第二層封裝（封 裝板形式）’以機械鑽孔方式形成互連通孔，該互連通 孔係攸5亥第—層封裝的第一焊接金屬墊穿過該第二層 基底的上表面、核心膠材至下表面處’並將導電材質^ 19 200921889 入該互連通孔以形成互連結構。 20200921889 VII. Patent application scope ···::: body: piece, laminated package structure, including: die, the first = ^ ' = 2 has at least one of the first layer of semiconductor layer under the increase # to couple Adding a layer on the human layer and/or a first layer of the first layer to couple the first layer of the upper and lower layers, and the second layer of the package, having at least the A (4) U R 苐-layer semiconductor dies are formed with the upper surface and the lower surface of the :=, = _ have a slab-layer pad, wherein the second layer package has and/or the second layer is layered to couple θ The layer of the flute-layer cut body die and the second layer of the upper and lower surfaces of the Shi Xuan first layer package and the first through hole, and the first layer leads the thunder; The 4-well electrical via is coupled to the first layer pad of the first layer surface and the second ring upper and lower pads. The second layer of the upper and lower surfaces of the S package 2. As requested! The stacked package structure, wherein the first dimension is the same size as the second layer package. Stomach ^ 3. The request item "packaged structure of the package" further comprises an adhesive material adhered to the lower surface of the first layer of the package, which is the upper surface of the package. The stacked package structure of claim 1, wherein the first layer of the dies 15 200921889 is larger than the second layer of dies. 5. The package structure as claimed in claim 1 further comprises an isolation The base is formed on the first layer package. 6. The package structure according to claim 5, wherein the isolation substrate is made of epoxy, FR4/FR5 glass epoxy substrate, polyimine (P〇lyimide, PI) or B1Smaleimide Triazine (BT) and other materials, and the interior of the glass-fiber structure is composed of - layer packaging and 8. As described in the claim a package structure, the structure being located between the first layer package and the first layer to the top layer of the support layer. 9_ The package package as described in claim 结 is formed under the second layer package. Further comprising a solder ball/tin block shape 10. The packaged package junction as claimed in claim 9 The composition of the lead-free material is included. The solder ball/tin block is the second layer package 11. The number of the conductive connection vias of the stacked package 16 200921889 as claimed in claim 1 is larger than the number of via holes of the first layer package. 12. The package structure of claim 1 further comprising more than one passive component soldered to the upper buildup layer of the first layer of the package. 13. The package structure of claim 1 wherein the The upper and lower layers of the first layer and the second layer comprise a plurality of wires. The layered package structure of claim i further comprises a core glue formed beside the first semiconductor die and the second semiconductor die. The laminated package structure according to Item 1, further comprising a dummy solder ball/tin block for mechanical support to avoid damage by an external force. The method for forming a semiconductor package package structure comprises: preparing a first layer substrate, the substrate Having a first layer of grain accommodating vias and a first layer of conductive connection vias; /, adhering an adhesive material around the bottom and bottom of the first die and at least one of the 2nd - (4) persons of the first layer of the substrate —layer grain accommodation a hole I, a layer formed on the upper surface and/or the lower surface of the first layer substrate, and the first 2 reverse layer-layer pad through the first layer conductive connection via hole The first layer of the first layer is provided with a second layer of a substrate having a via hole and a second layer of conductive connection vias; The periphery and the bottom of the die and at least the first day of the grain are embedded in the die of the second layer of the substrate; 2 the second die and the lower surface of the second substrate form a brother - layer buildup layer - coupling the second seed layer fresh pad to the second layer of the second solder metal pad through the conductive connection via; j solder paste on the second solder metal pad on the upper surface of the second layer package The wrong surface is attached to the lower surface of the first layer package by the alignment mounting system, and the solder paste is reflowed to form an interconnect structure. 17. The method of claim 16 further comprising cutting the package board along the scribe line to separate the package package structure. 18. The method of claim 16, further comprising forming a redistribution layer on the first layer package and the second layer package by a copper foil substrate, a sputter metal, a copper/nickel/gold plating, or the like. 19. The method of claim 16, further comprising forming an isolation base on the first layer package. The isolation substrate is epoxy (ep〇xy), FR4/FR5 glass epoxy substrate, and poly It is formed of an amine (p〇iyimide, ρι) or a bimaleimine triazine (BT). The method of claim 19, wherein the insulating base comprises glass fibers. 21. A method of forming a semiconductor device package structure comprising: preparing a first layer substrate having a first layer of die receiving vias and having a first layer of solder metal pads on the upper and lower surfaces; 2 adhesive material Adhering to the periphery and the bottom of the first die and embedding the at least one first die in the first layer of die holes of the first layer of the substrate; on the at least the first die and the first layer of the substrate Forming a first build-up layer on the surface and/or the lower surface, and bonding the pads of the first die to the first solder metal pad on the upper and lower surfaces of the first layer substrate; preparing a second layer substrate, The second layer substrate has a second layer of grain receiving through holes and a second layer of conductive connecting through holes; bonding an adhesive material around the bottom and bottom of the second die and embedding at least one first a grain into the second layer a die of the substrate is received in the via hole; a second build-up layer is formed on the upper surface and/or the lower surface of the second die and the second layer substrate, and the second crystal is connected through the second conductive connection via hole a solder pad of the grain and a second soldering gold of the second layer a pad is coupled to a portion of the second solder metal pad of the upper and lower surfaces of the first layer substrate; and the first layer package and the second layer package (in the form of a package board) are aligned and stacked by the adhesive material to form an interconnection by mechanical drilling a through hole, the first soldering metal pad of the first through-layer package passes through the upper surface of the second layer substrate, the core glue to the lower surface, and the conductive material is entered into the The vias are interconnected to form an interconnect structure. 20
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