CN101425510A - Sensor module package structure and method of the same - Google Patents
Sensor module package structure and method of the same Download PDFInfo
- Publication number
- CN101425510A CN101425510A CNA2008101731367A CN200810173136A CN101425510A CN 101425510 A CN101425510 A CN 101425510A CN A2008101731367 A CNA2008101731367 A CN A2008101731367A CN 200810173136 A CN200810173136 A CN 200810173136A CN 101425510 A CN101425510 A CN 101425510A
- Authority
- CN
- China
- Prior art keywords
- layer
- ground floor
- encapsulation
- hole
- crystal grain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A package on package structure for semiconductor devices comprises at least one first level package having at least first level semiconductor die therein, wherein the package having first level contact pads formed on a first upper and lower surfaces of the first level package, the first level package having a first level upper build up layers and/or a first level lower build up layer to couple to bonding pads of the first level semiconductor die to contact first level pads on the both upper and lower surfaces of the first level package; a second level package having at least one second semiconductor die contained therein, wherein the second level package has a second level contact pads on a second upper and lower surfaces of the second level package, and conductive connecting through holes; wherein the second level package have a second level upper build up layer and/or second level lower build up layer to couple second level bonding pads of the second semiconductor die to contact second level pads and the conductive connecting through holes on the upper and lower surface of the second level package, conductive through holes being coupled to the first level pads of upper and lower surfaces of the first level package and the second level pads of upper and lower surface of the second level package; and adhesion materials attached on lower surface of the first level package and the upper surface of the second level package.
Description
Technical field
The invention belongs to a kind of semiconductor packages, particularly about a kind of stacked package structure of semiconductor element.
Background technology
Integrated circuit (IC) crystal grain or chip are small-sized, the IC elements that are rectangle approximately that go up to downcut from semiconductor crystal wafer (as Silicon Wafer).Generally speaking, naked crystalline substance can be covered by in the die package structure to protect them not to be corroded.This class encapsulating structure can effectively be protected IC crystal grain, but for some small-sized polycrystalline grain package application, encapsulating structure more takes up space than expection.Increase the thermal transpiration and the electrical property efficiency of element and reduce industrial requirements such as volume and manufacturing cost for ordering about IC packaging industrial reasons of development at present.In semiconductor applications, the density of element constantly increases, and size is constantly dwindled, so also constantly increase with in response to said circumstances for the encapsulation of high density components and interconnection technique (interconnect) demand.Use welding material can form solder bump (solder bump).Having known Flip Chip (flip-chip) in the field can be electrically connected to crystal grain the adhesive lining bottom, as printed circuit board (PCB).The function of die package has comprised electric energy distribution, signal distributions, thermal transpiration, protection is provided and supports or the like.When becoming, semiconductor element becomes increasingly complex, traditional encapsulation technology, for example leaded package (lead frame package), soft encapsulation (flexible package), hard encapsulation (rigidpackage) technology etc. can not satisfy the making demand of high component density small chip.Generally speaking, the battle array encapsulating structure as ball grid array (BGA, Gall Grid Array) formula can provide highdensity interconnection configuration in the package surface zone.General ball grid array packages has circuitous signal path, and impedance is raise, and is not good at making the cooling mechanism variation because of its heat conduction.Along with the increase of packaging density, disperse the heat energy that element is produced in the encapsulating structure just to become especially important.For the package requirements of the satisfied electronic product of generation newly, the researcher is developing many mental and physical efforts stakes reliably, is according with on cost benefit, miniaturization and the dynamical encapsulating structure.For example, its requirement comprises the shared zone of the signal delay when reducing electronic signal transmission, all packing components and has more flexible output and goes into connection pad (I/O) configuration.
In recent years, the encapsulation technology of integrated circuit (chip) becomes high-effect development of integrated circuits bottleneck gradually, microminiaturized and multi-chip module (multi-chips module, encapsulating structure MCM) generally be used in electronic installation in.The multi-chip module encapsulation has mainly comprised the crystal grain more than two and has coated wherein, to promote the electrical and usefulness of encapsulation.
United States Patent (USP) the 2005161833rd publication number has disclosed a kind of polycrystalline grain encapsulating structure, as shown in Figure 6.In semiconductor element, through hole (via) can form around the crystal grain that encapsulation is buried usually.Can insert conductive material in the through hole, and the one end covered by exposed connection pad position, the other end then is connected with wiring layer (wiring layer).The position (being the connection pad position) of the corresponding conductive material of this conductor layer can expose out in the self-insurance sheath, or an outside link can weld with this connection pad position.The electrode tip of crystal grain can be connected with this conductor layer, and another side then can expose outside.Semiconductor element 406 (Fig. 6) is to be a stack architecture, and its other grainiess 106 is stacked as three layers with the difference modularization.In each semiconductor element 406, two vertical adjacent grainiesses 106 can be connected by the connection pad 236 of its top and bottom and the link of outside (as solder bump 266), and use the bottom to fill the space that (underfill) resin 416 is inserted between two elements.Moreover encapsulating structure can be with multilayer mode storehouse, and its connection pad position 236 and 246 can expose out from the two sides that encapsulates respectively.Also can form a welding resisting layer (solder resist) 25 in the encapsulation covers on conductor layer and the resin bed.
Because contain the dielectric layer and the encapsulant of too many storehouse in the general package design, can make its heat radiation variation, and reduce integral member usefulness.Add its dielectric layer and do not have elasticity (being non-soft materials), the problem that can cause thermal coefficient of expansion not conform to; Moreover, being short of the resilient coating that can discharge stress in the part-structure, it is also unreliable that it designs during the thermal cycle of encapsulating structure and running.
Therefore, the present invention proposes a kind of stacked package structure overcoming the problems referred to above, and have better element efficiency.
Summary of the invention
Purpose of the present invention encapsulates (crystal grain assembling) for a semiconductor element with crystal grain and conducting wiring is provided, and can reduce cost, and the encapsulating structure of high-effect and high-reliability is provided.
Another object of the present invention for the stacked package structure that proposes a kind of semiconductor element (Packageon Package, PoP).
Another purpose of the present invention is for proposing the manufacture method of a kind of convenience, the cost-benefit semiconductor laminated encapsulating structure of symbol.
In viewpoint of the present invention, the stacked package structure of semiconductor element comprises at least one ground floor encapsulation, has more than one ground floor semiconductor grain in it, has the ground floor connection pad to form on the upper surface of ground floor encapsulation and the lower surface.The encapsulation of this ground floor also have increase on the ground floor layer with/or a ground floor under increase layer and be coupled to the weld pad of its ground floor semiconductor grain to be connected the ground floor connection pad that ground floor encapsulates upper and lower surface; Have at least one second semiconductor grain in the second layer encapsulation, and second layer connection pad and conduction connecting through hole are arranged on its upper surface and the lower surface; Wherein second layer encapsulation have increase on the second layer layer with/or the second layer under increase layer coupling second semiconductor grain second layer weld pad with the second layer connection pad that is connected second layer encapsulation upper and lower surface with conduct electricity the binding through hole.Conductive through hole is to be coupled to the ground floor connection pad of ground floor encapsulation upper and lower surface and the second layer connection pad of second layer encapsulation upper and lower surface; And sticky material is to stick on the upper surface of the lower surface of ground floor encapsulation and second layer encapsulation.
Its first semiconductor packages and second semiconductor packages measure-alike, and the size of its first semiconductor grain is big than second semiconductor grain.Also comprising an isolated base in the encapsulating structure is formed in this ground floor encapsulation, this base is with epoxy resin (epoxy), FR4/FR5 glass fibre epoxy substrate, polyimides (polyimide, PI) or two Maleimide triazine resin (BismaleimideTriazine, BT) etc. material forms, and in mix glass fibre.Tin ball/block tin is to form in the below of second layer encapsulation.The material of tin ball/block tin has comprised unleaded compound.The number that the conduction connecting through hole is gone up in second layer encapsulation is encapsulated as many than ground floor.The more than one passive device of can burn-oning on the upper surface of ground floor encapsulation.Increasing up and down of the ground floor and the second layer comprised many leads in the layer.Core glue is formed on this first semiconductor grain and second semiconductor grain next door, and false solder ball/block tin (dummybump) is to be made for mechanical support to avoid being subjected to damage.
The aforesaid form of the present invention, purpose, viewpoint, feature and advantage will see obviously more along with description detailed in the following preferred embodiment and follow graphic thereof, its details describe with accompanying drawing only in order to state the present invention clearly.And category of the present invention will be defined by the claim of enclosing.
Description of drawings
The present invention can be described in detail with it and accompanying drawing is understood by some preferred embodiments in the specification.Yet, the operator in this field deserved with understand all preferred embodiments of the present invention be in order to the explanation but not limited with regard to claim scope of the present invention, wherein:
Fig. 1 is the sectional view according to semiconductor die package in the prior art;
Fig. 2 is the sectional view according to semiconductor die package in the embodiment of the invention;
Fig. 3 is the sectional view according to semiconductor die package in the embodiment of the invention;
Fig. 4 is the sectional view according to semiconductor die package in another embodiment of the present invention;
Fig. 5 is the sectional view according to semiconductor die package in further embodiment of this invention; And
Fig. 6 is the sectional view according to semiconductor die package in the prior art.
Embodiment
The present invention herein will be described in detail at invention specific embodiment and viewpoint thereof, and this type of is described as explaining structure of the present invention or steps flow chart, and it is the usefulness that is provided with illustrating but not gives the reality that the present patent application claim limits.Therefore, the specific embodiment and preferred embodiment in specification, the present invention also can extensively be performed among other different embodiment.
The present invention disclosed a kind of semiconductor element the multilayer encapsulating structure its a kind of semiconductor die package has been proposed, comprise crystal grain, conducting wiring and metal interconnect structure, as Fig. 1～shown in Figure 5.The most main element of each individual packages is all identical with structure in the invention.Embodiment can use the encapsulation of the superiors to be described.
Each individual packages all comprises a crystal grain 2n, and it is centered on by core glue material 4, and contains through-hole interconnection 18 structures and pass core glue material 4.Can form material around 8 between the sidewall of crystal grain 2n and core glue material 4.Through-hole interconnection 18 can be by rerouting layer (redistribution layer, RDL) 10 weld pad 6 that is coupled to crystal grain 2n.On increase the layer (build-up layer, BUL) 12 is the tops that are formed at crystal grain 2n, core glue material 4 and rerouting layer 10.Under increase layer and 20 also be formed on the lower surface equally.Sticky material 16 be coat crystal grain 2n below and on increase layer 12 top so that the adhesion effect to be provided.Can use the rubber-like sticky material to absorb the stress that thermal cycle was produced.A plurality of connection pads 32 be formed on down increase the layer 20 below respectively with through-hole interconnection 18 aligned in position.Connection pad 32 can be copper/nickel/gold or other metal material.The layer that increases of institute's storehouse is to be formed at crystal grain 2n and core glue material 4 tops, and this core glue material 4 is to be formed at crystal grain 2n side so that adhesion and protection effect to be provided.10 on rerouting layer is formed on and increases layer 12 inside.
There is the isolated base 14 of formation sticky material 16 tops, and this sticky material 16 is to stick to increase on the layer 12.For example, isolated base 14 is well materials such as epoxy resin, FR4/FR5, PI, BT resin, and its inner glass fibre in addition forms.In one embodiment, isolated base 14 has comprised adhesion coating 16 and has been formed on lower surface.Rerouting layer 10 is to electroplate or engraving method formation.Copper (with/or nickel) plating step can last till always that copper coating reaches desirable thickness.It is outer to hold crystal grain, promptly so-called diffusion type design (fan-out) that conductive layer can extend the zone.Core glue material 4 is coating crystal grain 2n.It can resin, compound, silica gel, FR5, BT or epoxy resin form.
Lower floor's encapsulation is similar with the upper strata encapsulation, but lower floor's encapsulation does not comprise isolated base 14.And increasing on it has connection pad 32 to form on layer 12.The connection pad of n layer encapsulation is to be coupled to the last connection pad of (n-1) layer by interconnect 24 structures or conduction connecting through hole of weld metal.
At least connection pad/weld metal the interconnection structure that contains three rows in the present embodiment.Sandwich between pad and the pad can be used as mechanical support 28.The space 26 that is produced between two adjacent encapsulated layers can give the preferable thermal diffusivity of encapsulating structure.In addition, every layer crystal grain can be different types with the crystal grain of other layer encapsulation, for example die type such as memory, flash memory, passive device.The encapsulating structure of bottom has also comprised solder bump 30 and has been coupled to down connection pad 32.
Fig. 2 has represented another embodiment of the present invention.Except its upper strata encapsulating structure, among the figure most structure all to the foregoing description in similar.Please refer to Fig. 2, be encapsulated in and more contain a through-hole structure 34 in the isolated base 14 to hold passive device 40.
In addition, in the embodiment of Fig. 3, isolated base then is removed.For the laminated die structure, size of lower floor's crystal grain is just more little more for it, as the difference of crystal grain 2n among Fig. 1 and crystal grain 2.Crystal grain is more little, and the shared space of its core glue material is just big more.Bottom encased core glue under this kind framework zone can be greatly than the package design framework of other type, so the mechanical support that can strengthen the overall package structure is to carry the encapsulation on its upper strata.
Fig. 4 has illustrated another embodiment of the present invention, and is similar with second embodiment.In order to form a through hole 18b (as the ground floor through-hole interconnection) who passes each layer in the encapsulation, passive device 40 palpiforms are formed in sticky material 16a top, but not the position among Fig. 1 originally.Electric conducting material 18d can be coated on through hole 18b surface, and packing material 18c can fill out back among the through hole 18b, and than through hole 18b, through-hole interconnection 18a then is the through-hole structure of individual layer.
Fig. 5 a to Fig. 5 c has represented the encapsulating structure of upper strata of the present invention, intermediate layer and lower floor.Upper strata encapsulation only contains the layer that increases of single face, and intermediate layer and lower floor encapsulate then that all there is layer reinforced structure on the two sides.
Stacked package is to be a kind of nesting structural embedded control design.The storehouse flow process of its each level package board is to use welding manner that each metal interconnect structure is connected, or getting out through hole forms conductive interconnecting structure again.Every layer of package board all can be carried out the final test (final testing) of package board level, and the packaging technology of diffusion type structure (fan-out) can be used on every layer of package board.Also providing the repair type structure in its encapsulation, is to be repaired by tip-off step (de-soldering).In encapsulating structure of the present invention, its passive device is that (surface mounting technology, SMT) storehouse is on end face with the surface adhering technology.In the present invention, the side-by-side encapsulation also is possible with the design that stack type encapsulation structure walks abreast in addition.Because each encapsulation of the present invention has identical thermal coefficient of expansion (using identical core glue material-BT or FR5) with printed circuit board (PCB), so can obtain better packaging and testing reliability.
The present invention also proposes a kind of method that forms the semiconductor die package interconnection structure, and it comprises the following step:
Prepare a ground floor substrate (material of substrate is good with BT or FR5), this substrate has ground floor die receiving through-hole and ground floor conduction connecting through hole;
Sticky material is sticked to this first crystal grain to embed in the die receiving through-hole of this ground floor substrate with the bottom and with at least one first crystal grain all around;
On the upper surface of this first crystal grain and ground floor substrate and lower surface, form ground floor and increase layer, be coupled with the first weld metal pad that ground floor increases layer by the ground floor weld pad of this ground floor conduction connecting through hole with this first crystal grain;
Prepare a second layer substrate (material of substrate is good with BT or FR5), this second layer substrate has a second layer die receiving through-hole and second layer conduction connecting through hole;
Sticky material is sticked to this second crystal grain to embed in the die receiving through-hole of this second layer substrate with the bottom and with at least one second crystal grain all around;
On the upper surface of this second crystal grain and second layer substrate and lower surface, form the second layer and increase layer, be coupled with the second weld metal pad that the second layer increases layer by the second layer weld pad of this second layer conduction connecting through hole with this second crystal grain;
On the second weld metal pad of second layer encapsulation upper surface, stamp tin cream; Also can on encapsulating the first weld metal pad of lower surface, ground floor stamp tin cream to form solder bump thereon;
Be installed on the tin cream by the lower surface of alignment bracket assembling system (mounting system) this ground floor encapsulation; And
Tin cream is imposed reflow (re-flow) form interconnection structure.
The inventive method has also comprised along the step of Cutting Road (scribe line) cutting panel, laminated encapsulation (PoP) is separated and form rerouting layer (be positioned at and increase layer) in the mode that copper clad laminate (laminated copper foil), metal sputtering, copper/nickel/gold are electroplated in ground floor and second layer encapsulation.
Other method of the present invention also comprises the step that forms laminated package interconnect structure: the encapsulation of the ground floor of package board form is aimed at second layer encapsulation and with the sticky material storehouse that bonds; The mode that also comprises with machine drilling forms the through-hole interconnection structure, and this through-hole interconnection is to pass the second layer metal connection pad place (also can pass core glue material in second layer encapsulation) of core glue material to second layer encapsulation from the ground floor metallic pad place of ground floor encapsulation; Insert electric conducting material (can by the electroplating technology of copper/nickel/golden composition) and form the interconnection structure between two metallic pad.The ground floor connection pad interconnection of the second layer metal connection pad of this second layer packed part and the encapsulation of this ground floor, other position of second layer package metals connection pad then link with the conduction connecting through hole that the second layer encapsulates.
Because core glue material of the present invention conforms to the printed circuit board (PCB) of joint with the thermal coefficient of expansion of isolated base, so encapsulating structure of the present invention can provide preferable thermal cycle test (temperature cyclingtest, TCT) reliability, drop test (drop test), tin ball shear test (Shear test).Moreover, have elasticity/extensibility increase the layer also can absorb the mechanicalness thermal stress that is produced during the thermal cycle.
Because glass fibre is contained in isolated base of the present invention inside.Its intensity is greater than the dielectric layer at top, so can avoid layer reinforced structure (particularly package edge zone) to be subjected to external force and damage.Pull out weldering flow process (rework) and can replace tin ball/block tin simply: because encapsulation has the isolated base structure, so general tin ball pulls out the upper surface that the weldering step can not be damaged to encapsulation.
As described, its expression and semiconductor die package interconnection structure and method thereof that the present invention's one innovation has been described.Allow the skilled person in this field be made and use the present invention although described with regard to embodiments of the invention above, description wherein there is no limitation meaning of the present invention.Under the prerequisite of not disobeying be contrary to the present invention's spirit and category, must award fair all kinds of modifications and the change of doing for the present invention and description thereof, also as this area skilled person cognition, category of the present invention will be by being as the criterion that claim defines.
Claims (10)
1, a kind of stacked package structure of semiconductor element comprises:
At least one ground floor encapsulation, the ground floor semiconductor grain that has at least one in it, the upper surface of this ground floor encapsulation has the ground floor connection pad to form with lower surface, this ground floor encapsulation also have increase on the ground floor layer with/or a ground floor under increase layer the ground floor connection pad that encapsulates upper and lower surface with weld pad and this ground floor of this ground floor semiconductor grain that is coupled; And
The encapsulation of one second layer, have at least one second layer semiconductor grain and second layer conductive through hole in it, and the upper surface of this second layer encapsulation and lower surface have second layer connection pad to form, wherein second layer encapsulation have increase on the second layer layer with/or the second layer under increase layer with the weld pad of this second layer semiconductor grain that is coupled and the second layer connection pad and the second layer conductive through hole of this second layer encapsulation upper and lower surface, and this ground floor conductive through hole is to be coupled to this ground floor to encapsulate the ground floor connection pad of upper and lower surface and the second layer connection pad that this second layer encapsulates upper and lower surface.
2, the stacked package structure of semiconductor element as claimed in claim 1 also comprises on the lower surface that sticky material sticks to the encapsulation of this ground floor on the upper surface with this second layer encapsulation.
3, the stacked package structure of semiconductor element as claimed in claim 1 also comprises an isolated base and be formed on this ground floor encapsulation top, and tin ball/block tin is formed on this second layer encapsulation below.
4, the stacked package structure of semiconductor element as claimed in claim 1, also comprise at least one supporting construction between the encapsulation of this ground floor and this second layer encapsulate to avoid damaged by external force, this supporting construction can be false tin ball/block tin.
5, the stacked package structure of semiconductor element as claimed in claim 1, wherein the layer that increases up and down of this ground floor and the second layer comprises many leads, more than one passive device be welded in this ground floor encapsulation on increase on the layer.
6, the stacked package structure of semiconductor element as claimed in claim 1 also comprises core glue and is formed on by this first semiconductor grain and second semiconductor grain.
7, a kind of method that forms semiconductor element stacked package structure comprises:
Prepare a ground floor substrate, this substrate has ground floor die receiving through-hole and ground floor conduction connecting through hole;
Stick to around this first crystal grain sticky material with the bottom and at least one first crystal grain is embedded in the ground floor die receiving through-hole of this ground floor substrate;
On the upper surface of this first crystal grain and ground floor substrate and lower surface, form ground floor and increase layer, and be coupled with the first weld metal pad that ground floor increases layer by the ground floor weld pad of this ground floor conduction connecting through hole with this first crystal grain;
Prepare a second layer substrate, this second layer substrate has a second layer die receiving through-hole and second layer conduction connecting through hole;
Sticky material is sticked to this second crystal grain to embed in the die receiving through-hole of this second layer substrate with the bottom and with at least one second crystal grain all around;
On the upper surface of this second crystal grain and second layer substrate and lower surface, form the second layer and increase layer, be coupled with the second weld metal pad that the second layer increases layer by the second layer weld pad of conduction connecting through hole with this second crystal grain;
On the second weld metal pad of second layer encapsulation upper surface, stamp tin cream;
Be installed on this tin cream by the lower surface of alignment bracket assembling system this ground floor encapsulation; And
This tin cream is imposed reflow form interconnection structure.
8, the method for formation semiconductor element stacked package structure as claimed in claim 7 also comprises the mode of electroplating with copper clad laminate, jet-plating metallization, copper/nickel/gold and encapsulates formation rerouting layer with the second layer in this ground floor encapsulation.
9, the method for formation semiconductor element stacked package structure as claimed in claim 7 also is included in this ground floor encapsulation and goes up the formation isolated base.
10, a kind of method that forms semiconductor element stacked package structure comprises:
Prepare a ground floor substrate, this substrate has the ground floor die receiving through-hole, and has a ground floor weld metal pad on its upper and lower surface;
Sticky material is sticked to this first crystal grain, and also at least one first crystal grain embeds in the ground floor die receiving through-hole of this ground floor substrate with this with the bottom all around;
On the upper surface of this at least one first crystal grain and ground floor substrate and lower surface, form ground floor and increase layer, and the weld pad of this first crystal grain is coupled with the first weld metal pad on this ground floor substrate upper and lower surface;
Prepare a second layer substrate, this second layer substrate has a second layer die receiving through-hole and second layer conduction connecting through hole;
Sticky material is sticked to this second crystal grain to embed in the die receiving through-hole of this second layer substrate with the bottom and with at least one second crystal grain all around;
On the upper surface of this second crystal grain and second layer substrate and lower surface, form the second layer and increase layer, the weld pad of this second crystal grain is increased the second weld metal pad of layer with this second layer and the part second weld metal pad of this second layer substrate upper and lower surface is coupled by this second layer conduction connecting through hole; And
Aim at and this ground floor encapsulation of storehouse and second layer encapsulation with sticky material, form through-hole interconnection in the machine drilling mode, this through-hole interconnection be pass this second layer substrate from the first weld metal pad of this ground floor encapsulation upper surface, core glue material to lower surface, and conductive material inserted this through-hole interconnection to form interconnection structure.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/933,703 | 2007-11-01 | ||
| US11/933,703 US20080157327A1 (en) | 2007-01-03 | 2007-11-01 | Package on package structure for semiconductor devices and method of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101425510A true CN101425510A (en) | 2009-05-06 |
Family
ID=40615994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101731367A Pending CN101425510A (en) | 2007-11-01 | 2008-10-30 | Sensor module package structure and method of the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101425510A (en) |
| TW (1) | TW200921889A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127035A1 (en) * | 2012-02-28 | 2013-09-06 | Liu Sheng | Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process |
| CN106952884A (en) * | 2016-01-06 | 2017-07-14 | 美光科技公司 | Fan-out wafer level encapsulation |
| WO2018126545A1 (en) * | 2017-01-05 | 2018-07-12 | 华为技术有限公司 | Electronic package structure with high reliability, circuit board and device |
| CN110010479A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of Fan-out packaging technology of radio frequency chip |
| CN112435966A (en) * | 2020-11-27 | 2021-03-02 | 上海易卜半导体有限公司 | Package and method of forming the same |
| US11973061B2 (en) | 2020-11-27 | 2024-04-30 | Yibu Semiconductor Co., Ltd. | Chip package including stacked chips and chip couplers |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI396004B (en) * | 2009-08-26 | 2013-05-11 | Au Optronics Corp | Electronic apparatus |
| US11876063B2 (en) * | 2021-08-31 | 2024-01-16 | Nanya Technology Corporation | Semiconductor package structure and method for preparing the same |
-
2008
- 2008-10-28 TW TW097141429A patent/TW200921889A/en unknown
- 2008-10-30 CN CNA2008101731367A patent/CN101425510A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127035A1 (en) * | 2012-02-28 | 2013-09-06 | Liu Sheng | Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process |
| CN106952884A (en) * | 2016-01-06 | 2017-07-14 | 美光科技公司 | Fan-out wafer level encapsulation |
| CN106952884B (en) * | 2016-01-06 | 2018-08-24 | 美光科技公司 | Fan-out wafer grade encapsulates |
| WO2018126545A1 (en) * | 2017-01-05 | 2018-07-12 | 华为技术有限公司 | Electronic package structure with high reliability, circuit board and device |
| CN108541340A (en) * | 2017-01-05 | 2018-09-14 | 华为技术有限公司 | A kind of high-reliability electronic encapsulating structure, circuit board and equipment |
| US11011477B2 (en) | 2017-01-05 | 2021-05-18 | Huawei Technologies Co., Ltd. | High-reliability electronic packaging structure, circuit board, and device |
| CN110010479A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of Fan-out packaging technology of radio frequency chip |
| CN110010479B (en) * | 2018-10-10 | 2021-04-06 | 浙江集迈科微电子有限公司 | Fan-out packaging process of radio frequency chip |
| CN112435966A (en) * | 2020-11-27 | 2021-03-02 | 上海易卜半导体有限公司 | Package and method of forming the same |
| CN112435966B (en) * | 2020-11-27 | 2021-09-14 | 上海易卜半导体有限公司 | Package and method of forming the same |
| US11973061B2 (en) | 2020-11-27 | 2024-04-30 | Yibu Semiconductor Co., Ltd. | Chip package including stacked chips and chip couplers |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200921889A (en) | 2009-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7294928B2 (en) | Components, methods and assemblies for stacked packages | |
| US20080157327A1 (en) | Package on package structure for semiconductor devices and method of the same | |
| KR100868419B1 (en) | Semiconductor device and manufacturing method thereof | |
| US8383456B2 (en) | Semiconductor device and manufacturing method therefor | |
| US8236608B2 (en) | Stacking package structure with chip embedded inside and die having through silicon via and method of the same | |
| CN104064551B (en) | A kind of chip stack package structure and electronic equipment | |
| US6753616B2 (en) | Flip chip semiconductor device in a molded chip scale package | |
| US9449941B2 (en) | Connecting function chips to a package to form package-on-package | |
| CN101859752B (en) | Stacking package structure with chip embedded inside and grain having through silicon via and method of manufacturing the same | |
| US20120267782A1 (en) | Package-on-package semiconductor device | |
| EP2798675B1 (en) | Method for a substrate core layer | |
| CN100576476C (en) | Chip buried in semiconductor encapsulation base plate structure and method for making thereof | |
| US20020114143A1 (en) | Chip-scale packages stacked on folded interconnector for vertical assembly on substrates | |
| US20050230797A1 (en) | Chip packaging structure | |
| US20090166873A1 (en) | Inter-connecting structure for semiconductor device package and method of the same | |
| US20020030261A1 (en) | Multi-flip-chip semiconductor assembly | |
| KR100353170B1 (en) | Miniaturized chip scale ball grid array semiconductor package | |
| KR20090039411A (en) | Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof | |
| US6448110B1 (en) | Method for fabricating a dual-chip package and package formed | |
| CN101425510A (en) | Sensor module package structure and method of the same | |
| CN101740551A (en) | Laminated die package structure for semiconductor element and method thereof | |
| US7276800B2 (en) | Carrying structure of electronic components | |
| CN100485894C (en) | Flip chip packaging method and packaging structure thereof | |
| US6495771B2 (en) | Compliant multi-layered circuit board for PBGA applications | |
| CN100539102C (en) | Circuit board is embedded with the electric connection structure of semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090506 |