TW201601214A - 封裝半導體裝置之方法及封裝的半導體裝置 - Google Patents

封裝半導體裝置之方法及封裝的半導體裝置 Download PDF

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TW201601214A
TW201601214A TW103138512A TW103138512A TW201601214A TW 201601214 A TW201601214 A TW 201601214A TW 103138512 A TW103138512 A TW 103138512A TW 103138512 A TW103138512 A TW 103138512A TW 201601214 A TW201601214 A TW 201601214A
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perforations
insulating material
semiconductor device
width
integrated circuit
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TW103138512A
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TWI625783B (zh
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鄭禮輝
蔡柏豪
林俊成
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台灣積體電路製造股份有限公司
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Abstract

本申請案揭示封裝半導體裝置的方法以及封裝的半導體裝置。在一些實施方式中，封裝半導體裝置的方法包含耦合穿孔至絕緣材料，該穿孔各自具有第一寬度。晶粒亦耦合至該絕緣材料。接近每一個穿孔之部分的絕緣材料係被移除。接近每一個該穿孔之被移除的部分的絕緣材料具有第二寬度，該第二寬度係小於該第一寬度。

Description

封裝半導體裝置之方法及封裝的半導體裝置
本發明係關於封裝半導體裝置之方法及封裝的半導體裝置。
半導體裝置用於不同的電子應用中，例如個人電腦、手機、數位相機以及其他電子設備。典型係藉由在半導體基板上連續沉積絕緣或介電層、傳導層以及半導體材料層，並且使用微影製程將不同材料層圖案化，以於其上形成電路組件與元件，而製造半導體裝置。
在單一半導體晶圓上，典型製造數十或數百個積體電路。沿著切割線，藉由鋸該積體電路而將個別晶粒切單。而後，例如，分別將該個別晶粒封裝於多晶片模組或其他形式的封裝中。
半導體工業藉由持續縮小最小特徵尺寸，使得在給定面積中可集成較多組件，而持續改良不同電子組件(例如，電晶體、二極體、電阻器、電容器等)的積體密度。在一些應用中，這些較小的電子組件，例如積體電路晶粒，亦需要較小的封裝，相較於傳統的封裝，其使用較小的面積。
本發明之封裝半導體裝置的方法包含耦合複數個穿孔至絕緣材料，每一個穿孔包括第一寬度，以及耦合複數個晶粒至該絕緣材料。所述方法包含移除接近每一個穿孔之部分的絕緣材料，其中接近每一 個穿孔之所移除的該部分的絕緣材料包括第二寬度，第二寬度小於第一寬度。在其他實施方式中，封裝半導體裝置的方法包含在載體上方形成絕緣材料，以及耦合複數個穿孔至該絕緣材料。每一個穿孔包括第一寬度。所述方法包含耦合複數個晶粒至絕緣材料，以及將模塑材料置於該複數個穿孔附近、該複數個晶粒附近，以及該複數個穿孔與該複數個晶粒之間。在複數個穿孔、複數個晶粒與模塑材料上方，形成互連結構。移除該載體，以及移除接近每一個穿孔之部分的絕緣材料。接近每一個穿孔之被移除的該部分的絕緣材料包括第二寬度，第二寬度小於第一寬度。切割絕緣材料、模塑材料以及互連結構，以形成複數個封裝的半導體裝置。
在一些實施方式中，封裝的半導體裝置包含積體電路晶粒、置於該積體電路晶粒附近的模塑材料，以及置於該模塑材料內的複數個穿孔。每一個穿孔包括第一寬度。絕緣材料係置於積體電路晶粒的第一側、模塑材料以及每一個穿孔的第一部分上。互連結構係置於積體電路晶粒的第二側、模塑材料以及複數個穿孔上。每一個穿孔的第二部分係透過絕緣材料中的開口而暴露。絕緣材料中的開口包括第二寬度，第二寬度小於第一寬度。
100‧‧‧載體
102‧‧‧薄膜
104‧‧‧絕緣材料
106‧‧‧晶種層
106/112‧‧‧穿孔
108‧‧‧犧牲材料
112‧‧‧傳導材料
120‧‧‧積體電路晶粒
122‧‧‧基板
124‧‧‧接觸墊
126‧‧‧絕緣材料
128a‧‧‧第一側
128b‧‧‧第二側
130‧‧‧模塑材料
132、132’‧‧‧互連結構
132C‧‧‧接觸墊
132D‧‧‧介電層
132M‧‧‧傳導金屬線
134‧‧‧連接器
136‧‧‧切割帶
138‧‧‧支撐物
140‧‧‧保護膜
142‧‧‧開口
142’、142”‧‧‧開口
144‧‧‧焊膏
146‧‧‧錐形
146’‧‧‧階梯形
146”‧‧‧直的側壁
150‧‧‧封裝的半導體裝置
152‧‧‧打線接合
156‧‧‧晶粒
158‧‧‧連接器
159‧‧‧金屬間化合物
160‧‧‧封裝的半導體裝置
162‧‧‧模塑材料
164‧‧‧絕緣材料
170‧‧‧封裝的半導體裝置/PoP裝置
172‧‧‧工具
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意，根據產業之標準實施方式，各種特中並非依比例繪示。實際上，為了清楚討論，可任意增加或減少各種特徵的尺寸。
圖1至圖16係根據本申請案揭示內容之一些實施方式說明封裝半導體裝置之方法的各種階段之橫切面圖。
圖17至圖18係根據一些實施方式說明封裝的半導體裝置耦合至另一封裝的半導體裝置之橫切面圖。
圖19係根據一些實施方式說明該封裝的半導體裝置之更詳細部 分的橫切面圖。
圖20係根據一些實施方式說明焊球之剪力測試的橫切面圖。
圖21與圖22係根據一些實施方式分別說明封裝的半導體裝置之部分的俯視圖與橫切面圖。
圖23係根據一些實施方式說明封裝的半導體裝置之橫切面圖。
圖24係根據一些實施方式說明封裝半導體裝置之方法的流程圖。
以下揭示內容提供許多不同的實施方式或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式，亦可包含在該第一與第二特徵之間形成其他特徵的實施方式，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施方式與/或所討論架構之間的關係。
再者，此處可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋此處使用的空間對應描述。
本申請案揭示內容的實施方式提供封裝半導體裝置的新方法及其結構，其中相較於該封裝的穿孔(through-via)寬度，絕緣材料層中的開口具有較小寬度。具有縮小寬度的開口改善該封裝的可信賴度、 排除相鄰模塑材料層中的凹槽與穿孔間隙，以及防止水蒸氣滲入，將進一步描述如下。
圖1至圖16係根據本申請案揭示內容之一些實施方式說明封裝半導體裝置之方法的各種階段之橫切面圖。
首先參閱圖1，為了封裝該半導體裝置，提供載體100。例如，該載體100可包括玻璃、氧化矽、氧化鋁或半導體晶圓。該載體100亦可包括其他材料。例如，在俯視圖中，該載體可為圓形、正方形或是矩形。或者，該載體100可包括其他形狀。
在一些實施方式中，該載體100具有形成於其上的薄膜102。例如，該薄膜102包括光熱轉換(LTHC)材料或是其他材料。例如，該LTHC薄膜102包括約0.5微米至約0.3微米的厚度。或者，該薄膜102可包括其他尺寸。在一些實施方式中，未包含該薄膜102。
如圖1所示，為了封裝半導體裝置，絕緣材料104係置於該薄膜102上方。於實施方式中，在該載體100上方形成該絕緣材料104，其中未包含該薄膜102。該絕緣材料104包括用於封裝之鈍化層。例如，在一些實施方式中，該絕緣材料104包括膠/聚合物基底緩衝層。例如，在一些實施方式中，該絕緣材料104包括抗焊劑(SR)、聚亞醯胺(PI)、聚苯噁唑(PBO)或多層或其組合。例如，該絕緣材料104包括約1微米至約20微米的厚度。或者，該絕緣材料104可包括其他材料與尺寸。例如，使用旋轉塗覆、分層或是其他方法形成該絕緣材料104。
接著，如圖2所示，在該絕緣材料104上方形成晶種層106。該晶種層106包括晶種材料，用於穿孔的後續電鍍製程，此處將進一步詳述。該晶種層106包括金屬，例如銅、鈦與銅合金、其他金屬、合金、其組合或多層。例如，該晶種層106包括約500埃(Å)至約5000埃的厚度。或者，該晶種層106可包括其他材料與尺寸。藉由物理蒸氣沉積(PVD)或其他方法形成該晶種層106。
而後，如圖3所示，在該晶種層106上方形成犧牲材料108。例如，在一些實施方式中，該犧牲材料108包括光阻、有機材料、絕緣材料或是其他材料。如圖4所示，使用微影製程或直接圖案化製程，將該犧牲材料108圖案化為所欲之圖案，成為複數個穿孔。在微影製程中，包括光阻或其他材料的該犧牲材料108暴露至由微影遮罩(未繪示)反射的或穿過該微影遮罩所傳送的光或能量，其中該微影遮罩具有所欲之圖案於其上。而後，將該犧牲材料108顯影，接著，部分的該犧牲材料108被灰化或蝕刻移除。例如，直接圖案化製程可包括使用雷射在該犧牲材料108中形成圖案。或者，可使用其他方法圖案化該犧牲材料108。
如圖5所示，在該晶種層106上方之該犧牲材料108的圖案中，使用電鍍製程形成傳導材料112。例如，該電鍍製程可包括電化學電鍍(ECP)或其他形式的電鍍製程。該晶種層106係作為該傳導材料112之電鍍製程的晶種。通過該圖案化的犧牲材料108，在該晶種層106上方，電鍍該傳導材料112。
而後，如圖6所示，剝離或移除該犧牲材料108。在移除該犧牲材料108之後，在該晶種層106上已經電鍍的傳導材料112之間的絕緣材料104上方留下部分的晶種層106。
而後，如圖7所示，移除晶種層106的暴露部分。例如，使用蝕刻製程或其他製程，移除在傳導材料112區域之間晶種層106的暴露部分。晶種層106與傳導材料112包括半導體裝置之封裝的穿孔106/112。穿孔106/112各自包括具有該晶種層106之材料的下部部分，以及具有被鍍傳導材料112之上部部分。
在其他實施方式中，可使用減除技術(subtractive technique)、鑲嵌技術或其他方法，形成穿孔106/112。例如，在減除技術中，可在絕緣材料104的整個表面上方形成傳導材料，例如銅(Cu)、銅合金、 其他金屬或其組合或多層，以及將傳導材料圖案化，形成穿孔106/112。在這些實施方式中，例如，穿孔106/112可包括單一材料層(未繪示)。可使用光微影製程，藉由在傳導材料上方形成光阻層、將該光阻層暴露至由具有所欲之圖案於其上的微影遮罩所反射的或穿過該微影遮罩所傳送的光或能量，以及將該光阻層顯影，而將該傳導材料圖案化。而後，將光阻層的暴露部分(或未暴露部分，取決於該光阻層為正或負)灰化或移除。而後，在蝕刻製程過程中，被圖案化的光阻層作為傳導材料的蝕刻遮罩。移除光阻層，所留下圖案化的該傳導材料係具有所欲之圖案的穿孔106/112。
例如，在一些實施方式中，該穿孔106/112的第一側係耦合至絕緣材料104。
接著，請參閱圖8，在形成該穿孔106/112之後，提供複數個積體電路晶粒120，並且將其接合至該絕緣材料104。此處，例如在一些請求項中，該積體電路晶粒120亦係指晶粒120。該積體電路晶粒120包括半導體裝置，其將依本申請案揭示內容的一些實施方式而被封裝。例如，可先在一或多個半導體晶圓上製造積體電路晶粒120，並且將該晶圓切單或切割，形成複數個積體電路晶粒120。
該積體電路晶粒120包含具有半導體材料的基板122，並且包含製造於其中與/或其上的電路、組件、接線以及其他元件(未繪示)。例如，該積體電路晶粒120係用以進行預定之功能，例如邏輯、記憶、處理、其他功能或其組合。該積體電路晶粒120之俯視圖的典型形狀為正方形或矩形(未繪示)。該積體電路晶粒120各自包含第一側128a與第二側128b，該第二側128b係與該第一側128a對立。該積體電路晶粒120的該第一側128a係耦合至該絕緣材料104。
該積體電路晶粒120各自包含橫過其第二側128b而形成的複數個接觸墊124。該接觸墊124係電性耦合至該基板122的部分。例如，該 接觸墊124包括傳導材料，例如銅、鋁、其他金屬、或其合金或多層。或者，該接觸墊124可包括其他材料。
該接觸墊124係位於形成於該基板122上方的絕緣材料126內。該接觸墊124的部分頂部表面係暴露於該絕緣材料126內，因而可對該接觸墊124形成電性連接。該絕緣材料126可包括一或多個絕緣材料層，例如二氧化矽、氮化矽、聚合物材料或其他材料。例如，在一些實施方式中，該絕緣材料126包括鈍化層。
複數個積體電路晶粒120係耦合至載體100的該絕緣材料104上方。圖8至圖16僅繪示兩個積體電路晶粒120；然而，可有數十、數百或更多的積體電路晶粒120耦合至載體100並且同時被封裝。該積體電路晶粒120的第一側128a係耦合至絕緣材料104上方的載體100。可使用接著劑，例如晶粒接合薄膜(die attach film，DAF)，將積體電路晶粒120耦合至絕緣材料104。可手動或使用例如取放型機器之自動機器，將該積體電路晶粒120耦合至絕緣材料104。
在一些實施方式中，積體電路晶粒120可耦合至置於載體100上的絕緣材料104，以及積體電路晶粒120係被封裝於個別封裝中。在其他實施方式中，可一起封裝二或多個積體電路晶粒120。例如，根據一些實施方式，可一起封裝具有相同或不同功能的複數個積體電路晶粒120。
而後，如圖9所示，模塑(molding)材料130係置於積體電路晶粒120與穿孔106/112的上方與附近。例如，在一些實施方式中，使用晶圓級成型製程而施用模塑材料130。在絕緣材料104的暴露部分上方、積體電路晶粒120的側壁上方、積體電路晶粒120的第二側128b的暴露部分上方以及穿孔106/112的側壁與頂部表面上方，形成模塑材料130。例如，在穿孔106/112的附近、複數個晶粒120的附近以及在複數個穿孔106/112與複數個晶粒120之間，形成模塑材料130。在一些 實施方式中，模塑材料130的第一側係耦合至絕緣材料104。
例如，可使用壓縮模塑成型、轉移模塑成型或其他方法，將模塑材料130成型。例如，模塑材料130封裝積體電路晶粒120與穿孔106/112。例如，模塑材料130可包括環氧化合物、有機聚合物、具有或不具有添加的二氧化矽或玻璃填充物之聚合物、或其他材料。在一些實施方式中，模塑材料130包括液體模塑化合物(LMC)，當施用時，其係膠體形式液體。當施用時，模塑材料130亦可包括液體或固體。或者，模塑材料130可包括其他絕緣與/或封裝材料。
接著，在一些實施方式中，使用硬化製程將模塑材料130硬化。該硬化製程可包括將模塑材料130加熱至預定溫度一段時間、使用退火製程或是其他加熱製程。該硬化製程亦可包括紫外線(UV)光暴露製程、紅外線(IR)能量暴露製程、其組合或其與加熱製程之組合。或者，可使用其他方法將模塑材料130硬化。在一些實施方式中，不包含硬化製程。
而後，如圖10所示，移除模塑材料130的頂部部分。例如，在一些實施方式中，使用研磨製程移除該模塑材料130的頂部部分。例如，該研磨製程可包括類似於使用旋轉磨砂機用於木頭之磨砂製程的製程。例如，該研磨製程可包括將具有適當材料或用於研磨模塑材料130的材料排列於其上的圓盤旋轉至預定高度。例如，該圓盤可具有鑽石排列於其上。例如，在一些實施方式中，使用化學-機械拋光(CMP)製程，移除模塑材料130的頂部部分。亦可使用研磨製程與CMP製程的組合。例如，在一些實施方式中，當達到積體電路晶粒120的第二側128b與/或穿孔106/112的頂部表面時，CMP製程或研磨製程可用以停止。在一些實施方式中，CMP製程與/或研磨製程包括前側研磨製程。
在一些實施方式中，不需要研磨或CMP製程。例如，在一些實 施方式中，可使用模塑材料130，因而該模塑材料130之水平達到與積體電路晶粒120的第二側128b以及穿孔106/112的頂部表面之水平實質上相同。在一些實施方式中，在使用模塑材料130之後，模塑材料130的頂部表面可置於積體電路晶粒120的第二側128b與穿孔106/112的頂部表面下方，作為另一範例，未繪示。
在一些實施方式中，在研磨與/或CMP製程之後，或在模塑材料130沉積製程之後，模塑材料130的頂部表面係與積體電路晶粒120的第二側128b以及穿孔106/112的頂部表面實質共平面。與第二側128b以及穿孔106/112的頂部表面實質共平面之模塑材料130利於促使後續互連結構132的形成，如圖11所示。例如，在一些實施方式中，模塑材料130、積體電路晶粒120與穿孔106/112的頂部表包括實質共平面，用於形成互連結構132。
互連結構132形成於複數個穿孔106/112的第二側上方，該第二側係與複數個穿孔的第一側對立，該第一側係耦合至絕緣材料104。同樣地，互連結構132係形成於模塑材料130的第二側上方，該第二側係與模塑材料130的第一側對立，該第一側係耦合至絕緣材料104。同樣地，互連結構132係形成於積體電路晶粒120的第二側128b上方，該第二側128b係與積體電路晶粒120的第一側128a對立。
在一些實施方式中，互連結構132包括鈍化後互連(post-passivation interconnect，PPI)結構或是重佈層(redistribution layer，RDL)，其係形成於複數個積體電路晶粒120、模塑材料130以及穿孔106/112的頂部表面上方。例如，在一些實施方式中，互連結構132包含扇出(fan-out)區域，其將積體電路晶粒120上的接觸墊124足跡延伸為更大的封裝足跡。互連結構132包含複數個介電層132D與複數個傳導金屬線132M以及/或形成於該複數個介電層132D內的複數個傳導金屬孔(未繪示)。複數個傳導線132M與複數個傳導孔提供電性連接至積 體電路晶粒120的基板122上之接觸墊124。圖11至圖16繪示兩個佈線層；或者，互連結構132可包含一個佈線層或是三個或多個佈線層。
例如，藉由任何合適的方法，例如旋轉、CVD與/或電漿CVD(PECVD)，可由低介電常數(低K)介電材料形成介電層132D，低介電常數介電材料例如磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽(BPSG)、氟化的矽酸鹽玻璃(FSG)、SiOxCy、懸塗式玻璃、懸塗式聚合物、矽碳材料、其化合物、其複合物、其組合物或類似物。例如，傳導線132M與傳導孔可包括銅、銅合金、其他金屬或合金、或其組合或多層。例如，可使用刪減與/或鑲嵌技術，形成傳導線132M與傳導孔。可使用一或多個濺鍍製程、光微影製程、電鍍製程以及光阻剝離製程，形成傳導線132M與傳導孔，作為範例。亦可使用其他方法形成互連結構132。互連結構132包含接近頂部表面而形成的接觸墊132C。在一些實施方式中，接觸墊132C可包括球下金屬化(under-ball metallization，UBM)結構，其係配置為球柵式陣列(ball grid array，BGA)或其他圖案或配置。
在一些實施方式中，接著，複數個連接器134耦合至互連結構132的接觸墊132C，如圖12所示。例如，連接器134可包括共熔材料，例如焊料。在一些實施方式中，該共熔材料可包括焊球或焊膏，藉由將該共熔材料加熱至共熔材料的熔點而將其迴焊。使用焊球安裝製程或其他製程而附接連接器134。而後使共熔材料冷卻與重新固化，形成連接器134。連接器134可包含其他形式的電性連接器，例如微凸塊、可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊或柱狀物，以及可包含傳導材料，例如Cu、Sn、Ag、Pb或類似物。在一些實施方式中，封裝中未包含連接器134。而後，在一些實施方式中，進行連接器134的測試以確定所形成之連接的電性與結構完整性。
在一些實施方式中，在互連結構132上方的連接器134之間，形成絕緣材料，未繪示。在一些實施方式中，絕緣材料包括液體模塑化合物(LMC)。或者，絕緣材料可包括其他材料。在一些實施方式中，未包含絕緣材料。
而後，此處所描述之載體100與形成於其上的結構被倒轉，並且連接器134耦合至切割帶136，如圖13所示。切割帶136耦合至支撐物138。而後，亦如圖13所示，使用剝離(de-bonding)製程，移除載體100與薄膜102。
如圖14所示，在一些實施方式中，在絕緣材料104上方，形成保護膜140。例如，在一些實施方式中，在移除載體100之後，形成保護膜140。例如，在一些實施方式中，保護膜140包括後側薄層膜。保護膜140包括約1微米至約100微米的層狀塗覆帶(LC tape)或DAF。在一些實施方式中，使用層壓製程，形成保護膜140。保護膜140亦可包括其他材料、尺寸與形成方法。在一些實施方式中，未包含保護膜140。
而後，如圖15所示，將絕緣材料104圖案化。如圖23所示，在包含保護膜140的一些實施方式中，保護膜140亦被圖案化，此處將進一步描述。
接著，參閱圖15，根據本申請案揭示內容的一些實施方式，接近每一個穿孔106/112之部分的絕緣材料104係被移除。被移除之部分的絕緣材料104包括開口142，其中該開口142係形成於各個穿孔106/112上方。在一些實施方式中，該部分的絕緣材料104之寬度係小於穿孔106/112的寬度。例如，在一些實施方式中，絕緣材料104中的開口142之寬度係小於穿孔106/112之寬度。
在一些實施方式中，使用雷射移除該部分的絕緣材料104。或者，可使用其他方法，例如光微影製程，移除該部分的絕緣材料 104。例如，可使用微影製程或直接圖案化方法，形成絕緣材料104中的開口142。或者，可使用其他方法，移除接近複數個穿孔106/112之該部分的絕緣材料104。每一個穿孔106/112的部分係透過絕緣材料104中的開口142而暴露。每一個穿孔106/112的其他部分(例如，邊緣部分)仍被絕緣材料104覆蓋。此處，例如在一些請求項中，仍被絕緣材料104覆蓋之穿孔106/112的部分亦係指第一部分，以及透過絕緣材料104中的開口142而暴露之穿孔106/112的該部分亦係指第二部分。兩個穿孔106/112之更詳細圖式係如圖19所示，此處將進一步說明。
如圖16所示，在一些實施例中，在穿孔106/112的暴露部分上，形成焊膏144。該焊膏144便於使用連接器(請見圖17中的連接器158)而將封裝的半導體裝置150耦合至另一裝置，例如另一封裝的半導體裝置。在一些實施方式中，封裝的半導體裝置150在切割線區域上被切單(singulated)或切割，形成複數個封裝的半導體裝置150。例如，在一些實施方式中，沿著切割線，切割模塑材料130、互連結構132與絕緣材料104，形成複數個封裝的半導體裝置150。在其他實施方式中，如圖17所示，在封裝的半導體裝置150附接至其他封裝的半導體裝置160之後，封裝的半導體裝置150而後被切單。
例如，在圖1至圖16所示的實施方式中，繪示兩個積體電路晶粒120被封裝在一起。或者，三個或更多的積體電路晶粒120可被封裝在封裝的半導體裝置150中。部分的互連結構132可對於封裝在一起的複數個積體電路晶粒120提供水平電性連接。例如，一些傳導線132M與孔可包括兩個或多個積體電路晶粒120之間的接線。模塑材料130係置於複數個積體電路晶粒120附近與之間。互連結構132係置於複數個積體電路晶粒120與模塑材料130上方。積體電路晶粒120亦可單獨被封裝在封裝的半導體裝置150內，其橫切面圖係如圖17與18所示。
圖17與18係根據一些實施方式，亦說明此處所描述之封裝的半 導體裝置150耦合至另一封裝的半導體裝置160。在一些實施方式中，封裝的半導體裝置150包括第一封裝的半導體裝置150，以及該第一封裝的半導體裝置150係藉由複數個連接器158而耦合至第二封裝的半導體裝置160。例如，包括焊球或其他材料的連接器158係耦合在第一封裝的半導體裝置150的穿孔106/112與第二封裝的半導體裝置160的接觸墊之間。每一個連接器158係透過絕緣材料104而耦合至第一封裝的半導體裝置150之複數個穿孔106/112其中之一。
在一些實施方式中，當連接器158耦合至穿孔106/112時，在連接器158與在穿孔106/112上形成的穿孔106/112的材料(參照圖16)之間形成金屬間化合物(IMC)159，該穿孔106/112的材料為例如銅以及/或焊膏144。在一些實施方式中，包含第一封裝的半導體裝置150與第二封裝的半導體裝置160之封裝的半導體裝置170係包括堆疊封裝(package-on-package，PoP)裝置。
封裝的半導體裝置150包含形成在模塑材料130內的複數個穿孔106/112。該穿孔106/112對於封裝的半導體裝置150提供垂直連接。互連結構132對於封裝的半導體裝置150提供水平的電性連接。第二封裝的半導體裝置160亦包含互連結構132'，其對於封裝的半導體裝置160提供水平的電性連接。第二封裝的半導體裝置160之互連結構132'係藉由複數個連接器158而耦合至第一封裝的半導體裝置150的穿孔106/112。
第二封裝的半導體裝置160包含耦合至基板的一或多個積體電路晶粒156。在一些實施方式中，晶粒156包括記憶體晶片。例如，在一些實施方式中，晶粒156可包括動態隨機存取記憶體(DRAM)裝置。或者，晶粒156可包括其他形式的晶片。打線接合152可耦合至積體電路晶粒或晶粒156的頂部表面上的接觸墊，其係耦合至基板上的接合墊。例如，在一些實施方式中，打線接合152對於封裝的半導體裝置 160提供垂直電性連接。模塑材料162可置於打線接合152、積體電路晶粒或晶粒156以及基板之上方。
或者，PoP裝置170可包含此處描述之兩個封裝的半導體裝置150，在一些實施方式中，其係耦合在一起，未繪示於圖式中。在一些實施方式中，PoP裝置170可包括系統單晶片(system-on-a-chip，SOC)，作為另一範例。
在一些實施方式中，絕緣材料164係置於連接器158之間的封裝的半導體裝置150與160之間，其橫切面圖如圖18所示。絕緣材料164可包括其他材料，或未包含絕緣材料164。
圖19係根據一些實施方式說明圖15之更詳細部分的橫切面圖。根據一些實施方式，說明絕緣材料104中的開口142與142’之一些尺寸與形狀。在一些實施方式中，絕緣材料104中的開口142之側壁可包括錐形146。在其他實施方式中，絕緣層104中的開口142’之側壁可包括階梯形狀146’。
在一些實施方式中，穿孔106/112的寬度包括尺寸d1，其中尺寸d1包括約190微米至約210微米。例如，在一些實施方式中，尺寸d1包括約300微米或更小。或者，尺寸d1可包括其他值，例如大於約300微米。在一些實施方式中，開口142與142'的寬度包括尺寸d2，其中尺寸d2小於尺寸d1。例如，在一些實施方式中，尺寸d2包括小於尺寸d1約10%或大於尺寸d1約10%。在其他實施方式中，尺寸d2包括小於尺寸d1約10%至30%，作為另一範例。在一些實施方式中，尺寸d2包括約10微米至約350微米。或者，尺寸d2可包括其他值以及其他相對值。
圖20係根據一些實施方式說明連接器158的剪力測試之橫切面圖，該連接器158包括焊球，且該焊球係耦合至封裝的穿孔106/112。連接器158係透過絕緣材料104中的開口142而耦合至此處描述之封裝的半導體裝置150的穿孔106/112。使用工具172，藉由施加側向壓力 於連接器158上，測試耦合至穿孔106/112之連接器158的剪力。本申請案實施方式之實驗結果顯示錯誤的焊料接合需要增加焊球強度與較大的剪應力。由於部分的絕緣材料104係置於穿孔106/112之邊緣上方的頂部表面，因而避免於接近模塑材料130處形成凹槽，有利的是造成連接器158與穿孔106/112的連接強度增加。
圖21與22分別係根據一些實施方式說明封裝的半導體裝置150的部分之俯視圖與橫切面圖。圖21係根據一些實施方式繪示連接器158耦合至穿孔106/112。穿孔106/112與模塑材料130之間無凹槽形成；而是絕緣材料104的邊緣直接鄰接穿孔106/112。俯視圖中無法看見模塑材料130的任何部分。
圖22係封裝的半導體裝置150的區域之橫切面電子顯微鏡(XSEM)影像複製圖式，該區域係接近絕緣材料104中的開口142，其顯示接近穿孔106/112、連接器158、模塑材料130與絕緣材料104的密封良好區域。連接器158係充分附接至絕緣材料104。有利的是穿孔106/112與成型化合物130之間無凹槽形成。
圖23係根據一些實施方式說明封裝的半導體裝置150之橫切面圖。保護膜140係包含於封裝中，並且置於絕緣材料104上方。開口142”形成於絕緣材料104與保護膜140中。例如，在一些實施方式中，移除接近每一個穿孔106/112之部分的絕緣材料104係進一步包括移除接近每一個穿孔106/112之部分的保護膜140。
圖23亦說明一些實施方式，其中絕緣材料104(以及保護膜140)中的開口142”實質包括直的側壁146”。例如，在本申請案揭示內容的一些實施方式中，絕緣材料104中的開口142、142’與142”之側壁146、146’與146”包括例如錐形(如圖19所示之146)、實質直的(如圖23所示之146”)、階梯狀(如圖19所示之146’)以及/或其組合之形狀。或者，絕緣材料104中的開口142、142’與142”之側壁146、146’與146”可包括 其他形狀。
圖24係根據一些實施方式說明封裝半導體裝置的方法之流程圖180。在步驟182中，穿孔106/112(請見圖1至7)係耦合至絕緣材料104，每一個穿孔106/112具有第一寬度d1(圖19)。在步驟184中，晶粒120係耦合至絕緣材料104(圖8)。在步驟186中，移除接近每一個穿孔106/112之部分的絕緣材料104，其中接近每一個穿孔106/112之所移除的該部分的絕緣材料104係具有第二寬度d2，該第二寬度d2小於第一寬度d1(圖15與19)。
本申請案揭示內容的一些實施方式包含封裝半導體裝置的方法。其他的實施方式包含已經使用本申請案所描述之新方法而封裝後之封裝的半導體裝置150與/或170。
本申請案揭示內容之實施方式的一些優點包含提供封裝方法以及結構，其中穿孔上方之絕緣材料中的開口寬度小於該穿孔。絕緣材料中的開口寬度小於穿孔，防止在模塑材料與穿孔之間形成凹槽，這改善信賴度並且排除水蒸氣進入此凹槽中。避免形成連接器之間包括焊球、絕緣材料與模塑材料的間隙。由於模塑材料與穿孔之間無凹槽形成，因而無凹槽深度控制的問題。
再者，由於防止在模塑材料與穿孔之間形成凹槽，因而改良施加於穿孔頂部表面之焊膏的一致性。該焊膏僅形成於穿孔的頂部表面。例如，該焊膏未形成於穿孔的側壁上，該側壁係被模塑材料覆蓋。亦改良套合(overlay，OVL)效能。所述之新的封裝結構與方法可實施於且特別有利於晶圓級封裝(WLP)或晶片等級封裝(CSP)技術與製程。再者，本申請案所述之新的封裝方法與結構可簡易實施於製造與封裝製程流程中。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本發明之各方面。熟知此技藝之人士應理解可輕易使用本申 請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。
104‧‧‧絕緣材料
106/112‧‧‧穿孔
120‧‧‧積體電路晶粒
130‧‧‧模塑材料
132‧‧‧互連結構
134‧‧‧連接器
136‧‧‧切割帶
138‧‧‧支撐物
140‧‧‧保護膜
142”‧‧‧開口
146”‧‧‧側壁
150‧‧‧封裝的半導體裝置

Claims (10)

  1. 一種封裝半導體裝置的方法，該方法包括：耦合複數個穿孔至絕緣材料，該複數個穿孔各自包括第一寬度；耦合複數個晶粒至該絕緣材料；以及移除接近每一個該複數個穿孔之部分的該絕緣材料，其中接近每一個該複數個穿孔之被移除的該部分的該絕緣材料係包括第二寬度，該第二寬度小於該第一寬度。
  2. 如請求項1所述之方法，其中移除接近每一個該複數個穿孔之該部分的該絕緣材料係使每一個該複數個穿孔之被暴露的部分，以及其中該方法進一步包括在每一個該複數個穿孔之該被暴露的部分上方，形成焊膏。
  3. 如請求項1所述之方法，進一步包括在該複數個穿孔附近、該複數個晶粒附近以及該複數個穿孔與該複數個晶粒之間，形成模塑材料，或其中該方法進一步包括耦合該複數個穿孔至該絕緣材料以及耦合該複數個晶粒至該絕緣材料係包括耦合該複數個穿孔的第一側與該複數個晶粒，以及其中該方法進一步包括在該複數個穿孔的第二側及該複數個晶粒上方，形成互連結構，該第二側係與該第一側對立。
  4. 一種封裝半導體裝置的方法，該方法包括：在載體上方，形成絕緣材料；耦合複數個穿孔至該絕緣材料，該複數個穿孔各自包括第一寬度；耦合複數個晶粒至該絕緣材料；將模塑材料置於該複數個穿孔附近、該複數個晶粒附近以及 該複數個穿孔與該複數個晶粒之間；在該複數個穿孔、該複數個晶粒以及該模塑材料上方，形成互連結構；移除該載體；移除接近每一個該複數個穿孔之部分的該絕緣材料，其中接近每一個該複數個穿孔之被移除的該部分的該絕緣材料係包括第二寬度，該第二寬度小於該第一寬度；以及切割該絕緣材料、該模塑材料以及該互連結構，以形成複數個封裝的半導體裝置。
  5. 如請求項4所述之方法，其中耦合該複數個穿孔至該絕緣材料係包括電鍍製程，以及其中該電鍍製程包括：在該絕緣材料上方，形成晶種層；在該晶種層上方，形成犧牲材料；圖案化該犧牲材料；透過該圖案化的犧牲材料，在該晶種層上方，電鍍傳導材料；移除該犧牲材料，使部分的該晶種層暴露在該傳導材料之間；以及移除該晶種層之暴露的該部分。
  6. 如請求項4所述之方法，其中將該模塑材料置於該複數個穿孔與該複數個晶粒附近係包括在該複數個穿孔與該複數個晶粒上方，形成該模塑材料，以及其中該方法進一步包括從該複數個穿孔與該複數個晶粒上方，移除該模塑材料的頂部部分。
  7. 一種封裝的半導體裝置，包括：積體電路晶粒；模塑材料，其係置於該積體電路晶粒附近； 複數個穿孔，其係置於該模塑材料內，該複數個穿孔各自包括第一寬度；絕緣材料，其係置於該積體電路晶粒的第一側、該模塑材料以及該複數個穿孔各自的第一部份上；以及互連結構，其係置於該積體電路晶粒的第二側、該模塑材料以及該複數個穿孔上，其中每一個該穿孔的第二部分係透過該絕緣材料中的開口而暴露，以及其中該絕緣材料中的該開口包括第二寬度，該第二寬度係小於該第一寬度。
  8. 如請求項7所述之封裝的半導體裝置，其中該絕緣材料中的該開口之側壁包括選自於實質上由錐形、實質直的、階梯狀及其組合所組成的群組之形狀。
  9. 如請求項7所述之封裝的半導體裝置，進一步包括複數個該積體電路晶粒，其中該模塑材料係置於該複數個積體電路晶粒附近與之間，以及其中該互連結構係置於該複數個積體電路晶粒與該模塑材料上方。
  10. 一種堆疊封裝(package-on-package，PoP)裝置，其包含請求項7所述之封裝的半導體裝置，其中該封裝的半導體裝置包括第一封裝的半導體裝置，其中該PoP裝置包含第二封裝的半導體裝置，其藉由複數個連接器而耦合至該第一封裝的半導體裝置，以及其中該複數個連接器各自透過該絕緣材料而耦合至該複數個穿孔的其中之一。
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