TWI667760B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI667760B
TWI667760B TW104136449A TW104136449A TWI667760B TW I667760 B TWI667760 B TW I667760B TW 104136449 A TW104136449 A TW 104136449A TW 104136449 A TW104136449 A TW 104136449A TW I667760 B TWI667760 B TW I667760B
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conductive
layer
conductive feature
height
top surface
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TW104136449A
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TW201639103A (zh
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林孟良
黃震麟
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台灣積體電路製造股份有限公司
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Abstract

本發明係提供半導體裝置及其製造方法，一實施例的裝置包括一導電墊，位於一基底上。一鈍化層位於基底上，且覆蓋導電墊的至少一部分。一第一導電特徵位於導電墊上，且具有一平坦的頂表面。第一導電特徵具有一第一高度，第一高度係從導電墊測量至第一導電特徵的平坦的頂表面。一第二導電特徵位於鈍化層上，且具有一非平坦的頂表面。第二導電特徵具有一第二高度，第二高度係從鈍化層測量至第二導電特徵的非平坦的頂表面。

Description

半導體裝置及其製造方法
本發明係有關於一種半導體技術，特別是有關於半導體裝置及其製造方法。
半導體裝置應用於各種電子產品，例如個人電腦、手機、數位相機及其他電子設備。半導體裝置的製作通常包括在一半導體基底上依序沉積絕緣層(或介電層)、導電層及半導體層的多層材料層，且利用微影製程圖案化各個材料層，以在半導體基底上形成電路元件及部件。數十或數百個積體電路通常製造於單一半導體晶圓上。藉由沿著切割道(scribe line)切割積體電路，將各個晶粒/晶片(die)單體化(singulate)。之後，獨立的晶粒分開地封裝，舉例來說，各個晶粒分開地封裝於多晶片(multi-chip)模組內或其他類型的封裝體內。
透過持續降低最小特徵尺寸，半導體產業不斷改善各種電子元件(例如，電晶體、二極體、電阻、電容等)的集成密度，以容許在給定的面積內整合更多的元件。這些較小的電子元件例如積體電路晶片，也可在某些應用中要求更小的封裝體，其使用比以往的封裝體更小的面積。
本發明係提供一種半導體裝置，包括一導電墊， 位於一基底上。一鈍化層位於基底上，且覆蓋導電墊的至少一部分。一第一導電特徵位於導電墊上，且具有一平坦的頂表面。第一導電特徵具有一第一高度，第一高度係從導電墊測量至第一導電特徵的平坦的頂表面。一第二導電特徵位於鈍化層上，且具有一非平坦的頂表面。第二導電特徵具有一第二高度，第二高度係從鈍化層測量至第二導電特徵的非平坦的頂表面。
本發明係提供另一種半導體裝置，包括一導電墊，位於一基底上。一鈍化層順應性地位於基底上，且覆蓋導電墊的至少一部分。一通孔電極位於導電墊上，且具有一第一高度，第一高度係從導電墊測量至通孔電極的一頂表面。一導電線位於鈍化層上，且具有一第二高度，第二高度係從鈍化層測量至導電線的一頂表面，且第一高度大於第二高度。一介電材料層位於鈍化層上，且具有一頂表面與通孔電極的頂表面共平面。介電材料層密封導電線。
本發明係提供一種半導體裝置的製造方法，包括進行一第一形成步驟，以在一基底上形成具有一第一高度的一第一導電特徵以及具有一第二高度的一第二導電特徵。第一高度係從第一導電特徵的一底表面測量至第一導電特徵的一頂表面。第二高度係從第二導電特徵的一底表面測量至第二導電特徵的一頂表面，且第一高度大於第二高度。利用一介電材料層密封第一導電特徵的複數側壁以及第二導電特徵的頂表面及複數側壁。第一導電特徵的頂表面與介電材料層的一頂表面共平面。
50‧‧‧基底
52‧‧‧導電墊
54‧‧‧鈍化層
56‧‧‧晶種層
58‧‧‧光阻
60、60A、60B‧‧‧開口
62‧‧‧導電特徵/通孔電極
64‧‧‧導電特徵/導電線
62A、64A‧‧‧頂表面
70‧‧‧介電材料層
70A‧‧‧頂表面
72‧‧‧晶種層
74‧‧‧光阻
76、76A、76B‧‧‧開口
78、80‧‧‧導電特徵
90‧‧‧金屬蓋層
90A‧‧‧頂表面
94‧‧‧測試結構
96‧‧‧接觸探針
100‧‧‧晶粒
200‧‧‧承載基底
202、206‧‧‧黏著層
204‧‧‧介電層/背側重佈線結構
208‧‧‧電性連接結構/整合扇出型通孔電極
210‧‧‧模塑成型材料
212‧‧‧金屬線
214‧‧‧鈍化層
216‧‧‧重佈線層/前側重佈線結構
218‧‧‧導電連接結構
220‧‧‧框架
222‧‧‧第二承載基底
224‧‧‧可剝離膠
230‧‧‧開口
240‧‧‧第二封裝體
244‧‧‧切割工具
300‧‧‧第一封裝體
302‧‧‧基底
304‧‧‧導電墊
D1、D2‧‧‧直徑
H1、H2、H3‧‧‧高度
第1至9圖係繪示出根據某些實施例之半導體裝置的製造過程期間的中間步驟的剖面示意圖。
第10、11A-11B、12-13圖係繪示出根據某些實施例之半導體裝置的製造及測試過程期間的中間步驟的剖面示意圖。
第14、15及16圖係繪示出根據某些實施例之半導體裝置的剖面示意圖。
第17-19、20A-20B、21-24圖係繪示出根據某些實施例之堆疊式封裝(package-on-package，PoP)結構的製造過程期間的中間步驟的剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語等。類似地，也可使用例如“前側”及“後側”的用語，以更容易地辨別各種部件，例如可以辨別這些部件在另一部件的相對側。可以理解的是，除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
以下所討論的實施例可能討論特定的內容，即半導體裝置，其可能為扇出型(fan-out)或扇入型(fan-in)晶圓級封裝體。所屬技術領域中具有通常知識者閱讀所揭露內容可輕易理解在其他實施例中可考慮其他應用，例如不同的封裝類型或不同的配置。應注意的是，此處所討論的實施例可能未必敘述出可能存在於結構內的每一個部件或特徵。舉例來說，圖式中可能省略一個或多個部件，例如當部件的討論說明可能足以傳達實施例的各個樣態時可能將其從圖式中省略。再者，此處所討論的方法實施例可能以特定的進行順序來討論，然而在其他方法實施例中，可以以任何合理的順序進行。
在具體說明實施例之前，將簡要地說明本揭露實施例的某些有益的特徵及樣態。概括而言，本發明揭露一種半導體裝置及其製造方法，以增加晶圓的產量，降低製程成本，且改善介電材料的間隙填充，並減少在晶圓上的應力及翹曲(warpage)的問題。特別是，如以下所揭露的實施例，透過將形 成半導體裝置的內連線(interconnect)結構所需的製造步驟的數量最小化，而增加晶圓的生產率及降低製程成本。透過控制電鍍製程來達成製造步驟的數量的降低，控制電鍍製程對不同的導電特徵尺寸具有不同的鍍膜速率，能夠使得在同一鍍膜步驟中所形成的導電特徵具有高度的區別。
舉例來說，在一些實施例中，較大的導電特徵具有較快的鍍膜速率，且在同一鍍膜製程期間，相較於較小的導電特徵，較大的導電特徵鍍膜至較高的高度(厚度)。如此一來，可容許較大的導電特徵例如作為通孔電極(via)來連接內連線結構的次一層，而較小的導電特徵可為目前的內連線層內的導電線/結構。在此範例中，導電通孔電極及導電線皆同時在同一製程中形成，因此並不需要額外的圖案化步驟及形成鈍化層(passivation layer)的步驟。通孔電極及導線簡化的形成步驟及輪廓使得環繞這些特徵的介電材料的間隙填充能力提升。再者，在晶圓上的應力及翹曲的問題減少是由於盡可能減少鈍化層的形成步驟的緣故，原因在於許多鈍化層需要進行固化的步驟進而導致在晶圓上造成應力及翹曲。
第1至9圖係繪示出根據某些實施例之晶粒100的製造過程期間的中間步驟的剖面示意圖。第1圖繪示出晶粒100於製造過程的中間階段，其包括一基底50、一導電墊52及一鈍化層54。在第1圖所示的步驟之前，可根據適用的製程對晶粒100進行處理，以在晶粒100內形成一積體電路，進而形成一積體電路晶粒100。基底50可包括塊狀半導體基底(bulk semiconductor substrate)、絕緣層上覆半導體(semiconductor- on-insulator，SOI)基底、多層或梯度(gradient)基底或類似的基底。基底50的半導體可包括任何半導體材料，例如元素半導體(例如，矽、鍺或類似的材料)、化合物或合金半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、矽鍺、磷化砷鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵、及/或的磷化砷鎵銦(GaInAsP)或類似的材料)、或其組合。
基底50可包括複數積體電路元件(未繪示)。所屬技術領域中具有通常知識者可以理解，各種積體電路元件(例如，電晶體、二極體、電容器、電阻器、類似的元件或其組合)可形成基底50內及/或基底50上，以使得晶粒100具有設計所需的結構及功能。可使用任何適合的方法來形成積體電路元件。
基底50也可包括一內連線結構(未繪示)。內連線結構可形成於積體電路元件上方，其用來連接各個積體電路元件，以形成功能電路。內連線結構可由交替的介電材料層(例如，低介電常數(k)材料)及導電材料層(例如，銅)所構成，且可透過任何適合的方法(例如，沉積製程、鑲嵌製程、雙鑲嵌製程等)來形成。導電層及介電層可包括金屬線(未繪示)及介層窗(via，未繪示)，以將積體電路元件電性耦接至導電墊52。圖式中僅繪示出一部份的基底50，其足以充分地描述實施例。
晶粒100還包括位於基底50上方的導電墊52。導電墊52可形成於基底50內的內連線結構(未繪示)上方且與其電性接觸，以協助提供外部元件與積體電路元件連接。導電墊52位於可稱為晶粒100的主動側(active side)之上。在一些實施例中，透過在介電層(未繪示)或基底50內形成凹口(未繪示)來形 成導電墊52。可形成凹口以容許導電墊52嵌入介電層(未繪示)及/或基底50內。在其他實施例中，可省略凹口，而導電墊52可形成於介電層或基底50上。導電墊52可包括一薄晶種層(未繪示)，其由銅、鈦、鎳、金、錫、類似的材料、或其組合所構成。導電墊52的導電材料可沉積於上述薄晶種層上方。可透過電化學電鍍(electro-chemical plating)製程、化學氣相沉積(chemical vapor deposition，CVD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、原子層沉積(atomic layer deposition，ALD)製程、類似的製程、或其組合形成導電墊52的導電材料。在一實施例中，導電墊52的導電材料為銅、鎢、鋁、銀、金、錫、類似的材料、或其組合。導電墊52的厚度可介於大約0.5微米(μm)至大約4微米的範圍內。
為了清楚及簡化的目的，僅繪示出晶粒100內的一個導電墊52，所屬技術領域中具有通常知識者可輕易地理解晶粒100內可存在一個以上的導電墊52。
鈍化層54可形成於基底50及導電墊52上方，如第1圖所示。鈍化層54可由一種或多種適合的介電材料所構成，例如氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物)、極低介電常數材料(例如，多孔碳摻雜二氧化矽)、聚合物(例如，聚醯亞胺)、防焊漆(solder resist，SR)、聚苯並噁唑(polybenzoxazole，PBO)、苯並環丁烯(benzocyclobutene，BCB)、模塑成型化合物、類似的材料、或其組合。可透過化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋塗介電材料(spin-on-dielectric)製程、類似的製程、或其組合形成鈍 化層54。鈍化層54的厚度可介於大約0.5微米至大約30微米的範圍內。在一些實施例中，導電墊52的頂表面與鈍化層54的底表面的一部分為同水平的(即，共平面)。
一開口穿過鈍化層54，以露出導電墊52的一部分。可透過例如蝕刻製程、銑削(milling)製程、雷射技術、類似的製程、或其組合形成上述開口。
第2圖繪示出一晶種層56形成於基底50、鈍化層54及導電墊52上方。晶種層56直接接觸鈍化層54的開口內的導電墊52的頂表面。在一些實施例中，晶種層56為一金屬層，其可為單層或複合層，複合層包括不同材料的複數子層。晶種層56可由銅、鈦、鎳、金、類似的材料、或其組合所構成。在一些實施例中，晶種層56包括一鈦層及位於鈦層上的一銅層。可使用例如物理氣相沉積製程或類似的方法形成晶種層56。
第3圖繪示出一光阻58形成於晶種層56上方並圖案化。在一些實施例中，光阻58形成於晶種層56上方並圖案化，然後導電特徵62及64形成於圖案化的光阻58內(可參見第4圖)。可透過濕式製程(例如，旋塗製程)或乾式製程(例如，塗佈乾膜)來形成光阻58。複數開口60可形成於光阻58內，以露出下方的晶種層56。開口60A形成於導電墊52上，而開口60B形成於鈍化層54上。
第4圖繪示出導電特徵62及64分別形成於開口60A及60B內。第4圖所示的導電特徵62及64分別具有凸形的頂表面62A及64A。在另一實施例中，導電特徵62的頂表面62A及導電特徵64的頂表面64A可能為大致上平坦的(未繪示)或為凹形的 (未繪示)。可透過用來形成導電特徵62及64的製程之參數來控制導電特徵62的頂表面62A及導電特徵64的頂表面64A之形狀/輪廓。另外，透過控制製程參數，可以取決於導電特徵62及導電特徵64的尺寸(例如，導電特徵的直徑或導電特徵的頂表面面積)不同而使得導電特徵62及導電特徵64具有不同的形成速率。形成速率的差異能夠使得在同一形成步驟中所形成的導電特徵62及導電特徵64具有高度的差異(例如，高度H1與高度H2)。
在一些實施例中，透過鍍膜製程(例如，電鍍製程、無電鍍製程或類似的製程)來形成導電特徵62及64。導電特徵62及64可由例如銅、鋁、鎳、金、銀、鈀、錫、類似的材料、或其組合所構成，且可具有包括複數膜層的複合結構。在一些實施例中，導電特徵62的直徑D1大於大約40微米。在一實施例中，直徑D1介於大約40微米至大約100微米的範圍內。在一些實施例中，導電特徵64的直徑D2小於大約20微米。在一實施例中，直徑D2介於大約1微米至大約20微米的範圍內。在一些實施例中，直徑D1與直徑D2的比例(D1/D2)介於大約1至大約100的範圍內。導電特徵62具有高度H1，且導電特徵64具有高度H2。在一些實施例中，高度H1比高度H2大至少50%。例如，如果導電特徵64的高度H2為大約20微米，則導電特徵62的高度H1為至少大約30微米。
在一些實施例中，可基於導電特徵的結構，在鍍膜溶液中加入化學添加劑，例如加速劑(accelerator)、抑制劑(suppressor)以及平整劑(leveler)。
在透過電鍍製程形成導電特徵62及64的實施例中，可藉由改變電鍍製程的參數(例如，電流密度、電鍍液、電鍍液的溫度、電鍍時間、電鍍工具腔室的流動(plating tool chamber flow)、光阻58的高度或其組合)，達成導電特徵62的高度H1與導電特徵64的高度H2之間的差異。舉例來說，在較低的電流密度(例如，10mA/cm2及以下)的情況下，電鍍液與光阻58之間的流體摩擦對電鍍製程的鍍膜速率影響很大。流體摩擦減慢及/或抑制(demobilize)接近光阻58的電鍍源離子，光阻58內的較窄開口(其用於形成導電特徵64)使得電鍍源離子可到達較窄開口之中的陰極(例如，晶種層56及導電特徵64)之數量顯著地降低。類似地，流體摩擦減慢及/或抑制接近光阻58內的較寬開口(其用於形成導電特徵62)的電鍍源離子，然而較寬開口具有不會受到流體摩擦所影響的較大面積(例如，開口的中間部分)，使得電鍍源離子可較快速且較容易地到達導電特徵62。另外，在電鍍製程期間，梯度離子濃度的區域(有時稱為擴散層)形成於導電特徵(導電特徵62及64)附近，且用於形成導電特徵62的較寬開口內的擴散層比較薄，其能夠引發電流擁擠效應(current crowding effect)。再者，由於流體摩擦及/或加速劑的添加，導電特徵62及64的中間部分比邊緣部分鍍膜較快，因此產生凸形的頂表面62A及64A。由此可知，在較低的電流密度的情況下，導電特徵62的鍍膜速率比導電特徵64的鍍膜速率更快，因此在相同的時間量(例如，相同的製程時間)內，導電特徵62的高度大於導電特徵64的高度。再者，在較高的電流密度(例如，20mA/cm2及以下)的情況下，電鍍製程的磁場 對電鍍製程的鍍膜速率影響很大，使得較小的導電特徵可能由於接近光阻58的電流擁擠效應而鍍膜較快。
第5圖繪示出在去除光阻58及導電特徵62及64之外的晶種層56之後的導電特徵62及64。可透過適合的去除方法(例如，灰化(ashing)製程、蝕刻製程、類似的製程、或其組合)移除光阻58及晶種層56。
為了清楚及簡化的目的，僅繪示出晶粒100內的一個導電特徵62及兩個導電特徵64，所屬技術領域中具有通常知識者可輕易地理解晶粒100內可存在一個以上的導電特徵62，且可存在更多或兩個以下的導電特徵64。
第6圖繪示出在積體電路晶粒100的主動側上形成一介電材料層70，例如形成於鈍化層54、導電特徵62及導電特徵64上方。介電材料層70可密封(encapsulate)導電特徵62且橫向地密封導電特徵64。在一些實施例中，介電材料層70橫向地連接(coterminous)晶粒100。介電材料層70為聚合物，例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)或類似的材料。在其他實施例中，介電材料層70由氮化物(例如，氮化矽)、氧化物(例如，氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)或類似的材料)、或類似的材料所構成。可透過任何可接受的沉積製程(例如，旋轉塗佈製程、化學氣相沉積製程、層壓(laminating)製程、類似的製程、或其組合)來形成介電材料層70。
在一些實施例中，導電特徵62及64埋置於介電材 料層70中，且在介電材料層70上進行平坦化步驟(例如，研磨製程)，如第7圖所示。平坦化步驟用以移除介電材料層70的多餘部分，其中多餘部分是位於導電特徵62的頂表面62A上方。在一些實施例中，導電特徵62的頂表面62A露出及平坦化，並且與介電材料層70的頂表面70A同水平。在這些實施例中，導電特徵62被平坦化而具有高度H3。即使高度H3可能小於高度H1(在平坦化步驟之前導電特徵62的高度)，在平坦化步驟之後導電特徵62的高度H3仍大於導電特徵64的高度H2。高度H3與高度H2之間的差異足以將導電特徵64與形成於介電材料層70的頂表面70A上的另一導電特徵(例如，導電特徵80)隔離。如第7圖所示，導電特徵62延伸到介電材料層70的頂表面70A。導電特徵62可作為連接到次一層導電層(可參見第9圖中的導電特徵78及80)的通孔電極，且以下可將其稱為通孔電極62。再者，導電特徵64嵌入介電材料層70內，且與次一層導電層(可參見第9圖中的導電特徵78及80)隔離(電性隔離)。導電特徵64可作為導電線，且以下可將其稱為導電線64。導電特徵62也可稱為導電柱或微凸塊(microbump)。
在平坦化步驟之後，通孔電極62及導電線64位於晶粒100的內連線結構的同一導電層內，通孔電極62具有平坦的頂表面，而導電線64具有非平坦(凸形)的頂表面。
第8圖繪示出形成一晶種層72，且將一光阻74形成於介電材料層70、通孔電極62及導電線64上並圖案化。晶種層72直接接觸通孔電極62。在一些實施例中，晶種層72為一金屬層，其可為單層或複合層，複合層包括不同材料的複數子層。 晶種層72可由銅、鈦、鎳、金、類似的材料、或其組合所構成。在一些實施例中，晶種層72包括一鈦層及位於鈦層上的一銅層。可使用例如物理氣相沉積製程或類似的方法形成晶種層72。
在一些實施例中，光阻74形成於晶種層72上並圖案化，之後將導電特徵78及80(可參見第9圖)形成於圖案化的光阻74內。可透過濕式製程(例如，旋塗製程)或乾式製程(例如，塗佈乾膜)來形成光阻74。複數開口76可形成於光阻74內，以露出下方的晶種層72。開口76A形成於通孔電極62上，而開口76B形成於介電材料層70上。在一些實施例中，開口76B可省略。
第9圖繪示出形成導電特徵78及80，且去除光阻74及導電特徵78及80之外的晶種層72。在一些實施例中，可透過化學氣相沉積製程、原子層沉積製程、物理氣相沉積製程、濺鍍製程、類似的製程、或鍍膜製程(例如，電鍍製程、無電鍍製程或類似的製程)形成導電特徵78及80。導電特徵78及80可由金屬所構成，例如銅、鋁、鎳、金、銀、鈀、錫、類似的材料、或其組合，且可具有包括複數膜層的複合結構。在一些實施例中，導電特徵78及80的形成方法類似於導電特徵62及64的形成方法，使得導電特徵78的高度比導電特徵80的高度高至少50%。在一些實施例中，導電特徵78及80具有相同的高度，或經平坦化而具有相同的高度。
雖然未繪示於圖式中，可在導電特徵78及80上方形成另一介電材料層(類似於介電材料層70)，且後續可形成另一層的導電特徵。上述製程步驟可根據晶粒100的設計所需而 重複進行多次。
透過控制電鍍製程使得不同尺寸的導電特徵具有不同的鍍膜速率，能夠實現在同一電鍍步驟中所形成的導電特徵具有高度差異。導電特徵的高度差異容許較大的導電特徵例如作為通孔電極(via)來連接內連線結構的次一層，而較小的導電特徵可為目前的內連線層內的導電線/結構。由於導電通孔電極及導電線皆在同一製程中同時形成，因此減少了圖案化步驟的次數及鈍化層/介電層的數量。圖案化步驟的次數及鈍化層/介電層的數量之減少可進一步降低晶粒上的應力及翹曲，原因在於許多鈍化層/介電層需要進行固化的步驟而在晶粒上造成應力及翹曲的緣故。
第10至13圖係繪示出根據某些實施例之半導體裝置的製造及測試過程期間的中間步驟的剖面示意圖。第10圖繪示出製造過程期間的中間步驟的晶粒100，其類似於第5圖所示的步驟。關於此實施例的細節類似於先前的實施例所述，此處不再重複說明。
在第10圖的實施例中，通孔電極62的頂表面62A上及導電線64的頂表面64A上具有一金屬蓋層90。金屬蓋層90可包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似的材料、或其組合，且可透過電鍍製程來形成。在一些實施例中，用以形成金屬蓋層90的電鍍製程之製程時間小於用以形成導電特徵62及64的電鍍製程之製程時間。在一實施例中，用以形成金屬蓋層90的電鍍製程之製程時間小於100秒，例如介於大約30秒至大約75秒的範圍內。金屬蓋層90的頂表面90A順 應性地形成於通孔電極62的頂表面62A上及導電線64的頂表面64A上。在一些實施例中，金屬蓋層90具有凸形的頂表面90A。在一實施例中，金屬蓋層90的材料組成不同於通孔電極62的材料組成。在一實施例中，金屬蓋層90的材料組成不同於導電線64的材料組成。
第11A及11B圖繪示出在製造過程期間使用具有接觸探針(probe contact)96的測試結構94對晶粒100進行測試。測試步驟可與晶粒100的形成步驟原位(in-situ)進行，且可容許晶粒100的產率得以監測。金屬蓋層90容許測試結構94的接觸探針96具有平坦的端部96A(而並非尖銳的端部)，其不會對導電特徵62及/或金屬蓋層90造成損傷。金屬蓋層90也容許通孔電極62與接觸探針96之間快速及可靠的連接。在一些實施例中，金屬蓋層90未氧化，其容許接觸探針96與通孔電極62之間的更加可靠的接觸。相較於用於鋁墊之尖銳的接觸探針，具有平坦端部的接觸探針96容許對具有金屬蓋層90的通孔電極62之測試速率(晶圓/每小時)增加大約7至8倍。
第12圖繪示出在積體電路晶粒100的主動側上形成介電材料層70，例如形成於鈍化層54、導電特徵62、導電特徵64及金屬蓋層90上方。介電材料層70可密封導電特徵62、導電特徵64及金屬蓋層90。在一些實施例中，介電材料層70與晶粒100橫向地相接。介電材料層70為聚合物，例如聚苯並噁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)或類似的材料。在其他實施例中，介電材料層70由氮化物(例如，氮化矽)、氧化物(例如，氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷 矽酸鹽玻璃(BPSG)或類似的材料)、或類似的材料所構成。可透過任何可接受的沉積製程(例如，旋轉塗佈製程、化學氣相沉積製程、層壓製程、類似的製程、或其組合)來形成介電材料層70。
在一些實施例中，導電特徵62、導電特徵64及金屬蓋層90埋置於介電材料層70中，且在介電材料層70上進行平坦化步驟(例如，研磨製程)，如第13圖所示。平坦化步驟用以移除介電材料層70的多餘部分，其中多餘部分是位於導電特徵62的頂表面62A上方。在一些實施例中，至少一部分的金屬蓋層90保留於導電特徵62上，且經平坦化而具有平坦的頂表面，此平坦的頂表面與介電材料層70的頂表面70A同水平。
在平坦化步驟之後，可形成晶種層72以及導電特徵78及80。這些結構的形成如上述所說明，此處不再重複描述。
通孔電極62上方具有金屬蓋層90，使得接觸探針96的端部可以為平坦的(而並非尖銳的端部)，進而不會損壞導電特徵62及/或金屬蓋層90。再者，相較於對鋁墊使用尖銳的接觸探針，對具有金屬蓋層90的通孔電極62使用具有平坦端部的接觸探針96，能夠容許測試速率(晶圓/每小時)增加大約7至8倍。
第14、15及16圖係繪示出根據某些實施例之半導體裝置的剖面示意圖。第14圖的實施例類似於第13圖的實施例，差異在於第14圖的實施例中導電特徵62上的金屬蓋層90大致上完全去除，使得導電特徵62的頂表面62A露出及平坦化，並且與介電材料層70的頂表面70A同水平。
第15圖的實施例類似於上述第13圖的實施例，差異在於第15圖的實施例中金屬蓋層90延伸到通孔電極62及導電線64的側壁。關於此實施例的細節類似於先前的實施例所述，此處不再重複說明。
第15圖中的金屬蓋層90的形成方法類似於第13圖中的金屬蓋層90的形成方法，差異在於用以形成第15圖中的金屬蓋層90的電鍍製程進行的時間長於第13圖的實施例，以允許金屬蓋層90形成於通孔電極62及導電線64的側壁上。
第16圖的實施例類似於第15圖的實施例，差異在於第16圖的實施例中導電特徵62的頂表面62A上的金屬蓋層90大致上完全去除，使得導電特徵62的頂表面62A露出及平坦化，並且與介電材料層70的頂表面70A同水平。在進行平坦化步驟之後，通孔電極62僅有側壁上具有金屬蓋層90，而導電線64的頂表面64A及側壁上皆具有金屬蓋層90。
第17至24圖係繪示出根據某些實施例之堆疊式封裝(PoP)結構的製造過程期間的中間步驟的剖面示意圖。第17圖繪示出一個(或多個)第一封裝體300於製造過程的中間步驟，其包括一承載基底200、位於承載基底200上方的一黏著層202以及位於黏著層202上方的一介電層204。承載基底200可為任何適合的基底，其用以(在製造過程的中間步驟期間)為承載基底200上方的膜層提供機械支撐。承載基底200可為一晶圓，其包括玻璃、矽(例如，矽晶圓)、氧化矽、金屬板、陶瓷材料、或類似的材料。
黏著層202可設置於(例如層疊於)承載基底200 上。黏著層202可由黏著膠(例如，紫外線(ultra-violet，UV)膠材，其暴露於紫外光時會失去黏著性)、光熱轉換(light-to-heat conversion，LTHC)材料(其加熱時會失去黏著性)、或類似的材料所構成。黏著層202可透過以液體塗佈並固化而形成，也可為層壓於承載基底200上的層壓膜，或透過類似的方式形成。黏著層202的頂表面可為經平整的，且可具有高程度的共面性(coplanarity)。
介電層204形成於黏著層202上。介電層204可為氮化矽、碳化矽、氧化矽、低介電常數材料(例如，碳摻雜氧化物)、極低介電常數材料(例如，多孔碳摻雜二氧化矽)、聚合物(例如，環氧樹脂)、聚醯亞胺、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、類似的材料、或其組合，也可使用其他相對較軟且通常為有機的介電材料。可透過化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋塗介電材料製程、類似的製程、或其組合形成介電層204。
在一些實施例中，介電層204可為背側重佈線結構(back side redistribution structure)204。背側重佈線結構204可由交替的介電材料層(例如，低介電常數材料)及導電材料層(例如，銅)所構成，且可透過任何適合的方法(例如，沉積製程、鑲嵌製程、雙鑲嵌製程等)來形成。導電層及介電層可包括金屬線及介層窗(未繪示)。
再者，在第17圖中，電性連接結構208可形成於一晶種層(未繪示)上，且以大致上垂直於介電層204的表面的方向從晶種層延伸。在一些實施例中，透過電鍍製程形成電性連接 結構208。在這些實施例中，電性連接結構208由銅、鋁、鎳、金、銀、鈀、錫、類似的材料、或其組合所構成，且可具有包括複數膜層的複合結構。在這些實施例中，一光阻(未繪示)可形成於承載基底200上。在一些實施例中，光阻形成於晶種層上並圖案化，然後在圖案化的光阻內形成電性連接結構208。可透過濕式製程(例如，旋塗製程)或乾式製程(例如，塗佈乾膜)來形成光阻。複數開口可形成於光阻內，以露出下方的晶種層。之後，進行電鍍製程以鍍膜出電性連接結構208。
在替代實施例中，電性連接結構208可為柱形凸塊(stud bumps)，其透過打線接合(wire bonding)技術形成於介電層204上，並切斷接合線而保留接合線的一部分連接到對應的接合球。舉例來說，電性連接結構208可包括一下部及一上部，其中下部可為打線接合技術中所形成的一接合球(未繪示)，且上部可為剩餘的接合線(未繪示)。電性連接結構208的上部可具有均勻的寬度及均勻的形狀，其包括上部的整個頂部部分、中間部分及底部部分皆為均勻的。電性連接結構208可由非焊料金屬材料所構成，其可透過打線接合機來接合。在一些實施例中，電性連接結構208由銅導線、金線、類似的材料、或其組合所構成，且可具有包括複數膜層的複合結構。在打線接合的實施例中，晶種層及犧牲層可被省略。
再者，在第17圖中，積體電路晶粒100透過一黏著層206而黏著至介電層204。在黏著至介電層204之前，可根據適用的製程對積體電路晶粒100進行處理，以在積體電路晶粒100內形成積體電路(可參見第1至16圖)。黏著層206可為任何適 合的黏著劑，例如晶粒附著膜(die attach film)或類似的黏著劑。晶粒100可為單一晶粒，或者可為兩個以上的晶粒。晶粒100可包括一邏輯晶粒，例如中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、類似的元件、或其組合。在一些實施例中，晶粒100包括堆疊晶粒(未繪示)，其可包括邏輯晶粒及記憶體晶粒。晶粒100可包括輸入/輸出(input/output，I/O)晶粒，例如寬輸入/輸出晶粒，其提供了第一封裝體300及後續貼附的第二封裝體240(可參見第23及24圖)之間的連接。晶粒100可包括通孔電極62及導電線64，通孔電極62及導電線64是利用第1至16圖所述之鍍膜高度差異化方法所形成的。
晶粒100的通孔電極62可作為晶粒100的導電墊。為了簡化，僅繪示出晶粒100的單一內連接層，可以理解的是晶粒100內可存在一層以上的內連接層。
第18圖繪示出密封晶粒100及電性連接結構208。在一些實施例中，透過一模塑成型材料210來橫向地密封晶粒100及電性連接結構208。模塑成型材料210可模塑於晶粒100及電性連接結構208上，例如利用壓縮模塑成型(compression molding)技術。在一些實施例中，模塑成型材料210由模塑成型化合物、聚合物、環氧樹脂、氧化矽填充材料、類似的材料、或其組合所構成。可進行固化製程將模塑成型材料210固化，其中固化製程可為熱固化製程、紫外線固化製程、類似的製程、或其組合。
在一些實施例中，晶粒100、通孔電極62及電性連 接結構208埋設於模塑成型材料210內，且在固化模塑成型材料210之後，在模塑成型材料210上進行平坦化步驟(例如，研磨製程)，如第18圖所示。平坦化步驟用以移除模塑成型材料210的多餘部分，其中多餘部分是位於通孔電極62及電性連接結構208的頂表面上方。在一些實施例中，通孔電極62的頂表面及電性連接結構208的頂表面露出，並且與模塑成型材料210的頂表面同水平。電性連接結構208可稱為模塑成型通孔電極(through molding via，TMV)、封裝體通孔電極(through package via，TPV)、及/或整合扇出型通孔電極(through integrated fan-out(InFO)via，TIV)，以下可將其稱為整合扇出型通孔電極208。
第19圖繪示出在晶粒100、整合扇出型通孔電極208及模塑成型材料210上形成一重佈線層216及複數導電連接結構218。重佈線層216可包括一層或多層金屬層，有時可稱為M1及/或MN，其中金屬層M1緊鄰與晶粒100，而金屬層MN是距離晶粒100最遠的金屬層(有時可稱為頂部金屬層MN)。在說明書中，“金屬層”的用語是指與金屬線212同一層中的所有金屬層。重佈線層216可包括一層或多層鈍化層214，其中一層或多層金屬層(M1至MN)設置於一層或多層鈍化層214內。
鈍化層214可為氮化矽、碳化矽、氧化矽、低介電常數材料(例如，碳摻雜氧化物)、極低介電常數材料(例如，多孔碳摻雜二氧化矽)、聚合物(例如，環氧樹脂)、聚醯亞胺、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、防焊漆(SR)、類似的材料、或其組合，也可使用其他相對較軟且通常為有機的介電材料。 可透過化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、旋塗介電材料製程、層壓製程、類似的製程、或其組合形成鈍化層214。可對鈍化層214進行固化製程而將鈍化層214固化，其中固化製程可為熱固化製程、紫外線固化製程、類似的製程、或其組合。
可使用單鑲嵌製程及/或雙鑲嵌製程、先鑽孔(via-first)製程或先金屬(rmetal-first)製程來形成金屬線212。金屬線212的金屬層及通孔電極由導電材料所構成，例如銅、鋁、鈦、類似的材料、或其組合，且可具有或不具有阻障層(barrier layer)。
在作為範例的一實施例中，使用雙鑲嵌製程形成金屬線212。在此範例中，形成金屬層M1的步驟包括先在最下層的鈍化層214上形成一蝕刻終止層(未繪示)，然後在蝕刻終止層上形成次一層的鈍化層214。沉積次一層的鈍化層214之後，次一層的鈍化層214的一部份被蝕刻去除而形成凹陷特徵，例如溝槽及導通孔，其可以填充導電材料來連接不同區域的重佈線層216，並容納金屬線212及通孔電極。可重複進行上述步驟來形成剩餘的金屬層至金屬層MN。
重佈線層216可稱為第一封裝體300的前側重佈線結構(可參見第23及24圖)。可使用前側重佈線結構216而經由導電連接結構218將第一封裝體300耦接至一個或一個以上的封裝體、封裝基底、元件、類似的部件或其組合(可參見第24圖)。
金屬線212的數量及鈍化層214的數量僅用於說明的目的，而非限定於此。可以有其他數量的金屬層，其多於或 少於所繪示的一層。可以有其他數量的鈍化層，其不同於第19圖所繪示的鈍化層的數量。
第19圖還繪示出在重佈線層216上方形成一組導電連接結構218，其電性耦接至重佈線層216。導電連接結構218可為焊料凸塊、金屬柱、可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold，ENEPIG)技術所形成的凸塊、或類似的結構。導電連接結構218可包括導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似的材料、或其組合。在一實施例中，導電連接結構218為焊料凸塊，且導電連接結構218的形成步驟包括透過常用的方法例如蒸鍍製程、電鍍製程、印刷製程、焊料轉印(solder transfer)技術、植球(ball placement)技術、或類似的方法，初步形成一層焊料層。形成焊料層之後，可進行回流(reflow)製程，以將材料塑型成所需的凸塊形狀。在另一實施例中，導電連接結構218為金屬柱(例如，銅柱)，且透過濺鍍製程、印刷製程、電鍍製程、無電鍍製程、化學氣相沉積製程、或類似的方法所形成。金屬柱可不含有焊料，且具有大致上垂直的側壁。在一些實施例中，一金屬蓋層(未繪示)形成於為金屬柱之導電連接結構218的頂部上。金屬蓋層可包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似的材料、或其組合，且可透過電鍍製程來形成。
雖然未繪示於圖式中，可能有凸塊底層金屬(Under-Bump Metallization，UBM，未繪示)耦接至重佈線層 216，且導電連接結構218耦接至凸塊底層金屬。凸塊底層金屬的形成步驟可包括先形成一組開口(未繪示)，其穿透過最上層的鈍化層214，以露出在金屬層MN內的金屬線212的表面。凸塊底層金屬可延伸穿過鈍化層214內的這些開口，且更沿著鈍化層214的表面延伸。凸塊底層金屬可包括三層導電材料，例如一層鈦層、一層銅層及一層鎳層。然而，所屬技術領域中具有通常知識者可以理解，上述材料及膜層有許多適合的配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或銅/鎳/金的配置，上述配置皆適合用來形成凸塊底層金屬。任何適合用來形成凸塊底層金屬的材料或材料層完全涵蓋於本發明之範圍內。
第20A圖繪示出根據一實施例去除承載基底200及黏著層202，以露出介電層204。在本實施例中，第一封裝體300放置於一框架220上，導電連接結構218鄰接框架220，而承載基底200及黏著層202被去除。
第20B圖繪示出根據另一實施例去除承載基底200及黏著層202，以露出介電層204。在本實施例中，第一封裝體300放置於一第二承載基底222上，導電連接結構218鄰接第二承載基底222，而承載基底200及黏著層202被去除。在此實施例中，一可剝離膠224位於第二承載基底222上，且導電連接結構218嵌入可剝離膠224內。可剝離膠224可有助於將第一封裝體300固定至第二承載基底222。在去除承載基底200之後，可透過剝離(peel-off)技術(例如，加熱製程、化學剝除製程、雷射去除製程、紫外線處理、類似的方法、或其組合)去除可剝 離膠224。
在第21圖中，開口230穿過介電層204的至少一部分，以局部露出在背側重佈線結構204內的導電特徵及/或整合扇出型通孔電極208。舉例來說，可使用雷射鑽孔製程、蝕刻製程、或類似的製程形成開口230。
在第22圖中，使用導電連接結構242將第二封裝體240貼附至背側重佈線結構204及/或整合扇出型通孔電極208。第二封裝體240可為任何封裝部件及/或包括任何封裝部件。舉例來說，如第22圖所示，每一個第二封裝體240包括一基底、位於基底上的兩個堆疊的積體電路晶粒、將積體電路晶粒電性耦接至基底的焊線、以及密封堆疊的積體電路晶粒及焊線之密封層。在一範例中，第二封裝體240的積體電路晶粒為記憶體晶粒，例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒。透過導電連接結構242，第二封裝體240電性耦接及機械性連接至背側重佈線結構204及/或整合扇出型通孔電極208。在一些實施例中，導電連接結構242可為焊料凸塊、金屬柱、可控塌陷晶片連接(C4)凸塊、微凸塊、無電鍍鎳鈀浸金(ENEPIG)技術所形成的凸塊、或類似的結構。在一些實施例中，可對導電連接結構242進行回流製程，以將第二封裝體240貼附至第一封裝體300。第二封裝體240的積體電路晶粒電性連通及耦接至積體電路晶粒100，例如透過第二封裝體240內的焊線及基底、導電連接結構242、背側重佈線結構204、整合扇出型通孔電極208及前側重佈線結構216。
再者，在第22圖中，使用切割工具244(例如，刀具) 沿著第二封裝體240之間的切割道區域進行單體化製程。切割工具244將第一封裝體300單體化為多個獨立的第一封裝體300。第23圖繪示出單體化後所得到的堆疊式封裝結構。經過單體化得到的第一封裝體300可為第22圖中被單體化的多個第一封裝體300的任一者。如第23圖所示，第二封裝體240貼附至第一封裝體300的背側重佈線結構204。
在第24圖中，堆疊式封裝結構貼附至一基底302。外部的導電連接結構218電性耦接及機械性連接至基底302上的複數導電墊304。舉例來說，基底302可為印刷電路板(printed circuit board，PCB)或類似的部件。
透過控制電鍍製程使得不同尺寸的導電特徵具有不同的鍍膜速率，能夠實現在同一電鍍步驟中形成具有高度差異的導電特徵。導電特徵的高度差異容許較大的導電特徵例如作為通孔電極來連接內連線結構的次一層，而較小的導電特徵可為目前的內連線層內的導電線/結構。由於導電通孔電極及導電線皆在同一製程中同時形成，因此減少了圖案化步驟的次數及鈍化層/介電層。由於許多鈍化層/介電層需要進行固化的步驟而會在晶粒上造成應力及翹曲，因此圖案化步驟的次數及鈍化層/介電層之減少可進一步降低晶粒上的應力及翹曲。另外，通孔電極上方具有金屬蓋層，使得接觸探針的端部可設計為平坦的(而並非尖銳的端部)，進而不會損壞導電特徵及/或金屬蓋層。再者，相較於對鋁墊使用尖銳的接觸探針，對具有金屬蓋層的通孔電極使用具有平坦端部的接觸探針，能夠容許測試速率(晶圓/每小時)增加大約7至8倍。
配合本發明一實施例，一種裝置包括一導電墊，位於一基底上。一鈍化層位於基底上，且覆蓋導電墊的至少一部分。一第一導電特徵位於導電墊上，且具有一平坦的頂表面。第一導電特徵具有一第一高度，第一高度係從導電墊測量至第一導電特徵的平坦的頂表面。一第二導電特徵位於鈍化層上，且具有一非平坦的頂表面。第二導電特徵具有一第二高度，第二高度係從鈍化層測量至第二導電特徵的非平坦的頂表面。
配合本發明另一實施例，一種裝置包括一導電墊，位於一基底上。一鈍化層順應性地位於基底上，且覆蓋導電墊的至少一部分。一通孔電極位於導電墊上，且具有一第一高度，第一高度係從導電墊測量至通孔電極的一頂表面。一導電線位於鈍化層上，且具有一第二高度，第二高度係從鈍化層測量至導電線的一頂表面，且第一高度大於第二高度。一介電材料層位於鈍化層上，且具有一頂表面與通孔電極的頂表面共平面。介電材料層密封導電線。
配合本發明又另一實施例，一種方法包括進行一第一形成步驟，以在一基底上形成具有一第一高度的一第一導電特徵以及具有一第二高度的一第二導電特徵。第一高度係從第一導電特徵的一底表面測量至第一導電特徵的一頂表面。第二高度係從第二導電特徵的一底表面測量至第二導電特徵的一頂表面，且第一高度大於第二高度。利用一介電材料層密封第一導電特徵的複數側壁以及第二導電特徵的頂表面及複數側壁。第一導電特徵的頂表面與介電材料層的一頂表面共平 面。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本發明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其他結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神及保護範圍內，且可在不脫離本發明之精神及範圍內，當可作更動、替代與潤飾。

Claims (8)

  1. 一種半導體裝置，包括：一導電墊，位於一基底上；一鈍化層，位於該基底上，且覆蓋該導電墊的至少一部分；一第一導電特徵，位於該導電墊上，且具有一平坦的頂表面，其中該第一導電特徵具有一第一高度，該第一高度係從該導電墊測量至該第一導電特徵的該平坦的頂表面；一第二導電特徵，位於該鈍化層上，且具有一非平坦的頂表面，其中該第二導電特徵具有一第二高度，該第二高度係從該鈍化層測量至該第二導電特徵的該非平坦的頂表面；以及一介電材料層，位於該鈍化層上，其中該第一導電特徵與該第二導電特徵由該介電材料層分隔。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一高度大於該第二高度，且其中該第一導電特徵的一直徑大於該第二導電特徵的一直徑，且該第一導電特徵的該直徑及該第二導電特徵的該直徑係從一平面所測量，該平面平行於該基底的一主表面。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該介電材料層橫向地密封該第一導電特徵，且密封該第二導電特徵，該介電材料層的一頂表面與該第一導電特徵的該平坦的頂表面共平面。
  4. 如申請專利範圍第3項所述之半導體裝置，更包括：一第一金屬蓋層，位於該第一導電特徵上，其中該第一金屬蓋層的至少一部分與該介電材料層的該頂表面共平面，該第一金屬蓋層的材料組成不同於該第一導電特徵的材料組成；以及一第二金屬蓋層，位於該第二導電特徵上，其中該第二金屬蓋層的材料組成不同於該第二導電特徵的材料組成。
  5. 一種半導體裝置，包括：一導電墊，位於一基底上；一鈍化層，順應性地位於該基底上，且覆蓋該導電墊的至少一部分；一通孔電極，位於該導電墊上，且具有一第一高度，該第一高度係從該導電墊測量至該通孔電極的一頂表面；一導電線，位於該鈍化層上，且具有一第二高度，該第二高度係從該鈍化層測量至該導電線的一頂表面，且該第一高度大於該第二高度，其中該通孔電極的該頂表面為平坦的，且該導電線的該頂表面為非平坦的；以及一介電材料層，位於該鈍化層上，且具有一頂表面與該通孔電極的該頂表面共平面，其中該通孔電極與該導電線由該介電材料層分隔，且該介電材料層密封該導電線。
  6. 如申請專利範圍第5項所述之半導體裝置，其中該通孔電極的一直徑大於該導電線的一直徑，且該通孔電極的該直徑及該導電線的該直徑係從一平面所測量，該平面平行於該基底的一主表面。
  7. 一種半導體裝置的製造方法，包括：進行一第一形成步驟，以在一基底上形成具有一第一高度的一第一導電特徵以及具有一第二高度的一第二導電特徵，其中該第一高度係從該第一導電特徵的一底表面測量至該第一導電特徵的一頂表面，且該第二高度係從該第二導電特徵的一底表面測量至該第二導電特徵的一頂表面，且其中該第一高度大於該第二高度；利用一介電材料層密封該第一導電特徵的複數側壁以及該第二導電特徵的該頂表面及複數側壁，其中該第一導電特徵的該頂表面與該介電材料層的一頂表面共平面，且該第一導電特徵與該第二導電特徵由該介電材料層分隔；在該介電材料層及該第一導電特徵上形成一第三導電特徵，其中該第三導電特徵接觸該第一導電特徵；以及在該介電材料層的該頂表面上形成一第四導電特徵，其中該第四導電特徵與該第三導電特徵位於相同層位，該第四導電特徵的至少一部分與該第二導電特徵重疊，且該第四導電特徵與該第二導電特徵電性隔離。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該第一導電特徵的一直徑大於該第二導電特徵的一直徑，且該第一導電特徵的該直徑及該第二導電特徵的該直徑係從一平面所測量，該平面平行於該基底的一主表面。
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