CN115513274A - 避免翘曲的半导体结构及其制作方法 - Google Patents

避免翘曲的半导体结构及其制作方法 Download PDF

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CN115513274A
CN115513274A CN202110630599.7A CN202110630599A CN115513274A CN 115513274 A CN115513274 A CN 115513274A CN 202110630599 A CN202110630599 A CN 202110630599A CN 115513274 A CN115513274 A CN 115513274A
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tensile stress
wafer
bend
warpage
semiconductor structure
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林大钧
杨晋嘉
侯泰成
蔡馥郁
蔡滨祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US17/369,936 priority patent/US12014995B2/en
Publication of CN115513274A publication Critical patent/CN115513274A/zh
Priority to US18/660,179 priority patent/US20240290731A1/en
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Abstract

本发明公开一种避免翘曲的半导体结构及其制作方法，其中该避免翘曲的半导体结构包含一晶片，晶片包含一正面和一背面，多个半导体元件设置在正面，一层氧化硅层设置在背面以及一紫外光可穿透氮化硅层覆盖并接触氧化硅层，其中紫外光可穿透氮化硅层的折射率介于1.55至2.10之间。

Description

避免翘曲的半导体结构及其制作方法
技术领域
本发明涉及一种避免翘曲(warpage)的半导体结构及其制作方法，特别是涉及一种利用氧化物来避免翘曲的半导体结构及其制作方法。
背景技术
一般而言，半导体元件的制作包含在半导体晶片上形成多层材料层后图案化这些材料层来制造半导体元件。当在半导体晶片的表面上形成材料层时，各层材料层会对晶片施加不同的伸张应力或压缩应力，视不同的元件设计可以在半导体晶片的正面和背面形成不同的材料层，或者是相同的材料层但厚度不同，如此就会造成正面和背面上的应力不平衡。
然而，当在半导体晶片的正面和背面上的应力不平衡时，可能会发生半导体晶片的翘曲，也就是半导体晶片往正面或背面弯曲。另外，由于各层的材料层本身热膨胀系数不同，在经历的温度变化也可能造成正面和背面上的应力不同导致翘曲。
当翘曲超过一定的幅度，在后续要进行晶片对晶片接合，或是在晶片上堆迭芯片时就会发生问题。
发明内容
有鉴于此，本发明提供一种避免翘曲的半导体结构以解决上述问题。
根据本发明的一优选实施例，一种避免翘曲的半导体结构，包含一晶片包含一正面和一背面，多个半导体元件设置在正面，一层氧化硅层设置在背面以及一紫外光可穿透(UV-transparent)氮化硅层覆盖并接触氧化硅层，其中紫外光可穿透氮化硅层的折射率介于1.55至2.10之间。
根据本发明的另一优选实施例，一种避免翘曲的半导体结构包含一晶片包含一正面和一背面，多个金属线路设置在正面，一层应力层设置在背面，应力层包含四乙氧基硅烷(TEOS)、碳化硅掺杂氮(SiC:N)、碳氧化硅(SiCO)或氮氧化硅(SiON)以及一氮化硅层覆盖并接触应力层。
根据本发明的又一优选实施例，一种避免翘曲的半导体结构的制作方法，包含提供一晶片包含一正面和一背面，多个半导体元件设置在正面，接着形成一层氧化硅层设置在背面，之后形成一氮化硅层覆盖并接触氧化硅层，最后进行一紫外光照射制作工艺，以紫外光穿透氮化硅层以照射氧化硅层。
让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图4为本发明的第一优选实施例所绘示的一种避免翘曲的半导体结构的制作方法的示意图；
图5至图8为本发明的第二优选实施例所绘示的一种避免翘曲的半导体结构的制作方法的示意图。
主要元件符号说明
10:晶片
10a:正面
10b:背面
12:晶体管
12a:源极
12b:漏极
14:金属线路
14a:后端布线
14b:前端布线
18:应力层
20:紫外光可穿透氮化硅层
22:紫外光照射制作工艺
24a:硅穿孔
24b:硅穿孔
26a:第一输出/输入金属元件
26b:第二输出/输入金属元件
100:避免翘曲的半导体结构
200:避免翘曲的半导体结构
T1:第一伸张应力
T2:第二伸张应力
T3:第三伸张应力
T4:第四伸张应力
具体实施方式
图1至图4为根据本发明的第一优选实施例所绘示的一种避免翘曲的半导体结构的制作方法。
如图1所示，首先提供一晶片10包含一正面10a和一背面10b，正面10a和背面10b相对，晶片10可以为未切割的硅基底、硅中介板、印刷电路板或已切割完成的管芯(die)，在本实施例中以晶片10为硅基底为例。多个半导体元件设置在正面10a，多个半导体元件可以包含至少一晶体管12设置在晶片10上以及多个金属线路14设置在晶片10上，其中多个金属线路14包含后端布线(back end of line)14a和前端布线(front end of line)14b，前端布线14b和后端布线14a接触并电连接，前端布线14b和晶体管12的源极12a和漏极12b接触并电连接。除此之外，前端布线14b还可以电连接其它半导体元件，例如电容、电阻、存储器等，不限于上述的晶体管。
至此在晶片10的正面10a形成了金属线路14，而晶片10的背面10b设置较少数量的金属线路14，或是晶片10的背面完全没有任何金属线路14。因为后端布线14a通常为金属制作并且后端布线14a的金属层的总面积通常很大，所以后端布线14a的金属层会造成明显的第一伸张应力(tensile stress)T1使晶片10朝向正面10a弯曲，然而晶片10的背面10b因为设置较少数量的金属线路14或是完全没有金属线路14，就造成了晶片10的背面10b的伸张应力不足以抵消正面的第一伸张应力T1，所以此时晶片10会有朝向正面10a弯曲的倾向，若不进行任何处理，之后晶片10就会发生翘曲。
如图2所示，形成一层应力层18设置在晶片10的背面10b，应力层18提供一第四伸张应力T4使晶片10朝向背面10b弯曲，也就是说应力层18具有一第四伸张应力T4。应力层18可以为氧化硅层例如(TEOS)、碳氧化硅(SiCO)或氮氧化硅(SiON)，也可以非氧化硅层，例如碳化硅掺杂氮(SiC:N)。根据本发明的优选实施例，应力层18为四乙氧基硅烷。另外四乙氧基硅烷的制作方式较佳是利用一等离子体化学气相沉积(PECVD)制作工艺，其制作工艺压力为8托耳(torr)，温度介于300至400℃，射频等离子体源的功率为800瓦，在制作工艺中所通入的前驱物包含四乙氧基硅烷，通入的气体包含氧气和氦气。
如图3所示，形成一紫外光可穿透氮化硅层20覆盖并接触应力层18，其中紫外光可穿透氮化硅层20的折射率介于1.55至2.10之间。然后进行一紫外光照射制作工艺22，以紫外光穿透紫外光可穿透氮化硅层20后照射应力层18。根据本发明的一优选实施例，紫外光照射制作工艺22的制作工艺压力为6托耳，制作工艺温度介于300℃至400℃之间，紫外光功率为600(瓦/英寸)，通入的气体包含氧气和氦气，照射时间为10至200秒之间。如图4所示，由于紫外光照射应力层18可去除应力层18中的杂质以及让应力层18中的悬键(danglingbond)结合，因此紫外光照射制作工艺22可将应力层18的伸张应力从原本的第四伸张应力T4增加到第三伸张应力T3，第三伸张应力T3大于第四伸张应力T4。第三伸张应力T3是使晶片10朝向背面10b弯曲的应力。紫外光可穿透氮化硅层20的主要功用在于将应力层18和周围环境隔絶，避免水气进入应力层18。若是水气进入应力层18后会使得应力层18的伸张应力下降，甚至转变为压缩应力(compressive stress)，因此需要使用氮化硅层隔絶水气。紫外光照射制作工艺22主要可用来微调应力层18的伸张应力，因此可以选择性进行。在紫外光照射制作工艺22后，第三伸张应力T3和第一伸张应力T1之间的差值可让晶片10保持不翘曲。较佳地，第三伸张应力T3等于第一伸张应力T1。至此本发明的第一优选实施例中的避免翘曲的半导体结构100业已完成。
如图4所示，利用第一优选实施例所制作的一种避免翘曲的半导体结构100包含一晶片10，晶片10包含一正面10a和一背面10b，正面10a和背面10b相对，晶片10可以为未切割的硅基底、硅中介板、印刷电路板或已切割完成的管芯(die)。多个半导体元件设置在正面10，半导体元件包含至少一晶体管12和多个金属线路14设置在正面10a，一层应力层18设置在背面10b以及一紫外光可穿透氮化硅层20覆盖并接触应力层18，其中紫外光可穿透氮化硅层20的折射率介于1.55至2.10之间，折射率在前述区间的氮化硅层可以让紫外光穿透。紫外光可穿透氮化硅层20的厚度较佳小于200埃，因为厚度小于200埃可保证紫外光可穿透氮化硅层20本身不会产生足以使晶片10翘曲的压缩应力。多个金属线路14可以为多个后端布线14a，其中后端布线14a提供一第一伸张应力T1使晶片10朝向正面10a弯曲，应力层18提供一第三伸张应力T3使晶片10朝向背面10b弯曲，根据本发明的优选实施例，第一伸张应力T1等于第三伸张应力T3，如此一来造成晶片10的正面10a和背面10b的弯曲应力就会抵消，晶片10就不会翘曲。应力层18可以为氧化硅层例如(TEOS)、碳氧化硅(SiCO)或氮氧化硅(SiON)，也可以非氧化硅层，例如碳化硅掺杂氮(SiC:N)。
图5至图8为根据本发明的第二优选实施例所绘示的一种避免翘曲的半导体结构的制作方法，其中具有相同功能的元件，将使用第一优选实施例中的元件符号，并且其相关说明请参阅第一优选实施例，在第二优选实施例中不再重复说明。
如图5所示，首先提供一晶片10，晶片10包含一正面10a和一背面10b。在本实施例中晶片10较佳为硅中介板，硅中介板中包含有多个硅穿孔(through silicon via)24a，多个半导体元件设置在正面10a，多个半导体元件较佳为多个第一输出/输入金属元件26a，第一输出/输入金属元件26a提供一第一伸张应力T1使晶片10朝向正面10a弯曲。接着，形成一层应力层18设置在晶片10的背面10b，应力层18提供一第四伸张应力T4使晶片10朝向背面10b弯曲。同样地，应力层18可以包含(TEOS)、碳氧化硅(SiCO)、氮氧化硅(SiON)或碳化硅掺杂氮(SiC:N)。应力层18的示范性制作工艺方式请参阅第一优选实施例中的说明。
如图6所示，形成一紫外光可穿透氮化硅层20覆盖并接触应力层18，紫外光可穿透氮化硅层20的折射率介于1.55至2.10之间。然后进行一紫外光照射制作工艺22，紫外光穿透紫外光可穿透氮化硅层20后照射应力层18，紫外光照射制作工艺22的示范性制作工艺方式请参阅第一优选实施例中的说明。在照射完紫外光后，应力层18的伸张应力从原本的第四伸张应力T4增加到第三伸张应力T3。第三伸张应力T3使晶片10朝向背面10b弯曲。
如图8所示，完成紫外光照射制作工艺22之后，形成多个硅穿孔24b在应力层18和紫外光可穿透氮化硅层20中并且硅穿孔24b接触硅穿孔24a。之后形成多个第二输出/输入金属元件26b设置在晶片10的背面10b，详细来说第二输出/输入金属元件26b直接接触紫外光可穿透氮化硅层20并且和接触硅穿孔24b。或者也可以另外形成其它的介电层(图未示)覆盖紫外光可穿透氮化硅层20后，再形成多个硅穿孔24b在应力层18、紫外光可穿透氮化硅层20和介电层中，之后再形成第二输出/输入金属元件26b在介电层上。此时本发明的避免翘曲的半导体结构200业已完成。第二输出/输入金属元件26b提供一第二伸张应力T2使晶片10朝向背面10b弯曲，其中第二伸张应力T2小于第一伸张应力T1。第二伸张应力T2和第三伸张应力T3的总和较佳等于第一伸张应力T1。或者第二伸张应力T2和第三伸张应力T3的总和与第三伸张应力T3之间的差值小到可让晶片10保持不翘曲。
如图8所示，利用第二优选实施例所制作的避免翘曲的半导体结构200包含一晶片10，晶片10包含一正面10a和一背面10b，晶片10较佳为硅中介板，多个半导体元件设置在正面10a，一层应力层18设置在背面10b以及一紫外光可穿透氮化硅层20覆盖并接触应力层20，其中紫外光可穿透氮化硅层20的折射率介于1.55至2.10之间，折射率在前述区间的氮化硅层可以让紫外光穿透。应力层18可以包含(TEOS)、碳氧化硅(SiCO)、氮氧化硅(SiON)或碳化硅掺杂氮(SiC:N)。半导体元件较佳为多个第一输出/输入金属元件26a，例如多个导电凸块(bump)，第一输出/输入金属元件26a提供一第一伸张应力T1使晶片10朝向正面10a弯曲。除了导电凸块，半导体元件也可以为重分布层(redistribution Layer)或是其它电路元件。多个第二输出/输入金属元件26b设置在晶片10的背面10b，第二输出/输入金属元件26b可以为多个导电垫，视不同产品需求，第二输出/输入金属元件26b可以变换成重分布层或是其它电路元件。第二输出/输入金属元件26b提供一第二伸张应力T2使晶片10朝向背面10b弯曲，其中第二伸张应力T2小于第一伸张应力T1。第二伸张应力T2和第三伸张应力T3的总和较佳等于第一伸张应力T1，或是第二伸张应力T2和第三伸张应力T3的总和与第三伸张应力T3之间的差值小到可让晶片10保持不翘曲。
本发明利用在晶片的背面形成应力层以平衡晶片正面和背面的不同应力，特别是当晶片的正面和背面上的单位面积内的金属层数量差距过大时，就会造成晶片朝向正面或背面弯曲，通过在应力较小的那一面设置应力层将正面和背面的应力平衡后，就可以改善晶片翘曲的现象。此外在应力层上设置氮化硅层可以避免水氧进入应力层，以防止应力层所提供的应力因为水气影响而变化。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种避免翘曲的半导体结构，包含：
晶片，其中该晶片包含正面和背面；
多个半导体元件，设置在该正面；
一层氧化硅层，设置在该背面；以及
紫外光可穿透(UV-transparent)氮化硅层，覆盖并接触该氧化硅层，其中该紫外光可穿透氮化硅层的折射率介于1.55至2.10之间。
2.如权利要求1所述的避免翘曲的半导体结构，其中该多个半导体元件包含：
晶体管，设置在该晶片的该正面；
多个后端布线(back end of line)，设置在该晶体管上，其中该多个后端布线提供第一伸张应力使该晶片朝向该正面弯曲，该氧化硅层提供第三伸张应力使该晶片朝向该背面弯曲。
3.如权利要求2所述的避免翘曲的半导体结构，其中该第一伸张应力等于该第三伸张应力。
4.如权利要求1所述的避免翘曲的半导体结构，其中该多个半导体元件包含：
多个第一输出/输入金属元件，设置在该正面，该多个第一输出/输入金属元件提供第一伸张应力使该晶片朝向该正面弯曲。
5.如权利要求4所述的避免翘曲的半导体结构，另包含：
多个第二输出/输入金属元件，设置在该背面，该多个第二输出/输入金属元件提供第二伸张应力使该晶片朝向该背面弯曲，其中该第二伸张应力小于该第一伸张应力，其中该氧化硅层和该紫外光可穿透氮化硅层设置在该多个第二输出/输入金属元件和该背面之间，该氧化硅层提供第三伸张应力使该晶片朝向该背面弯曲。
6.如权利要求5所述的避免翘曲的半导体结构，其中该第一伸张应力等于该第二伸张应力和该第三伸张应力的总和。
7.如权利要求1所述的避免翘曲的半导体结构，其中该氧化硅层包含四乙氧基硅烷(TEOS)、碳氧化硅(SiCO)或氮氧化硅(SiON)。
8.一种避免翘曲的半导体结构，包含：
晶片，其中该晶片包含正面和背面；
多个金属线路，设置在该正面；
应力层，设置在该背面，该应力层包含四乙氧基硅烷(TEOS)、碳化硅掺杂氮(SiC:N)、碳氧化硅(SiCO)或氮氧化硅(SiON)；以及
氮化硅层，覆盖并接触该应力层。
9.如权利要求8所述的避免翘曲的半导体结构，其中该多个金属线路为多个后端布线(back end of line)，其中该多个后端布线提供第一伸张应力使该晶片朝向该正面弯曲，该应力层提供第三伸张应力使该晶片朝向该背面弯曲。
10.如权利要求9所述的避免翘曲的半导体结构，其中该第一伸张应力等于该第三伸张应力。
11.如权利要求8所述的避免翘曲的半导体结构，其中该多个金属线路包含：
多个第一输出/输入金属元件，设置在该正面，该多个第一输出/输入金属元件提供第一伸张应力使该晶片朝向该正面弯曲。
12.如权利要求11所述的避免翘曲的半导体结构，另包含：
多个第二输出/输入金属元件设置在该背面，该多个第二输出/输入金属元件提供第二伸张应力使该晶片朝向该背面弯曲，其中该第二伸张应力小于该第一伸张应力，其中该应力层设置在该多个第二输出/输入金属元件和该背面之间，该应力层提供第三伸张应力使该晶片朝向该背面弯曲。
13.如权利要求12所述的避免翘曲的半导体结构，其中该第一伸张应力等于该第二伸张应力和该第三伸张应力的总和。
14.一种避免翘曲的半导体结构的制作方法，包含：
提供晶片，该晶片包含正面和背面，多个半导体元件设置在该正面；
形成一层氧化硅层设置在该背面；
形成氮化硅层覆盖并接触该氧化硅层；以及
进行紫外光照射制作工艺，以紫外光穿透该氮化硅层以照射该氧化硅层。
15.如权利要求14所述的避免翘曲的半导体结构的制作方法，其中该氮化硅层为紫外光可穿透(UV-transparent)氮化硅，其中该氮化硅层的折射率介于1.55至2.10之间。
16.如权利要求14所述的避免翘曲的半导体结构的制作方法，其中该多个半导体元件包含：
晶体管，设置在该晶片的该正面；
多个后端布线(back end of line)，设置在该晶体管上，其中该多个后端布线提供第一伸张应力使该晶片朝向该正面弯曲，该氧化硅层提供第三伸张应力使该晶片朝向该背面弯曲。
17.如权利要求16所述的避免翘曲的半导体结构的制作方法，其中该第一伸张应力等于该第三伸张应力。
18.如权利要求14所述的避免翘曲的半导体结构的制作方法，其中该氧化硅层包含四乙氧基硅烷(TEOS)、碳氧化硅(SiCO)或氮氧化硅(SiON)。
19.如权利要求14所述的避免翘曲的半导体结构的制作方法，其中该多个半导体元件包含：
多个第一输出/输入金属元件，设置在该正面，该多个第一输出/输入金属元件提供第一伸张应力使该晶片朝向该正面弯曲。
20.如权利要求19所述的避免翘曲的半导体结构的制作方法，另包含：
多个第二输出/输入金属元件，设置在该背面，该多个第二输出/输入金属元件提供第二伸张应力使该晶片朝向该背面弯曲，其中该第二伸张应力小于该第一伸张应力，其中该氧化硅层和该紫外光可穿透氮化硅层设置在该多个第二输出/输入金属元件和该背面之间，在该紫外光照射制作工艺后，该氧化硅层提供第三伸张应力使该晶片朝向该背面弯曲。
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