TWI578476B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI578476B
TWI578476B TW105108638A TW105108638A TWI578476B TW I578476 B TWI578476 B TW I578476B TW 105108638 A TW105108638 A TW 105108638A TW 105108638 A TW105108638 A TW 105108638A TW I578476 B TWI578476 B TW I578476B
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Taiwan
Prior art keywords
pads
row
semiconductor
germanium wafer
semiconductor package
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TW105108638A
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English (en)
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TW201639100A (zh
Inventor
陳盈志
周哲雅
林敏裕
楊家豪
儲文彬
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聯發科技股份有限公司
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Publication of TW201639100A publication Critical patent/TW201639100A/zh
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Publication of TWI578476B publication Critical patent/TWI578476B/zh

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Description

半導體封裝
本發明涉及半導體封裝結構，特別係涉及一種用於半導體封裝的祼晶片至祼晶片線接合墊佈置設計。
近年來，相應於電子裝置的高性能和多功能化，高容量半導體記憶體的需求快速增加。一般地，若干增加半導體記憶體存儲容量的方法已經被廣泛地使用。例如，增加半導體記憶體存儲容量的一種方法係增加半導體祼晶片(semiconductor die)的集成度。儘管增加半導體祼晶片集成度的方法能夠輕易地增加半導體記憶體的存儲容量，但是顯著地增加了開發和研究環境中的製造成本和時間消耗。
增加半導體記憶體存儲容量的另一種方法係將複數個半導體記憶體祼晶片安排進單個半導體封裝中(如，多祼晶片半導體封裝)。例如，複數個半導體記憶體祼晶片係水平或垂直地居於單個半導體封裝中。但是，因為需要改變封裝基板的設計以相應於此種半導體記憶體祼晶片佈置，所以此種方法不可避免地增加製造成本。另外，由於此種封裝基板的設計改變，也會增加封裝尺寸。相應地，習知的多祼晶片半導體封裝不能調整以適應電子裝置的小型化。
如此，期望一種具有高容量的創新半導體記憶體 封裝。
因此，本發明之主要目的即在於提供一種半導體封裝，可以增加半導體封裝的存儲容量。
根據本發明至少一個實施例的半導體封裝，包括：一第一半導體祼晶片，具有一第一祼晶片部分，一第二祼晶片部分，以及位於該第一和第二祼晶片部分之間的一切割道部分；一在該半導體祼晶片之上的一鈍化層，該鈍化層具有彼此相鄰的一第一區域和一第二區域；一第一鈍化後互連結構，包括：佈置在第一排中的複數個第一墊，以及佈置在第二排中的複數個第二墊，其中該等第一和第二墊設置在對應該第一祼晶片部分的該鈍化層的該第一區域之上；一第二鈍化後互連結構，包括：設置在第三排中的復數個第三墊，以及設置在第四排中的複數個第四墊，其中該等第三和第四墊設置在對應該第二祼晶片部分的該鈍化層的該第一區域之上；一第一接合線，具有兩個端，分別耦接至該等第一墊之一和該等第四墊之一；以及一第二接合線，具有兩個端，分別耦接至該等第二墊之一和該等第三墊之一。
以上的半導體封裝，半導體記憶體祼晶片的兩個祼晶片部分通過祼晶片至祼晶片線接合墊和祼晶片至祼晶片接合線而彼此電性連接，從而增加半導體封裝的存儲容量。
100‧‧‧半導體祼晶片
100a‧‧‧第一祼晶片部分
100b‧‧‧切割道部分
100c‧‧‧第二祼晶片部分
102‧‧‧鈍化層
102a‧‧‧第一區域
102b‧‧‧第二區域
101’、103’‧‧‧接觸墊
101、103‧‧‧PPI墊
114、116‧‧‧電源/接地墊
104‧‧‧第一墊
106‧‧‧第二墊
115、117‧‧‧重分佈線
201‧‧‧第一排
202‧‧‧第二排
108‧‧‧第三墊
110‧‧‧第四墊
112‧‧‧第五墊
203‧‧‧第三排
204‧‧‧第四排
120‧‧‧第一接合線
130‧‧‧第二接合線
H1、H2‧‧‧線接合高度
600、600’‧‧‧半導體封裝
300‧‧‧第一基板
300a、500a‧‧‧設備連接面
301、303‧‧‧I/O墊
203、305‧‧‧接合線
400‧‧‧第二半導體祼晶片
500‧‧‧第二基板
501‧‧‧指狀結構
第1A圖係半導體設備的典型實施例的頂視圖，其清楚地 示出了一種典型的祼晶片至祼晶片線接合墊佈置設計，用於半導體設備。
第1B圖係第1A圖所示的半導體設備的典型實施例的側面透視圖。
第2A圖係具有第1A圖所示的半導體設備的半導體封裝的典型實施例的頂視圖。
第2B圖係第2A圖所示的半導體封裝的典型實施例的側面透視圖。
第3圖係半導體封裝的典型實施例的側面透視圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
下面的描述包含了製造製程，並且是出於公開的目的。但是應當理解，為了說明製造製程和本公開的使用的目的而提供該描述，並且該描述不應被理解成具有限制性的意 義。在圖式或說明書中，相同或相似的元件使用相同或類似的符號表示或標記。此外，出於簡單化和方便，可以放大圖式中所示的元件的形狀或厚度。此外，本領域公知的通用元件沒有示出在圖式中或在說明書中描述。
參考第1A和1B圖，第1A圖是半導體設備的典型實施例的頂視圖，其明確地示出了用於半導體設備的祼晶片至祼晶片線接合墊(die-to-die wire bonding pad)佈置設計的一個典型實施例。第1B圖是第1A圖所示的半導體設備的側面透視圖。在本實施例中，該半導體設備包括：一半導體祼晶片100，諸如RAM(Random Access Memory；隨機存取記憶體)祼晶片。如第1A圖所示，該半導體祼晶片100包括：一第一祼晶片部分100a、一第二祼晶片部分100c和在該第一祼晶片部分100a和該第二祼晶片部分100c之間的一切割道(scribe line)部分100b。
在一個實施例中，通過把含有複數個記憶體祼晶片區域的晶圓分割為單獨的祼晶片來得到該半導體祼晶片100。例如，提供現存的已合格祼晶片(known good die；KGN)晶圓，該KGN晶圓具有複數個由複數條切割道定義的記憶體祼晶片區域。然後，分割KGN晶圓為單獨的祼晶片，此處，某些單獨的祼晶片包括：兩個相鄰的由切割道分開的記憶體祼晶片區域。也就是，單獨的祼晶片包括：切割道以及兩個祼晶片區域，該兩個祼晶片區域由半導體祼晶片100的切割道部分100b、第一祼晶片部分100a和第二祼晶片部分100c定義。
在本實施例中，該半導體設備進一步包括：一鈍 化層102，覆蓋半導體祼晶片100的頂面，如第1B圖所示。該鈍化層102可以由非有機材料形成，例如：氧化矽，氮化矽，氮氧化矽，非摻雜矽玻璃(undoped silicate glass；USG)等等。在本實施例中，如第1A圖所示，該鈍化層102具有一第一區域102a和相鄰於該第一區域102a的一第二區域102b。另外，該鈍化層102可以包括：位於鈍化層102中的複數個開口(未示出)，該等開口對應於該第一區域102a，以暴露第一祼晶片部分100a的接觸墊101’(即輸入輸出(I/O)墊)以及第二祼晶片部分100c的接觸墊103’(即I/O墊)。一般地，這些I/O墊包括：信號墊、電源墊和接地墊。
在本實施例中，該半導體設備進一步包括：在鈍化層102上的一第一鈍化後互連(post-passivation interconnect；PPI；如此命名的原因在於其在鈍化層之後形成)結構和一第二PPI結構。該第一和第二PPI結構分別對應半導體祼晶片100的第一祼晶片部分100a和第二祼晶片100c部分。在一個實施例中，該第一PPI結構包括：複數個PPI墊101、複數個電源/接地墊114、複數個第一墊104、複數個第二墊106以及用於連接這些墊101、104、106和114的複數條重分佈線115。該等PPI墊101設置在鈍化層102的第一區域102a之上並且對齊於第一祼晶片部分100a的接觸墊101’。該等PPI墊101佈置在一條接近並且平行於第一祼晶片部分100a的邊緣的直線中，並且通過鈍化層102相應地電性連接至第一祼晶片部分100a的接觸墊101’。該等電源/接地墊114設置在鈍化層102的第二區域102b之上。另外，該等電源/接地墊114通過 重分佈線115電性連接至某些PPI墊101，這些PPI墊101耦接至第一祼晶片部分100a的電源/接地墊(即接觸墊)。
該等第一墊104和第二墊106設置在鈍化層102中的第一區域102a上，並且分別佈置在第一排(tier)201和第二排202中。在一個實施例中，第一排201和第二排202彼此平行，並且沒有墊設置在第一排201和第二排202之間。另外，第一排201和第二排202平行於切割道部分100b的延伸方向。在一個實施例中，第一排201平行於第一祼晶片部分100a中平行於切割道部分100b的延伸方向的邊緣，從而第一排201比第二排202更接近第一祼晶片部分100a的該邊緣，以及第二排202比第一排201更接近切割道部分100b。另外，該等第一墊104和第二墊106係通過重分佈線115電性連接至某些PPI墊101，並且這些PPI墊101耦接至該第一祼晶片部分100a的信號墊(即接觸墊)。在本實施例中，某些第一墊104可以對應某些第二墊106。另外，某些第一墊104可以對齊或者不對齊於某些第二墊106。在本實施例中，第一墊104的總數量等於或不同於第二墊106的總數量。例如，第一墊104的總數量大於第二墊106的總數量。注意，第1A圖所示的墊101、104、106和114的數量為示例，而本發明不限制於此。
在一個實施例中，該第二PPI結構包括：複數個PPI墊103、複數個電源/接地墊116、複數個第三墊108、複數個第四墊110、複數個第五墊112和用於連接這些墊103、108、110、112和114的複數條重分佈線117。該等PPI墊103設置在鈍化層102中的第一區域102a上，並且對齊於第二祼晶片 部分100c的接觸墊103’。該等PPI墊103設置在接近並且平行於第二祼晶片部分100c的邊緣的直線中，並且通過鈍化層102對應地電性連接至第二祼晶片部分100c的接觸墊103’。該等電源/接地墊116設置在鈍化層102的第二區域102b之上。另外，該等電源/接地墊116係通過重分佈線117電性連接至某些PPI墊103，這些PPI墊103耦接至第二祼晶片部分100c的電源/接地墊(即接觸墊)。
該等第三墊108和第四墊110設置在鈍化層102的第一區域102a之上並且分別設置在第三排203和第四排204中。在一個實施例中，第三排203和第四排204平行於第一排201和第二排202，並且沒有墊位於第三排203和第四排204之間。另外，第三排203和第四排204也平行於切割道部分100b的延伸方向。在一個實施例中，第四排204平行第二祼晶片部分100c中平行於切割道部分100b的延伸方向的邊緣，從而第四排204比第三排203更接近第二祼晶片部分100c的該邊緣，以及第三排203比第四排204更接近切割道部分100b。另外，第三墊108和第四墊110通過重分佈線117電性連接至某些PPI墊103，這些PPI墊103耦接至第二祼晶片部分100c的信號墊(即接觸墊)。在本實施例中，某些第三墊108可以對應某些第四墊110。另外，某些第四墊110可以對齊或不對齊於對應的第三墊108。在本實施例中，第四墊110的總數量等於或不同於第三墊108的總數量。例如，第四墊110的總數量大於第三墊108的總數量。在本實施例中，第一墊104的總數量等於第四墊110的總數量，以及第二墊106的總數量等於第三 墊108的總數量。
第五墊112設置在鈍化層102的第二區域102b之上。在一個實施例中，第五墊112沿垂直於第一排201、第二排202、第三排203和第四排204的方向排列。另外，第五墊112係通過重分佈線117電性連接至某些PPI墊103，這些PPI墊103耦接至第二祼晶片部分100c的信號墊(即接觸墊)。該等第五墊112係通過重分佈線117電性連接至第三墊108和第四墊110。另外，注意，第1A圖中所示的墊103、108、110、112和116的數量為示例，並且本發明不限制於此。
在本實施例中，該半導體設備進一步包括：復數條第一接合線120和復數條第二接合線130(在第1A圖中沒有示出，但是在第2A圖中示出)。該等第一和第二接合線120和130用來作為用於半導體祼晶片100中的第一祼晶片部分100a和第二祼晶片部分100c的祼晶片至祼晶片接合線。此中，為了簡化圖形，在第1B圖中僅描繪了一條第一接合線120和一條第二接合線130。如第1B圖所示，第一接合線120具有兩個端，分別耦接至該等第一墊104之一和該等第四墊110之一。類似地，第二接合線130具有兩端，分別耦接至該等第二墊106之一以及該等第三墊108之一。在本實施例中，每條第一接合線120具有線接合高度H1，並且每條第二接合線130具有線接合高度H2。另外，線接合高度H1大於線接合高度H2，以避免短路問題。在第一和第二接合線120和130分別耦接在第一和第四墊104、110之間，以及第二和第三墊106、108之間後，第一祼晶片部分100a的接觸墊101’可以通過第一和 第二PPI結構以及第一和第二接合線120和130，電性連接至第二祼晶片部分100c的接觸墊103’。
參考第2A和2B圖，第2A圖為頂視圖，示出了半導體封裝600的典型實施例，該半導體封裝600具有第1A圖所示的半導體設備，以及第2B圖為第2A圖所示的半導體封裝600的側面透視圖。在本實施例中，半導體封裝600包括：一第一基板300，例如封裝基板，具有一設備連接面300a(如第2B圖所示)。第1A圖所示的半導體設備中的半導體祼晶片100貼合到第一基板300的設備連接面300a之上。此中，為了簡化圖形，如第1A圖中所示的重分佈線115和117均沒有在第2A圖中描繪。在一個實施例中，該第一基板300可以包括：嵌入於該第一基板300中的一導電線路(沒有示出)以及在該第一基板300上的一I/O墊301和303。在一個實施例中，該導電線路用於直接貼合在第一基板300之上的半導體祼晶片100的I/O連接。半導體祼晶片100的第一祼晶片部分100a和第二祼晶片部分100c的電路係通過一第一導電路徑和一第二導電路徑電性連接至第一基板300的電路，該第一導電路徑由第二PPI結構中的第五墊112、接合線(binding wire)203和第一基板300的I/O墊301所構建，該第二導電路徑由第二PPI結構的電源/接地墊116、接合線203和第一基板300的I/O墊301所構建。此中，為了簡化圖形，僅描述了由第五墊112、接合線203和I/O墊301所構建的第一導電路徑，如第2B圖中所示。另外，如第2A圖所示，僅描述了某些導電路徑。
在本實施例中，該半導體封裝600進一步包括： 一第二半導體祼晶片400，設置在第一基板300的下方。在一個實施例中，第二半導體祼晶片400可以為記憶體控制器祼晶片，用於控制貼合在第一基板300之上的半導體設備。在本實施例中，該半導體封裝600進一步包括：一第二基板500，設置在第二半導體祼晶片400的下方，從而第二半導體祼晶片400插入於第一基板300和第二基板500之間。在一個實施例中，第二基板500(例如印刷線路板(PCB))具有設備連接面500a(如第2B圖所示)。該第二半導體祼晶片400貼合在該第二基板500的設備連接面500a上。在一個實施例中，導電線路用於直接貼合在第二基板500之上的第二半導體祼晶片400的I/O連接。該第二半導體祼晶片400的電路通過覆晶技術電性連接至第二基板500的電路。另外，第一基板300的電路通過導電路徑電性連接至第二基板500的電路，該導電路徑由第一基板300的I/O墊303、接合線305和第二基板500的指狀結構(finger)501所構建，從而半導體祼晶片100通過第一基板300電性連接至祼晶片400。此中，為了簡化圖形，如第2B圖所示，僅描繪了由第一基板300的I/O墊303、接合線305和第二基板500的指狀結構501所構建的導電路徑。
參考第3圖，為半導體封裝600’的典型實施例的側面透視圖。以下實施例中描述的元件，相同或類似於先前已參考第2A和2B圖已描述了的元件的，出於簡潔而省略。在本實施例中，半導體封裝600’類似於第2A和2B圖所示的半導體封裝600。在本實施例中，半導體祼晶片100與第一基板300和第二半導體祼晶片400不對齊(misaligned)，從而半導 體祼晶片100的一部分懸於第一基板300和第二半導體祼晶片400之上。在這種情形中，第二半導體祼晶片400和第一基板300具有的尺寸可以等於或大於祼晶片100具有的尺寸。根據前面的實施例，由於半導體記憶體祼晶片包括：通過分割已有的晶圓而提供的兩個祼晶片部分，以及由於該兩個祼晶片部分通過祼晶片至祼晶片線接合墊以及祼晶片至祼晶片接合線而彼此電性連接，因此半導體記憶體封裝的存儲容量可以增加兩倍，而無需增加半導體記憶體祼晶片的集成度。因此，可以降低開發和研究環境中的製造成本和時間消耗。另外，由於半導體記憶體祼晶片的電路包括：兩個祼晶片部分，能夠經由設置在半導體封裝記憶體祼晶片中的其中一個祼晶片部分(如，第二祼晶片部分)上的I/O墊(如第一墊)而電性連接至封裝基板(即第一基板)的電路，所以不需要改變封裝基板的設計。因此，可以排除設計新封裝基板的成本以及維持封裝尺寸。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、均等替換和改進等，均應包含在本發明的保護範圍之內。
100a‧‧‧第一祼晶片部分
100b‧‧‧切割道部分
100c‧‧‧第二祼晶片部分
102‧‧‧鈍化層
104‧‧‧第一墊
106‧‧‧第二墊
108‧‧‧第三墊
110‧‧‧第四墊
120‧‧‧第一接合線
130‧‧‧第二接合線
H1、H2‧‧‧線接合高度

Claims (16)

  1. 一種半導體封裝，包括：一第一半導體祼晶片，具有一第一祼晶片部分，一第二祼晶片部分，以及位於該第一和第二祼晶片部分之間的一切割道部分；一在該第一半導體祼晶片之上的一鈍化層，該鈍化層具有彼此相鄰的一第一區域和一第二區域；一第一鈍化後互連結構，包括：佈置在第一排中的複數個第一墊，以及佈置在第二排中的複數個第二墊，其中該等第一墊和該等第二墊設置在對應該第一祼晶片部分的該鈍化層的該第一區域之上；一第二鈍化後互連結構，包括：設置在第三排中的復數個第三墊，以及設置在第四排中的複數個第四墊，其中該等第三墊和該等第四墊設置在對應該第二祼晶片部分的該鈍化層的該第一區域之上；一第一接合線，具有兩個端，分別耦接至該等第一墊之一和該等第四墊之一；以及一第二接合線，具有兩個端，分別耦接至該等第二墊之一和該等第三墊之一；其中，該第二鈍化後互連結構進一步包括：複數個第五墊，設置在對應該第二祼晶片部分的該鈍化層中的該第二區域之上，並且電性連接至該等第三和第四墊。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，該第一排、該第二排、該第三排和該第四排彼此平行。
  3. 如申請專利範圍第2項所述的半導體封裝，其中，該第一排、該第二排、該第三排和該第四排平行於該切割道部分的延伸方向。
  4. 如申請專利範圍第2項所述的半導體封裝，其中，該第一排平行於該第一祼晶片部分的一邊緣，以及該第一排比該第二排更接近該邊緣。
  5. 如申請專利範圍第4項所述的半導體封裝，其中，該第二排比該第一排更接近該切割道部分。
  6. 如申請專利範圍第2項所述的半導體封裝，其中，該第四排平行於該第二祼晶片部分的一邊緣，以及該第四排比該第三排更接近該邊緣。
  7. 如申請專利範圍第6項所述的半導體封裝，其中，該第三排比該第四排更接近該切割道部分。
  8. 如申請專利範圍第1項所述的半導體封裝，其中，該等第一墊的總數量等於該等第四墊的總數量，以及該等第二墊的總數量等於該等第三墊的總數量。
  9. 如申請專利範圍第1項所述的半導體封裝，其中，該第一接合線具有的線接合高度大於該第二接合線具有的線接合高度。
  10. 如申請專利範圍第1項所述的半導體封裝，其中，該等第五墊沿垂直於該第一排、該第二排、該第三排和該第四排的方向排列。
  11. 如申請專利範圍第1項所述的半導體封裝，其中，該第一半導體祼晶片為隨機存取記憶體祼晶片。
  12. 如申請專利範圍第1項所述的半導體封裝，其中，進一步包括：一第一基板，該第一半導體祼晶片安裝在該第一基板之上；一第二基板，設置在該第一基板的下方；以及一第二半導體祼晶片，插入在該第一和第二基板之間。
  13. 如申請專利範圍第12項所述的半導體封裝，其中，該第一半導體祼晶片係通過該第一基板電性連接至該第二半導體祼晶片。
  14. 如申請專利範圍第12項所述的半導體封裝，其中，該第二半導體祼晶片係電性連接至該第二基板。
  15. 如申請專利範圍第12項所述的半導體封裝，其中，該第一半導體祼晶片不對齊於該第二半導體祼晶片，以便於該第一半導體祼晶片中的一部分懸於該第二半導體祼晶片之上。
  16. 如申請專利範圍第12項所述的半導體封裝，其中，該第一半導體祼晶片不對齊於該第一基板，以便於該第一半導體祼晶片中的一部分懸於該第一基板之上。
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