TWI755052B - 針對用於半導體封裝之矽橋的無金屬框設計(二) - Google Patents

針對用於半導體封裝之矽橋的無金屬框設計(二) Download PDF

Info

Publication number
TWI755052B
TWI755052B TW109130417A TW109130417A TWI755052B TW I755052 B TWI755052 B TW I755052B TW 109130417 A TW109130417 A TW 109130417A TW 109130417 A TW109130417 A TW 109130417A TW I755052 B TWI755052 B TW I755052B
Authority
TW
Taiwan
Prior art keywords
metal
semiconductor
substrate
grommet
guard ring
Prior art date
Application number
TW109130417A
Other languages
English (en)
Other versions
TW202111895A (zh
Inventor
賽倫 亞格拉哈蘭
蘇吉斯 莎朗
大宇 金
Original Assignee
美商英特爾公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商英特爾公司 filed Critical 美商英特爾公司
Publication of TW202111895A publication Critical patent/TW202111895A/zh
Application granted granted Critical
Publication of TWI755052B publication Critical patent/TWI755052B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1715—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/17153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/17177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

茲描述針對用於半導體封裝之矽橋的無金屬框設計和所得矽橋及半導體封裝體。在一實施例中，一種半導體結構包括：一基板，其具有設置於其上之一絕緣層，該基板有一周界。一金屬化結構設置於該絕緣層上，該金屬化結構包括設置於一介電材料堆疊中的傳導性之佈線。一第一金屬護環設置於該介電材料堆疊中且包圍該傳導性之佈線。一第二金屬護環設置於該介電材料堆疊中且包圍該第一金屬護環。該介電材料堆疊的一無金屬區域包圍該第二金屬護環。該無金屬區域係設置成鄰接該第二金屬護環及鄰接該基板之該周界。

Description

針對用於半導體封裝之矽橋的無金屬框設計(二)
本發明的具體實施例屬於半導體封裝領域，且特別有關於針對用於半導體封裝之矽橋的無金屬框設計和所得矽橋及半導體封裝體。
現今的消費者電子產品市場經常要求需要極複雜電路的複雜功能。按比例縮放成越來越小的基本建構區塊，例如電晶體，已使得每個先進世代可在單一晶粒上加入更複雜的電路。半導體封裝用來保護積體電路(IC)晶片或晶粒，而且也用來提供具有外部電路之電氣介面的晶粒。隨著更小電子元件的需求增加，半導體封裝體也被設計成更加緊湊而且必須支援更高的電路密度。此外，效能更高裝置的需求導致亟須改善半導體封裝使得薄封裝輪廓及低整體翹曲有可能與後續組裝加工相容。
C4焊球連接多年來已用來提供半導體裝置與基板之間的倒裝晶片互連。倒裝晶片或控制塌陷高度晶片連接(C4)為一種使用於例如積體電路(IC)晶片、MEMS或組件之半導體裝置的安裝方式係利用銲錫凸塊而不是打 線(wire bond)。銲錫凸塊沉積於位在基板封裝體頂面的C4墊上。為了安裝半導體裝置於基板，在安裝區上以主動面朝下的方式翻轉它。銲錫凸塊用來使半導體裝置直接連接至基板。
與習知IC製造類似的倒裝晶片加工有幾個額外步驟。在製程快要結束時，將附接墊(attachment pad)金屬化以使它們更能接收焊錫。這通常由數個處理組成。然後，在各個金屬化墊上沉積一個小點的焊錫。然後，照常從晶圓切出晶片。為了附加倒裝晶片於電路中，倒置該晶片使焊點降落到在底下電子器件或電路板上的連接器上。然後，再熔化該焊錫以產生電氣連接，通常是使用超音波或者回焊製程。這在晶片的電路與底下的座架之間也留下小空間。在大多數情形下，隨後「底填」一電絕緣黏著劑以提供較強的機械連接，提供熱橋(heat bridge)，以及確保焊接點沒有由於晶片與系統其餘部份之差別加熱(differential heating)引起的應力。
較新的封裝及晶粒對晶粒互連辦法，例如矽通孔(TSV)、矽中介層及矽橋，得到為了實現高效多晶片模組(MCM)和系統級封裝(SiP)的設計人員越來越多的關注。不過，此類較新的封裝方案需要額外的改良。
依據本發明之一實施例，係特地提出一種半導體結構，其包含：一基板，該基板具有設置於其上之一絕緣層，該基板具有一周界；一金屬化結構，該金屬化結 構設置於該絕緣層上，該金屬化結構包含設置於一介電材料堆疊中的傳導性之佈線；一第一金屬護環，該第一金屬護環設置於該介電材料堆疊中且包圍該傳導性之佈線；一第二金屬護環，該第二金屬護環設置於該介電材料堆疊中且包圍該第一金屬護環；以及該介電材料堆疊的一無金屬區域，該無金屬區域包圍該第二金屬護環，該無金屬區域設置成鄰接該第二金屬護環及鄰接該基板之該周界。
100:半導體封裝體
102:第一晶粒
104:第二晶粒
106:矽橋
108、110:凸塊
108A、108B、110A、110B:凸塊陣列
108B、110B:凸塊
112A、112B:接合墊
114:封裝基板
116:金屬化層
117:周界
118:絕緣層
120:無金屬區域
200:部份
202:第一矽橋晶粒
204:第二矽橋晶粒
206、208:第一金屬護環
210、212:主動區
214、216:第二金屬護環
218、220:區域
222:無金屬刻劃線
300:部份
302、304:第一、第二矽橋晶粒
306、308:外緣
310:內金屬護環
312:外金屬護環
314:交錯虛擬金屬特徵
316:微影對準標記
318:無金屬刻劃線
400:部份
402:晶粒邊緣
404:無金屬區
406:外護環
408:內護環
410:主動區
412:虛擬金屬特徵
414:晶粒龜裂
500:半導體結構
502:基板
504:絕緣層
506:周界
508:金屬化結構
510:傳導性之佈線
512:介電材料堆疊
514:第一金屬護環
516:第二金屬護環
518:無金屬區域
519:金屬特徵
520:電子測試墊
522:墊
599:公共軸線
700:半導體封裝體
752:第一晶粒
754:記憶體晶粒堆疊
756:嵌入式多晶粒互連橋/EMIB
758、760:凸塊
770:基板或板材料
799:底填材料
800:封裝佈局
802:共用基板
804:中央處理單元或系統單晶片(CPU/SoC)晶粒
806:記憶體晶粒
808:嵌入式多晶粒互連橋/EMIB
810:C4連接體
812:晶粒對晶粒間距
900:流程圖
902、904:操作
1000:電腦系統/電子系統
1010、1011:積體電路(晶粒)
1012、1013:處理器
1014、1015:通訊電路
1016、1017:晶粒上記憶體/eDRAM
1020:系統匯流排
1030:電壓源
1040:外部記憶體
1042:主記憶體
1044:硬碟
1046:可移除式媒體
1048:嵌入式記憶體
1050:顯示裝置
1060:聲頻輸出
1070:控制器
W1、W2:寬度
圖1A的橫截面圖根據本發明之一具體實施例圖示有連接多個晶粒之嵌入式多晶粒互連橋(EMIB)的半導體封裝體。
圖1B的平面圖根據本發明之一具體實施例圖示圖1A之第一及第二晶粒的凸塊陣列。
圖2的平面圖根據本發明之一具體實施例圖示有複數個矽橋晶粒製造其上之矽晶圓的一部份。
圖3根據本發明之一具體實施例圖示相鄰矽橋晶粒在共用基板或晶圓上的示範佈局。
圖4的放大平面圖根據本發明之一具體實施例圖示包括形成於其中之龜裂的矽橋晶粒之一部份。
圖5的橫截面圖根據本發明之一具體實施例圖示雙護環結構中之一護環。
圖6的橫截面圖根據本發明之一具體實施例圖示雙護環結構。
圖7的橫截面圖根據本發明之一具體實施例 圖示包括與嵌入式多晶粒互連橋(EMIB)耦接之多個晶粒的半導體封裝體。
圖8的平面圖根據本發明之一具體實施例圖示共封裝高效運算(HPC)晶粒的封裝佈局與高頻寬記憶體(HBM)佈局。
圖9的流程圖根據本發明之一具體實施例圖示複數個矽橋晶粒之製造方法的操作。
圖10根據本發明之一具體實施例示意圖示一電腦系統。
茲描述針對用於半導體封裝之矽橋的無金屬框設計和所得矽橋及半導體封裝體。在以下說明中，提出許多特定細節，例如封裝及互連架構，供徹底了解本發明的具體實施例。熟諳此藝者應瞭解，在沒有這些細節下可實施本發明的具體實施例。在其他情況下，不詳述習知特徵，例如特定半導體製程，以免不必要地混淆本發明的具體實施例。此外，應瞭解，圖示於附圖的各種具體實施例為圖解說明且不一定按比例繪製。
描述於本文的一或更多具體實施例針對用於矽(Si)橋的無金屬框設計。應用特別有用於所謂的2.5D封裝設計。如通篇所用所，用語「矽橋」用來指稱提供兩個或更多裝置晶粒之接線(routing)的晶粒。用語「嵌入式多晶粒互連橋(EMIB)」意指封裝基板或所得封裝包括此一矽橋晶粒。
為了提供上下文，使用及/或評估用於例如組合高效運算(HPC)與高頻寬記憶體(HBM)之應用的嵌入式多晶粒互連橋(EMIB)技術。矽橋技術常涉及使用極厚的金屬層疊(metal stack-up)，通常金屬總共約有20微米或更多以減少以其他方式與習知訊號接線關聯的電阻。該等矽橋晶粒可由有複數個此類晶粒在其上的晶圓製成。同樣地，晶圓的切晶(dicing)需要單粒化(singulate)該等矽橋晶粒。不過，在鋸斷(saw cut)前使用雷射刻劃製程(laser scribe process)的傳統做法不可能使用於矽橋技術，因為包括晶圓刻劃線(scribe line)的堆疊中有厚厚的銅(Cu)金屬層。此外，已證明在沒有雷射刻劃下超薄矽橋晶圓的處理及切割是極大的挑戰。例如，去除單粒化製程的雷射刻劃操作常導致小晶粒龜裂的形成。
應付上述問題中之一或更多，描述於本文的具體實施例針對雙護環及刻劃線(溝道)無金屬區框設計的製造及使用。可實作此一設計以最小化及/或減少晶粒龜裂擴散(propagate)。在一具體實施例中，此一框設計更涉及兩個護環在雙護環設計中的分離以便包括兩個密閉的密封護環之間的交錯金屬層虛擬化。可實作該整體設計以提供晶粒龜裂擴散的最大保護，特別是在有複數個矽橋晶粒之晶圓的單粒化期間。
為了進一步提供上下文，針對保護可能晶粒龜裂擴散及水分滲入的習知框或(溝道)設計常包括使用 並排定位的兩個護環以及金屬網壕溝結構(metal-meshed moat structure)於刻劃線中。此類結構的切晶通常涉及壕溝區的雷射刻劃以在鋸斷製程(saw cut process)期間最小化晶粒損傷。不過，如上述，矽橋技術可能不適合使用並排護環與壕溝，因為雷射刻劃時存在相對厚銅金屬層。此外，雷射刻劃加工通常可能很貴。
根據描述於本文的一或更多具體實施例，用於矽橋晶粒之晶圓的框設計包括在切晶期間提供初始保護與鋸斷區緊鄰用於各個個別晶粒的第一(外)護環。第二(內)護環位在晶粒邊緣四周。交錯金屬陣列放在內、外護環之間。在單粒化製程期間(或之後)通過外護環擴散的一或更多龜裂可在位於內、外護環之間的交錯金屬陣列終止。
提供描述於本文之概念的高階概圖，圖1A的橫截面圖根據本發明之一具體實施例圖示有連接兩個晶粒之嵌入式多晶粒互連橋(EMIB)的半導體封裝體。請參考圖1A，半導體封裝體100包括第一晶粒102(例如，記憶體晶粒)與第二晶粒104(例如，邏輯、CPU或SoC晶粒)。例如，藉由熱壓接合(TCB)，第一晶粒102及第二晶粒104各自通過第一晶粒102及第二晶粒104的凸塊108及110以及矽橋106的接合墊112A及112B(也被稱為傳導墊112A及112B)耦接至矽橋106。
第一晶粒102及第二晶粒104設置於封裝基板114上。封裝基板114包括形成於絕緣層118中的金屬 化層116(例如，線與通孔的垂直配置)。金屬化層116可為簡單或複雜型且可用來耦接至其他封裝或可形成有機封裝或印刷電路板(PCB)的一部份或全部等等。第一晶粒102及第二晶粒104各自通過凸塊108B及110B可直接耦接至封裝基板114，如圖1A所示。圖1B的平面圖圖示圖1A之第一102、第二104晶粒的凸塊陣列108A、108B、110A及110B。
再參考圖1A，圖示矽橋106被稱為嵌入式多晶粒互連橋(EMIB)，因為它包括封裝基板114的諸層。在另一具體實施例中，此一矽橋106不嵌入封裝，反而在基板或板的開放空腔中。在這兩種情形下，在一具體實施例中，以及以及如下文所詳述的，矽橋106包括有一絕緣層設置於其上的一矽基板，該矽基板有一周界117。一金屬化結構設置於該絕緣層上，該金屬化結構包括設置於一介電材料堆疊中的傳導性之佈線。一第一金屬護環(first metal guard ring)設置於介電材料堆疊中且包圍該傳導性之佈線。一第二金屬護環設置於該介電材料堆疊中且包圍該第一金屬護環。該介電材料堆疊的一無金屬區域120包圍該第二金屬護環。無金屬區域120係鄰接第二金屬護環和鄰接矽基板周界117地設置。在一具體實施例中，矽橋106的矽基板沒有設置於其中的半導體裝置(亦即，該矽橋只提供接線層而且不是主動半導體裝置)。
在一具體實施例中，矽橋106的第一金屬護環或第二金屬護環中之至少一者提供該矽橋之該金屬化結 構的一密閉的密封。在一具體實施例中，矽橋106更包括在該第一金屬護環與該第二金屬護環之間設置於該介電材料堆疊中的數個金屬特徵，該等金屬特徵包括一特徵，例如但不限於對準標記、虛擬特徵或測試特徵。在一具體實施例中，矽橋106的第一金屬護環或第二金屬護環中之至少一者包括由沿著一公共軸線對齊之數條金屬線及數個通孔交錯組成的一垂直堆疊。
再參考圖1A，第一102、第二104相鄰半導體晶粒設置於半導體封裝基板114上以及用矽橋106之金屬化結構的傳導性之佈線互相電氣耦接。在一具體實施例中，第一半導體晶粒102為記憶體晶粒，以及第二半導體晶粒104為邏輯晶粒。第一半導體晶粒102附接至矽橋106的第一複數個傳導墊112A，以及第二半導體晶粒104附接至矽橋106的第二複數個傳導墊112B。在一具體實施例中，矽橋106的傳導性之佈線使第一複數個傳導墊112A與第二複數個傳導墊112B電氣耦接。在一具體實施例中，矽橋106的第一112A、第二112B複數個傳導墊包括厚度大於約5微米的一銅層。
如上述，複數個矽橋晶粒可製造於最終需要切晶以提供單粒化矽橋晶粒的共用矽晶圓上。例如，圖2的平面圖根據本發明之一具體實施例圖示有複數個矽橋晶粒製作於其上的矽晶圓之一部份。
請參考圖2，矽晶圓的部份200包括在其上的第一矽橋晶粒202與第二矽橋晶粒204。第一金屬護環 206或208各自包圍第一202、第二204矽橋晶粒的主動區210或212。第二金屬護環214或216各自包圍第一金屬護環206或208。用於各種金屬化特徵的區域218或220各自包括在第一護環206或208與第二護環214或216之間，如下文所詳述。無金屬刻劃線222使第一202、第二204矽橋晶粒各自在第二護環214或216外隔開。應注意，圖2只圖示兩個矽橋晶粒。不過，應瞭解，晶圓或標線片(reticle)可包括更複數個矽橋晶粒，這取決於晶圓或標線片大小以及取決於晶粒大小。
在一具體實施例中，圖2的主動晶粒區域210或212包括所有訊號及電力/接地互連，這考慮到在晶粒之間的切晶溝道(dicing street)中的無金屬刻劃線222。作為有更多細節的實施例，圖3根據本發明之一具體實施例圖示相鄰矽橋晶粒在共用基板或晶圓上的示範佈局。
圖3圖示複數個矽橋晶粒在共用晶圓或標線片上之佈局的部份300。圖示的部份300包括第一及第二矽橋晶粒302及304的部份。也圖示晶粒302或304的各自外緣306或308。應瞭解，原尺寸佈局包括包圍第一及第二晶粒302及304之整個外周的外緣。外緣306及308各自包括內金屬護環310與外金屬護環312。在一特定具體實施例中，各個護環有約2微米的寬度(W1)，以及內金屬護環310與外金屬護環312的間距約有60至70微米。
在內金屬護環310、外金屬護環312之間可包括數個金屬特徵。例如，在一具體實施例中，內金屬護環310、外金屬護環312(如在說明圖4時所述)之間包括交錯虛擬金屬特徵314(在此也被稱為迷你護環)。在一具體實施例中，微影對準標記316包括在內金屬護環310、外金屬護環312之間。在一具體實施例中，無金屬刻劃線318在相鄰晶粒302及304的外護環312之間。在特定的此類具體實施例中，無金屬刻劃線318有約40至50微米的寬度(W2)。
再參考圖3，在一具體實施例中，用於各個晶粒302及304的此一雙護環框設計致能用於矽橋技術的只鋸晶粒單粒化製程(saw-only die singulation process)。無金屬刻劃線318寬度適合在不接觸銅(Cu)金屬特徵下允許鋸刀切割矽及介電層(例如，氧化矽層)。在一具體實施例中，如上述，內金屬護環310與外金屬護環312用交錯迷你護環隔開以便有最大的保護。另外，在一具體實施例中，內金屬護環310與外金屬護環312提供包括在晶粒302及304之所謂「主動」區域中之電氣接線的密閉的密封。
如上述，描述於本文的護環設計可適用於阻止在單粒化共用晶圓或標線片上之複數個矽橋晶粒期間或之後形成的龜裂擴散。在一實施例中，圖4的放大平面圖根據本發明之一具體實施例圖示包括形成於其中之龜裂的矽橋晶粒之一部份。
圖4圖示顯示晶粒邊緣402的晶粒部份400。晶粒邊緣402是晶粒在單粒化期間/之後的末端。雙金屬護環結構包括外護環406與內護環408。在晶粒邊緣402與外護環406之間包括無金屬區404。該等護環保護晶粒400的「主動」區410，其包括用於例如通過矽橋晶粒410之晶粒對晶粒通訊的金屬化/接線。護環406及408之間包括虛擬金屬特徵412，例如「迷你」護環。儘管未圖示，然而護環406及408之間可包括其他特徵，例如對準標記。根據本發明之一具體實施例，晶粒龜裂414在晶粒單粒化期間或之後形成。如圖示，晶粒龜裂414可從晶粒邊緣402開始。晶粒龜裂414可被外護環406阻止。不過，如果不被外護環406阻止，該龜裂最終在到達內護環408之前會被虛擬金屬特徵412阻止。亦即，在一具體實施例中，用可應用於供單粒化矽橋晶粒用之只鋸單粒化製程的雙金屬護環框設計最小化龜裂擴散。
可由金屬化結構的多層製成雙護環結構，例如複數個交錯金屬線及通孔。例如，圖5的橫截面圖根據本發明之一具體實施例圖示雙護環結構的護環。圖6的橫截面圖根據本發明之一具體實施例圖示雙護環結構。
請參考一起圖5及圖6，在一具體實施例中，半導體結構500(例如，矽橋)包括有絕緣層504設置於其上的基板502。該基板有周界506，它的最外面部份圖示於圖6的右手邊。金屬化結構508設置於絕緣層504上。金屬化結構508包括設置於介電材料堆疊512中的傳 導性之佈線510。
第一金屬護環514設置於介電材料堆疊512中且包圍傳導性之佈線510。第二金屬護環516(只圖示於圖6)設置於介電材料堆疊512中且包圍第一金屬護環514。介電材料堆疊512的無金屬區域518包圍第二金屬護環516(只圖示於圖6)。無金屬區域516係鄰接第二金屬護環516和鄰接基板502之周界506地設置。
在一具體實施例中，第一金屬護環514或第二金屬護環516中之至少一者提供金屬化結構508的一密閉的密封。在一具體實施例中，該半導體結構包括在第一金屬護環514、第二金屬護環516之間設置於介電材料堆疊中的數個金屬特徵519。另外，如圖6所示，在第一金屬護環514、第二金屬護環516之間可包括電子測試墊(e-test pad)520。因此，該等金屬特徵包括一特徵，例如但不限於：對準標記、虛擬特徵或測試特徵。在一具體實施例中，該第一金屬護環或該第二金屬護環中之至少一者包括由沿著公共軸線599對齊之數條金屬線及數個通孔交錯組成的一垂直堆疊，如圖5所示。在一具體實施例中，該金屬化結構的最上層包括第一及第二複數個傳導墊於其上，例如圖示於圖5的墊522(然而應瞭解，護環結構可省略該墊，即使包括在主動晶粒區的金屬化物中)。在一個此類具體實施例中，該傳導性之佈線使該等第一複數個傳導墊與該等第二複數個傳導墊電氣耦接。在一具體實施例中，該等第一及該等第二複數個傳導墊包括厚度大於約 5微米的一銅層。
在一具體實施例中，該基板502沒有設置於其中的半導體裝置。亦即，該矽橋晶粒的主要功能是要在耦接至該矽橋晶粒的兩個晶粒之間提供局部及直接的通訊。在一具體實施例中，該基板為一單晶矽基板。在一具體實施例中，該半導體結構更包括設置於該介電材料堆疊之無金屬區域中且擴散通過該第二金屬護環但不通過該第一金屬護環的龜裂，如以上在說明圖4時所述。
儘管上述具體實施例針對用矽橋或EMIB互相耦接的兩個個別晶粒，然而應瞭解，複雜結構也可受益於描述於本文的具體實施例。在第一實施例中，圖7的橫截面圖根據本發明之一具體實施例圖示包括與嵌入式多晶粒互連橋(EMIB)耦接之多個晶粒的半導體封裝體。請參考圖7，半導體封裝體700包括第一晶粒752(例如，邏輯晶粒中央處理單元、CPU)與記憶體晶粒堆疊754。例如，藉由熱壓接合(TCB)，第一晶粒752及記憶體晶粒堆疊754各自通過第一晶粒752及記憶體晶粒堆疊754的凸塊758及760耦接至EMIB 756。EMIB 756嵌入基板(例如，撓性有機基板)或板(例如，環氧樹脂PCB材料)材料770。在第一晶粒752、EMIB 756/基板770介面之間與在記憶體晶粒堆疊754、EMIB 756/基板770介面之間可包括底填材料799，如圖7所示。在一具體實施例中，EMIB 756包括被在最外面金屬護環外面之無金屬部份包圍的雙金屬護環，如上述。
在第二實施例中，圖8的平面圖根據本發明之一具體實施例圖示共封裝高效運算(HPC)晶粒的封裝佈局與高頻寬記憶體(HBM)佈局。請參考圖8，封裝佈局800包括共用基板802。中央處理單元或系統單晶片(CPU/SoC)晶粒804與8個記憶體晶粒806一起由基板802支撐。複數個EMIB 808用C4連接體810使記憶體晶粒806橋接至CPU/SoC晶粒804。晶粒對晶粒間距812約有100至200微米。應瞭解，從由上而下的視線透視，晶粒804及806設置於C4連接體810上方，C4連接體810設置於包括在基板802中的EMIB 808上方。在一具體實施例中，EMIB 808中之一或更多包括被在最外面金屬護環外面之無金屬部份包圍的雙金屬護環，如上述。
如上述，在一具體實施例中，矽橋的基板可為單晶矽基板。在其他具體實施例中，以及仍在「矽橋」的背景下，基板可由多或單晶體材料構成，它可包括但不限於鍺、矽-鍺或III-V族化合物半導體材料。在另一具體實施例中，使用玻璃基板。
參考以上關於矽橋技術的說明，在一具體實施例中，例如但不限於，絕緣、介電或層間介電(ILD)材料為以下各物中之一者：矽的氧化物(例如，二氧化矽(SiO2))，矽的摻雜氧化物，矽的氟化氧化物，矽的摻碳氧化物，本技藝所習知的各種低介電係數介電材料，以及彼等的組合。該絕緣、介電或層間介電(ILD)材料可用習知技術形成，例如，化學氣相沉積(CVD)，物理氣 相沉積(PVD)，或其他沉積方法。
參考以上關於矽橋技術的說明，在一具體實施例中，互連或傳導性之佈線材料由一或更多金屬或其他傳導結構構成。常見實施例是使用在銅與周圍ILD材料之間可能包括或不包括阻障層的銅線與結構(例如，通孔)。如本文所使用的，用語金屬包括多種金屬的合金、堆疊及其他組合。例如，金屬互連線可包括阻障層，不同金屬或合金的堆疊等等。該等互連線或傳導性之佈線在本技藝有時被稱為跡線、配線、線、金屬、或簡稱互連。
如上述，複數個矽橋晶粒可由共用晶圓製成。在一實施例中，圖9的流程圖900根據本發明之一具體實施例圖示製造複數個矽橋晶粒之方法的操作。
請參考流程圖900的操作902，一種製造複數個矽橋晶粒之方法包括：提供有複數個矽橋晶粒在其上的一晶圓。該等複數個矽橋晶粒中之每一者用數條無金屬刻劃線互相隔開。在一具體實施例中，該等複數個矽橋晶粒中之每一者在該雙金屬護環內有厚度大於約5微米的一最上面金屬層。
請參考流程圖900的操作904，製造該等複數個矽橋晶粒的該方法包括：藉由鋸切該晶圓的該等無金屬刻劃線來單粒化該等複數個矽橋晶粒。根據本發明之一具體實施例，該等複數個矽橋晶粒中之每一者在鋸切期間用該雙金屬護環保護。
在一具體實施例中，單粒化該等複數個矽橋 晶粒的步驟涉及留下該等無金屬刻劃線的一部份以保留作為該等經單粒化之複數個矽橋晶粒中之每一者的一部份。在一具體實施例中，該雙金屬護環的該等金屬護環中之至少一者在鋸切期間為該等複數個矽橋晶粒中之每一者提供一密閉的密封。在一具體實施例中，在鋸切該晶圓之該等無金屬刻劃線期間形成一龜裂。在一特定具體實施例中，該龜裂擴散通過該雙金屬護環的最外面金屬護環但是不通過該雙金屬護環的最內面金屬護環，即使在鋸切製程之後。在一具體實施例中，有無金屬最外面區域的雙金屬護環設計致能矽橋技術的只鋸晶粒單粒化製程。該無金屬區設在劃線區中以及可實作有迷你護環金屬虛擬化的雙護環以在晶粒單粒化期間或之後提供潛在晶粒龜裂的最大保護。
圖10根據本發明之一具體實施例示意圖示電腦系統1000。圖示電腦系統1000(也被稱為電子系統1000)可體現有無金屬框設計的矽橋，這是根據如本揭示內容所述之數個揭示具體實施例及其等效物中之任一者。電腦系統1000可為例如上網電腦的行動裝置。電腦系統1000可為例如無線智慧型手機的行動裝置。電腦系統1000可為桌上電腦。電腦系統1000可為手持讀取器。電腦系統1000可為伺服器系統。電腦系統1000可為超級電腦或高效運算系統。
在一具體實施例中，電子系統1000為包括能電氣耦接電子系統1000之各種組件之系統匯流排1020 的電腦系統。根據各種具體實施例，系統匯流排1020為單一匯流排或數個匯流排之任何組合。電子系統1000包括提供電力給積體電路1010的電壓源1030。在一些具體實施例中，電壓源1030通過系統匯流排1020供應電流給積體電路1010。
根據一具體實施例，積體電路1010電氣耦接至系統匯流排1020且包括任何電路或電路組合。在一具體實施例中，積體電路1010包括可為任何類型的處理器1012。如本文所使用的，處理器1012可意指任何類型的電路，例如但不限於微處理器、微控制器、圖形處理器、數位訊號處理器、或另一處理器。在一具體實施例中，處理器1012包括如本文所述具有無金屬框設計的矽橋或與其耦接。在一具體實施例中，在處理器的記憶體快取中發現SRAM具體實施例。可包含於積體電路1010中的其他類型電路為客製電路或特殊應用積體電路(ASIC)，例如通訊電路1014供使用於例如行動電話、智慧型手機、呼叫器、可攜式電腦、雙向收音機及類似電子系統的無線裝置，或用於伺服器的通訊電路。在一具體實施例中，積體電路1010包括晶粒上記憶體1016，例如靜態隨機存取記憶體(SRAM)。在一具體實施例中，積體電路1010包括嵌入式晶粒上記憶體1016，例如嵌入式動態隨機存取記憶體(eDRAM)。
在一具體實施例中，積體電路1010與後續積體電路1011互補。有用的具體實施例包括雙處理器 1013與雙通訊電路1015及雙晶粒上記憶體1017，例如SRAM。在一具體實施例中，雙積體電路1010包括嵌入式晶粒上記憶體1017，例如eDRAM。
在一具體實施例中，電子系統1000也包括外部記憶體1040，接著它可包括適合特定應用的一或更多記憶體元件，例如形式為RAM的主記憶體1042，一或更多硬碟1044及/或處理可移除式媒體1046(例如，軟碟、光碟(CD)、數位光碟(DVD)、快閃記憶體驅動器及本技藝習知其他可移除式媒體)的一或更多驅動器。根據一具體實施例，外部記憶體1040也可為嵌入式記憶體1048，例如晶粒堆疊中的第一晶粒。
在一具體實施例中，電子系統1000也包括顯示裝置1050，聲頻輸出1060。在一具體實施例中，電子系統1000包括輸入裝置，例如可為鍵盤、滑鼠、軌跡球、遊戲控制器、麥克風、語音辨識裝置、或輸入資訊於電子系統1000中之任何其他輸入裝置的控制器1070。在一具體實施例中，輸入裝置1070為相機。在一具體實施例中，輸入裝置1070為數位錄音機。在一具體實施例中，輸入裝置1070為相機及數位錄音機。
如本文所示，積體電路1010可實作於許多不同的具體實施例中，包括如根據數個揭示具體實施例及其等效物中之任一所述有具有無金屬框設計之矽橋的封裝基板，電子系統，電腦系統，製造積體電路的一或更多方法，以及製造包括有具有無金屬框設計之矽橋之封裝基板 的電子總成的一或更多方法，這是根據如各種具體實施例所述之數個揭示具體實施例及其經本技藝認定之等效物中之任一者。元件、材料、幾何、尺寸及操作順序都可改變以適合特定I/O耦接要求，包括用於嵌入處理器安裝基板之微電子晶粒的陣列接觸數目(array contact count)、陣列接觸組態，這是根據有具有無金屬框設計具體實施例及其等效物之矽橋的數個揭示封裝基板中之任一者。可包括一基礎基板，如圖10的虛線所示。也可包括被動裝置，也如圖10所示。
本發明的具體實施例包括針對用於半導體封裝之矽橋的無金屬框設計和所得矽橋及半導體封裝體。
在一具體實施例中，一種半導體結構包括有設置於其上之一絕緣層的一基板，該基板有一周界。一金屬化結構設置於該絕緣層上，該金屬化結構包括設置於一介電材料堆疊中的傳導性之佈線。一第一金屬護環設置於該介電材料堆疊中且包圍該傳導性之佈線。一第二金屬護環設置於該介電材料堆疊中且包圍該第一金屬護環。該介電材料堆疊的一無金屬區域包圍該第二金屬護環。該無金屬區域係鄰接該第二金屬護環和鄰接該基板之該周界地設置。
在一具體實施例中，該第一金屬護環或該第二金屬護環中之至少一者提供該金屬化結構的一密閉的密封。
在一具體實施例中，該半導體結構包括在該 第一金屬護環與該第二金屬護環之間設置於該介電材料堆疊中的數個金屬特徵。該等金屬特徵包括由下列各物組成之群組選出的一特徵：一對準標記、一虛擬特徵、以及一測試特徵。
在一具體實施例中，該第一金屬護環或該第二金屬護環中之至少一者包括由沿著一公共軸線對齊之數條金屬線及數個通孔交錯組成的一垂直堆疊。
在一具體實施例中，該金屬化結構的一最上層包括第一及第二複數個傳導墊於其上。
在一具體實施例中，該傳導性之佈線使該等第一複數個傳導墊與該等第二複數個傳導墊電氣耦接。
在一具體實施例中，該等第一及該等第二複數個傳導墊包括厚度大於約5微米的一銅層。
在一具體實施例中，該基板沒有設置於其中的半導體裝置。
在一具體實施例中，該基板為一單晶矽基板。
在一具體實施例中，該半導體結構更包括一龜裂，其設置於該介電材料堆疊之該無金屬區域中且擴散通過該第二金屬護環但是不通過該第一金屬護環。
在一具體實施例中，一種製造複數個矽橋晶粒之方法包括下列步驟：提供有複數個矽橋晶粒在其上的一晶圓。該等複數個矽橋晶粒中之每一者用數條無金屬刻劃線互相隔開。該方法也包括：藉由鋸切該晶圓的該等無 金屬刻劃線來單粒化該等複數個矽橋晶粒。在鋸切期間用一雙金屬護環保護該等複數個矽橋晶粒中之每一者。
在一具體實施例中，單粒化該等複數個矽橋晶粒的步驟涉及：在該雙金屬護環內提供有厚度大於約5微米之一最上面金屬層的複數個矽橋晶粒。
在一具體實施例中，單粒化該等複數個矽橋晶粒的步驟涉及：留下該等無金屬刻劃線的一部份以保留作為該等經單粒化之複數個矽橋晶粒中之每一者的一部份。
在一具體實施例中，該雙金屬護環的該等金屬護環中之至少一者在鋸切期間為該等複數個矽橋晶粒中之每一者提供一密閉的密封。
在一具體實施例中，鋸切該晶圓之該等無金屬刻劃線的步驟更涉及：在該等無金屬刻劃線中之一者中形成一龜裂，該龜裂擴散通過該雙金屬護環的一最外面金屬護環但是不通過該雙金屬護環的一最內面金屬護環。
在一具體實施例中，一種半導體封裝體包括包括設置於一半導體封裝基板內之一矽橋的一嵌入式多晶粒互連橋(EMIB)。該矽橋包括有一絕緣層設置於其上的一矽基板，該矽基板有一周界。一金屬化結構設置於該絕緣層上，該金屬化結構包括設置於一介電材料堆疊中的傳導性之佈線。一第一金屬護環設置於該介電材料堆疊中且包圍該傳導性之佈線。一第二金屬護環設置於該介電材料堆疊中且包圍該第一金屬護環。該介電材料堆疊的一無 金屬區域包圍該第二金屬護環。該無金屬區域係鄰接該第二金屬護環和鄰接該矽基板之該周界地設置。該半導體封裝體也包括第一及第二相鄰半導體晶粒，彼等設置於該半導體封裝基板上且藉由該矽橋之該金屬化結構的該傳導性之佈線互相電氣耦接。
在一具體實施例中，該第一半導體晶粒為一記憶體晶粒，以及該第二半導體晶粒為一邏輯晶粒。
在一具體實施例中，該矽橋的該第一金屬護環或該第二金屬護環中之至少一者提供該矽橋之該金屬化結構的一密閉的密封。
在一具體實施例中，該矽橋更包括在該第一金屬護環與該第二金屬護環之間設置於該介電材料堆疊中的數個金屬特徵，該等金屬特徵包括一特徵，例如但不限於對準標記、虛擬特徵或測試特徵。
在一具體實施例中，該矽橋的該第一金屬護環或該第二金屬護環中之至少一者包括由沿著一公共軸線對齊之數條金屬線及數個通孔交錯組成的一垂直堆疊。
在一具體實施例中，該矽橋之該金屬化結構的一最上層包括第一及第二複數個傳導墊於其上。該第一半導體晶粒附接至該等第一複數個傳導墊，以及該第二半導體晶粒附接至該等第二複數個傳導墊。
在一具體實施例中，該矽橋之該傳導性之佈線使該等第一複數個傳導墊與該等第二複數個傳導墊電氣耦接。
在一具體實施例中，該矽橋的該等第一及該等第二複數個傳導墊包括厚度大於約5微米的一銅層。
在一具體實施例中，該矽基板沒有設置於其中的半導體裝置。
在一具體實施例中，該矽橋更包括一龜裂，其設置於該矽橋之該介電材料堆疊之該無金屬區域中且擴散通過該第二金屬護環但是不通過該矽橋之該第一金屬護環。
302、304:第一、第二矽橋晶粒
306、308:外緣
310:內金屬護環
312:外金屬護環
314:交錯虛擬金屬特徵
316:微影對準標記
318:無金屬刻劃線
W1、W2:寬度

Claims (20)

  1. 一種半導體結構，其包含： 一基板，該基板具有於其上之一絕緣層，該基板具有一周界，並且該基板包含矽； 一金屬化結構，其於該絕緣層上，該金屬化結構包含於一介電材料堆疊中的傳導性之佈線； 一第一金屬護環，其於該介電材料堆疊中且連續的圍繞該傳導性之佈線； 一第二金屬護環，其於該介電材料堆疊中且連續的圍繞該第一金屬護環； 複數個交錯迷你護環，其在該第一金屬護環以及該第二金屬護環之間；以及 該介電材料堆疊的一無金屬區域，該無金屬區域包圍該第二金屬護環，該無金屬區域鄰接該第二金屬護環及鄰接該基板之該周界。
  2. 如請求項1的半導體結構，其中，該第一金屬護環或該第二金屬護環其中至少一者提供用於該金屬化結構的一密閉的密封。
  3. 如請求項1的半導體結構，其進一步包含： 一金屬特徵，該金屬特徵在該第一金屬護環與該第二金屬護環之間，該金屬特徵選自於由下列各者所組成之群組：一對準標記、一虛擬特徵、以及一測試特徵。
  4. 如請求項1的半導體裝置，其中，該第一金屬護環或該第二金屬護環其中至少一者包含一垂直堆疊之交錯的金屬線及通孔。
  5. 如請求項1的半導體結構，其中，該金屬化結構的一最上層包含在該最上層上的第一及第二複數個傳導墊。
  6. 如請求項5的半導體結構，其中，該傳導性之佈線使該等第一複數個傳導墊與該等第二複數個傳導墊電氣耦接。
  7. 如請求項5的半導體結構，其中，該等第一及該等第二複數個傳導墊包含具有大於約5微米之厚度的一銅層。
  8. 如請求項1的半導體結構，其中，該基板沒有半導體裝置於其中。
  9. 如請求項1的半導體結構，其中，該基板為一單晶矽基板。
  10. 如請求項1的半導體結構，該半導體結構進一步包含： 於該介電材料堆疊之該無金屬區域中之一龜裂，該龜裂擴散通過該第二金屬護環但是不通過該第一金屬護環。
  11. 一種半導體封裝體，其包含： 一嵌入式互連橋（EMIB），其包含在一半導體封裝基板內的一橋，該橋包含： 一基板，其具有一絕緣層於其上，該基板有一周界，並且該基板包含矽； 一金屬化結構，其於該絕緣層上，該金屬化結構包含於一介電材料堆疊中的傳導性之佈線； 一第一金屬護環，其於該介電材料堆疊中且連續的圍繞該傳導性之佈線； 一第二金屬護環，其於該介電材料堆疊中且連續的圍繞該第一金屬護環； 複數個交錯迷你護環，其在該第一金屬護環以及該第二金屬護環之間；以及 該介電材料堆疊的一無金屬區域，該無金屬區域包圍該第二金屬護環，該無金屬區域鄰接該第二金屬護環及鄰接該基板之該周界； 一第一半導體晶粒，其在該半導體封裝體基板上；以及 一第二半導體晶粒，其在該半導體封裝基板上，且相鄰該第一半導體晶粒，該第二半導體晶粒藉由該橋之該金屬化結構的該傳導性之佈線而電氣耦接至該第一半導體晶粒。
  12. 如請求項11的半導體封裝體，其中，該第一半導體晶粒為一記憶體晶粒，以及該第二半導體晶粒為一邏輯晶粒。
  13. 如請求項11的半導體封裝體，其中，該橋的該第一金屬護環或該第二金屬護環其中至少一者提供用於該橋之該金屬化結構的一密閉的密封。
  14. 如請求項11的半導體封裝體，該橋進一步包含： 在該第一金屬護環與該第二金屬護環之間的一金屬特徵，該金屬特徵選自於由下列各者組成之群組：一對準標記、一虛擬特徵、以及一測試特徵。
  15. 如請求項11的半導體封裝體，其中，該橋的該第一金屬護環或該第二金屬護環其中至少一者包含一垂直堆疊之交錯的金屬線及通孔。
  16. 如請求項11的半導體封裝體，其中，該橋之該金屬化結構的一最上層包含在該最上層上的第一及第二複數個傳導墊，其中，該第一半導體晶粒附接到該等第一複數個傳導墊，並且其中，該第二半導體晶粒附接到該等第二複數個傳導墊。
  17. 如請求項16的半導體封裝體，其中，該橋的該傳導性之佈線使該等第一複數個傳導墊電氣耦接至該等第二複數個傳導墊。
  18. 如請求項16的半導體封裝體，其中，該橋的該等第一及該等第二複數個傳導墊包含具有大於約5微米之厚度的一銅層。
  19. 如請求項11的半導體封裝體，其中，該基板沒有半導體裝置於其中。
  20. 如請求項11所述的半導體封裝體，該橋進一步包含： 於該橋之該介電材料堆疊之該無金屬區域中之一龜裂，該龜裂擴散通過該第二金屬護環但是不通過該橋之該第一金屬護環。
TW109130417A 2015-10-29 2016-08-19 針對用於半導體封裝之矽橋的無金屬框設計(二) TWI755052B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOPCT/US15/58074 2015-10-29
PCT/US2015/058074 WO2017074392A1 (en) 2015-10-29 2015-10-29 Metal-free frame design for silicon bridges for semiconductor packages

Publications (2)

Publication Number Publication Date
TW202111895A TW202111895A (zh) 2021-03-16
TWI755052B true TWI755052B (zh) 2022-02-11

Family

ID=58630827

Family Applications (2)

Application Number Title Priority Date Filing Date
TW109130417A TWI755052B (zh) 2015-10-29 2016-08-19 針對用於半導體封裝之矽橋的無金屬框設計(二)
TW105126641A TWI704657B (zh) 2015-10-29 2016-08-19 針對用於半導體封裝之矽橋的無金屬框設計

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW105126641A TWI704657B (zh) 2015-10-29 2016-08-19 針對用於半導體封裝之矽橋的無金屬框設計

Country Status (4)

Country Link
US (5) US10461047B2 (zh)
DE (1) DE112015007070T5 (zh)
TW (2) TWI755052B (zh)
WO (1) WO2017074392A1 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10461047B2 (en) 2015-10-29 2019-10-29 Intel Corporation Metal-free frame design for silicon bridges for semiconductor packages
US11430740B2 (en) * 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
US10217719B2 (en) * 2017-04-06 2019-02-26 Micron Technology, Inc. Semiconductor device assemblies with molded support substrates
US10700021B2 (en) * 2018-08-31 2020-06-30 Intel Corporation Coreless organic packages with embedded die and magnetic inductor structures
US11282761B2 (en) 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
TWI728561B (zh) * 2018-11-29 2021-05-21 台灣積體電路製造股份有限公司 半導體封裝件以及其製造方法
KR102601582B1 (ko) * 2018-12-11 2023-11-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11557541B2 (en) * 2018-12-28 2023-01-17 Intel Corporation Interconnect architecture with silicon interposer and EMIB
US10998262B2 (en) 2019-04-15 2021-05-04 Intel Corporation Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge
US11569172B2 (en) * 2019-08-08 2023-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US11049830B2 (en) * 2019-08-14 2021-06-29 International Business Machines Corporation Level shifting between interconnected chips having different voltage potentials
US11515317B2 (en) 2020-06-05 2022-11-29 Sandisk Technologies Llc Three-dimensional memory device including through-memory-level via structures and methods of making the same
WO2021247084A1 (en) * 2020-06-05 2021-12-09 Sandisk Technologies Llc Three-dimensional memory device including through-memory-level via structures and methods of making the same
US11398488B2 (en) 2020-06-05 2022-07-26 Sandisk Technologies Llc Three-dimensional memory device including through-memory-level via structures and methods of making the same
US11756871B2 (en) * 2020-09-15 2023-09-12 Sj Semiconductor (Jiangyin) Corporation Fan-out packaging structure and method
US11495535B2 (en) * 2020-12-17 2022-11-08 Advanced Micro Devices, Inc. Fuses to measure electrostatic discharge during die to substrate or package assembly
US20230035627A1 (en) * 2021-07-27 2023-02-02 Qualcomm Incorporated Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods
JP2023043036A (ja) * 2021-09-15 2023-03-28 キオクシア株式会社 半導体装置
CN115332220B (zh) * 2022-07-15 2024-03-22 珠海越芯半导体有限公司 一种实现芯片互连封装结构及其制作方法
KR20240045007A (ko) * 2022-09-29 2024-04-05 엘지이노텍 주식회사 반도체 패키지

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070102791A1 (en) * 2005-11-07 2007-05-10 Ping-Chang Wu Structure of multi-layer crack stop ring and wafer having the same
US20080265378A1 (en) * 2007-04-27 2008-10-30 Hsin-Hui Lee Scribe line layout design
US7642625B2 (en) * 2007-06-15 2010-01-05 Nec Electronics Corporation Method of evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having test element
TW201140792A (en) * 2010-01-29 2011-11-16 Stats Chippac Ltd Semiconductor device and method of forming thin profile WLCSP with vertical interconnect over package footprint
TW201145493A (en) * 2010-06-01 2011-12-16 Chipmos Technologies Inc Silicon wafer structure and multi-chip stack structure
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects
US20140097861A1 (en) * 2011-07-11 2014-04-10 Fujitsu Semiconductor Limited Semiconductor device and test method
TW201501239A (zh) * 2013-06-27 2015-01-01 Taiwan Semiconductor Mfg Co Ltd 內連線結構及形成內連線結構的方法
TW201532280A (zh) * 2014-02-07 2015-08-16 Taiwan Semiconductor Mfg 半導體結構及其製造方法
TW201539679A (zh) * 2014-03-07 2015-10-16 Bridge Semiconductor Corp 具有隔離件之散熱增益型線路板製作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008114655A (ja) 2006-11-01 2008-05-22 Denso Corp 車両用照明制御装置
US7893459B2 (en) * 2007-04-10 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structures with reduced moisture-induced reliability degradation
JP2008311465A (ja) 2007-06-15 2008-12-25 Nikon Corp Ｅｕｖ光源、ｅｕｖ露光装置および半導体デバイスの製造方法
KR20100101688A (ko) * 2008-04-15 2010-09-17 코토 테크놀로지 인코퍼레이티드 개선된 ｃ형 릴레이 및 그것을 이용한 패키지
US7993950B2 (en) * 2008-04-30 2011-08-09 Cavendish Kinetics, Ltd. System and method of encapsulation
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US20130050155A1 (en) * 2011-08-30 2013-02-28 Qualcomm Mems Technologies, Inc. Glass as a substrate material and a final package for mems and ic devices
EP2788280B1 (en) * 2011-12-07 2018-06-20 Georgia Tech Research Corporation Packaging compatible wafer level capping of mems devices
US9269664B2 (en) * 2012-04-10 2016-02-23 Mediatek Inc. Semiconductor package with through silicon via interconnect and method for fabricating the same
JP6057565B2 (ja) * 2012-07-04 2017-01-11 キヤノン株式会社 画像処理装置、画像処理装置の制御方法、およびプログラム
JP6061726B2 (ja) 2013-02-26 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置および半導体ウェハ
US9345184B2 (en) * 2013-09-27 2016-05-17 Intel Corporation Magnetic field shielding for packaging build-up architectures
US10461047B2 (en) * 2015-10-29 2019-10-29 Intel Corporation Metal-free frame design for silicon bridges for semiconductor packages

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070102791A1 (en) * 2005-11-07 2007-05-10 Ping-Chang Wu Structure of multi-layer crack stop ring and wafer having the same
US20080265378A1 (en) * 2007-04-27 2008-10-30 Hsin-Hui Lee Scribe line layout design
US7642625B2 (en) * 2007-06-15 2010-01-05 Nec Electronics Corporation Method of evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having test element
TW201140792A (en) * 2010-01-29 2011-11-16 Stats Chippac Ltd Semiconductor device and method of forming thin profile WLCSP with vertical interconnect over package footprint
TW201145493A (en) * 2010-06-01 2011-12-16 Chipmos Technologies Inc Silicon wafer structure and multi-chip stack structure
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects
US20140097861A1 (en) * 2011-07-11 2014-04-10 Fujitsu Semiconductor Limited Semiconductor device and test method
TW201501239A (zh) * 2013-06-27 2015-01-01 Taiwan Semiconductor Mfg Co Ltd 內連線結構及形成內連線結構的方法
TW201532280A (zh) * 2014-02-07 2015-08-16 Taiwan Semiconductor Mfg 半導體結構及其製造方法
TW201539679A (zh) * 2014-03-07 2015-10-16 Bridge Semiconductor Corp 具有隔離件之散熱增益型線路板製作方法

Also Published As

Publication number Publication date
US20230223361A1 (en) 2023-07-13
DE112015007070T5 (de) 2018-09-13
TW202111895A (zh) 2021-03-16
US20230238339A1 (en) 2023-07-27
WO2017074392A1 (en) 2017-05-04
TWI704657B (zh) 2020-09-11
US10916514B2 (en) 2021-02-09
US20210125942A1 (en) 2021-04-29
US20200013734A1 (en) 2020-01-09
US10461047B2 (en) 2019-10-29
TW201724410A (zh) 2017-07-01
US11626372B2 (en) 2023-04-11
US20180226364A1 (en) 2018-08-09
US12074121B2 (en) 2024-08-27

Similar Documents

Publication Publication Date Title
TWI755052B (zh) 針對用於半導體封裝之矽橋的無金屬框設計(二)
US11848259B2 (en) Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
US11676889B2 (en) Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US10128223B2 (en) Semiconductor device and manufacturing method thereof
US6661085B2 (en) Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US7972902B2 (en) Method of manufacturing a wafer including providing electrical conductors isolated from circuitry
TW202032748A (zh) 具有封裝面積縮減的高頻寬晶粒對晶粒互連
KR20120035719A (ko) 반도체 패키지 및 그 제조 방법
TWI581387B (zh) 封裝結構及其製法
TWI578476B (zh) 半導體封裝
US20230141447A1 (en) Semiconductor package, and method of manufacturing the same
KR20230043271A (ko) 반도체 칩 및 반도체 패키지
JP2021158336A (ja) パッケージシールドを含むパッケージエッジに対する新規ｗｌｃｓｐの信頼性の向上
US20240222330A1 (en) Semiconductor package
KR20110038561A (ko) 멀티칩 모듈들을 위한 개선된 전기적 연결들