CN106057748A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN106057748A
CN106057748A CN201610169905.0A CN201610169905A CN106057748A CN 106057748 A CN106057748 A CN 106057748A CN 201610169905 A CN201610169905 A CN 201610169905A CN 106057748 A CN106057748 A CN 106057748A
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row
chip
pad
semiconductor
pads
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CN201610169905.0A
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CN106057748B (zh
Inventor
陈盈志
周哲雅
林敏裕
杨家豪
储文彬
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明公开了一种半导体封装，该半导体封装包括：半导体祼芯片，具有第一祼芯片部分和第二祼芯片部分。钝化层位于该半导体祼芯片之上。第一PPI(钝化后互连)结构包括：多个第一和第二垫，分别布置在第一和第二排中。该第一和第二垫设置在该半导体祼芯片的该第一祼芯片部分上。第二PPI结构包括：多个第三和第四垫，分别布置在第三和第四排中。该第三和第四垫设置在该半导体祼芯片的该第二祼芯片部分之上。该第一垫之一和该第四垫之一通过第一接合线彼此耦接。该第二垫之一和该第三垫之一通过第二接合线彼此耦接。在本发明中，半导体封装通过两个彼此电性连接的祼芯片部分而增大其存储容量。

Description

半导体封装
技术领域
本发明涉及半导体封装结构，特别涉及一种用于半导体封装的祼芯片(die)至祼芯片线接合垫布置设计。
背景技术
近年来，相应于电子装置的高性能和多功能化，高容量半导体存储器的需求快速增加。一般地，若干增加半导体存储器存储容量的方法已经被广泛地使用。例如，增加半导体存储器存储容量的一种方法是增加半导体祼芯片(semiconductor die)的集成度。尽管增加半导体祼芯片集成度的方法能够轻易地增加半导体存储器的存储容量，但是显著地增加了开发和研究环境中的制造成本和时间消耗。
增加半导体存储器存储容量的另一种方法是将多个半导体存储器祼芯片安排进单个半导体封装中(如，多祼芯片半导体封装)。例如，多个半导体存储器祼芯片水平或垂直地居于单个半导体封装中。但是，因为需要改变封装基板的设计以相应于此种半导体存储器祼芯片布置，所以此种方法不可避免地增加制造成本。另外，由于此种封装基板的设计改变，也会增加封装尺寸。相应地，已知的多祼芯片半导体封装难以调整以适应电子装置的小型化。
如此，期望一种具有高容量的创新半导体存储器封装。
发明内容
有鉴于此，本发明提供了一种半导体封装，以增加其存储容量。
本发明提供了一种半导体封装，包括：第一半导体祼芯片，具有第一祼芯片部分、第二祼芯片部分以及切割道部分，该切割道部分位于该第一祼芯片部分和该第二祼芯片部分之间；钝化层，在该第一半导体祼芯片之上并且具有彼此相邻的第一区域和第二区域；第一钝化后互连结构，包括：布置在第一排中的多个第一垫以及布置在第二排中的多个第二垫，其中所述多个第一垫和所述多个第二垫设置在对应该第一祼芯片部分的该钝化层的该第一区域之上；第二钝化后互连结构，包括：设置在第三排中的多个第三垫以及设置在第四排中的多个第四垫，其中所述多个第三垫和所述多个第四垫设置在对应该第二祼芯片部分的该钝化层的该第一区域之上；第一接合线，具有两个端，分别耦接至所述多个第一垫之一和所述多个第四垫之一；以及第二接合线，具有两个端，分别耦接至所述多个第二垫之一和所述多个第三垫之一。
其中，该第一排、该第二排、该第三排和该第四排彼此平行。
其中，该第一排、该第二排、该第三排和该第四排平行于该切割道部分的延伸方向。
其中，该第一排平行于该第一祼芯片部分的一边缘，以及该第一排比该第二排更接近该边缘。
其中，该第二排比该第一排更接近该切割道部分。
其中，该第四排平行于该第二祼芯片部分的一边缘，以及该第四排比该第三排更接近该边缘。
其中，该第三排比该第四排更接近该切割道部分。
其中，所述多个第一垫的总数量等于所述多个第四垫的总数量，以及所述多个第二垫的总数量等于所述多个第三垫的总数量。
其中，该第一接合线具有的线接合高度大于该第二接合线具有的线接合高度。
其中，该第二钝化后互连结构进一步包括：多个第五垫，设置在对应该第二祼芯片部分的该钝化层中的该第二区域之上，并且电性连接至所述多个第三垫和所述多个第四垫。
其中，所述多个第五垫沿垂直于该第一排、该第二排、该第三排和该第四排的方向排列。
其中，该第一半导体祼芯片为随机存取存储器祼芯片。
其中，进一步包括：第一基板，该第一半导体祼芯片安装在该第一基板之上；第二基板，设置在该第一基板的下方；以及第二半导体祼芯片，插入在该第一和第二基板之间。
其中，该第一半导体祼芯片通过该第一基板电性连接至该第二半导体祼芯片。
其中，该第二半导体祼芯片电性连接至该第二基板。
其中，该第一半导体祼芯片不对齐于该第二半导体祼芯片，以便于该第一半导体祼芯片中的一部分悬于该第二半导体祼芯片之上。
其中，该第一半导体祼芯片不对齐于该第一基板，以便于该第一半导体祼芯片中的一部分悬于该第一基板之上。
以上的半导体封装中，半导体存储器祼芯片的两个祼芯片部分通过祼芯片至祼芯片线接合垫和祼芯片至祼芯片接合线而彼此电性连接，可以增加半导体封装的存储容量。
附图说明
图1A为半导体设备的一实施例的俯视图，其清楚地示出了一种典型的祼芯片至祼芯片线接合垫的布置设计，用于半导体设备。
图1B为图1A所示的半导体设备的侧面透视图。
图2A为具有图1A所示的半导体设备的半导体封装的实施例的俯视图。
图2B为图2A所示的半导体封装的侧面透视图。
图3为半导体封装的另一实施例的侧面透视图。
具体实施方式
在本申请说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异作为区分组件的方式，而是以组件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述包含了制造工艺，并且是出于公开的目的。但是应当理解，出于说明制造工艺和本公开的使用的目的而提供该描述，该描述不应被理解成具有限制性的意义。在附图或说明书中，相同或相似的组件使用相同或类似的符号来表示或标记。此外，出于简化和方便，可以放大附图中所示的组件的形状或厚度。此外，在附图中或在说明书中并没有示出或描述本领域公知的通用组件。
参考图1A和1B，图1A是半导体设备的典型实施例的俯视图，其明确地示出了一种祼芯片至祼芯片线接合垫(die-to-die wire bonding pad)的布置设计，该布置设计可用于半导体设备。图1B是图1A所示的半导体设备的侧面透视图。在本实施例中，该半导体设备包括：半导体祼芯片100，诸如RAM(Random AccessMemory，随机存取存储器)祼芯片。如图1A所示，该半导体祼芯片100包括：第一祼芯片部分100a、第二祼芯片部分100c和位于该第一祼芯片部分100a和该第二祼芯片部分100c之间的切割道(scribe line)部分100b。
在一个实施例中，通过把含有多个存储器祼芯片区域的晶圆(wafer)分割为单独的祼芯片来得到该半导体祼芯片100。例如，提供已有的已合格祼芯片(known good die，KGN)晶圆，该KGN晶圆具有多个由多条切割道定义的存储器祼芯片区域。然后，分割KGN晶圆为单独的祼芯片，此处，某些单独的祼芯片包括：两个相邻的由切割道分开的存储器祼芯片区域。也就是，单独的祼芯片包括：切割道以及两个祼芯片区域，该两个祼芯片区域由半导体祼芯片100的切割道部分100b、第一祼芯片部分100a和第二祼芯片部分100c定义。
在本实施例中，该半导体设备进一步包括：钝化层102，覆盖半导体祼芯片100的顶面，如图1B所示。该钝化层102可以由非有机材料形成，例如，氧化硅，氮化硅，氮氧化硅，非掺杂硅玻璃(undoped silicate glass，USG)等等。在本实施例中，如图1A所示，该钝化层102具有第一区域102a和相邻于该第一区域102a的第二区域102b。另外，该钝化层102可以包括：位于钝化层102中的多个开口(未示出)，这些开口对应于该第一区域102a，以暴露第一祼芯片部分100a的接触垫101’(即输入/输出(I/O)垫)以及第二祼芯片部分100c的接触垫103’(即I/O垫)。一般地，这些I/O垫包括：信号垫、电源垫和接地垫。
在本实施例中，该半导体设备进一步包括：在钝化层102上的第一钝化后互连(post-passivation interconnect，即PPI，如此命名的原因在于其在钝化层之后形成)结构和第二PPI结构。该第一和第二PPI结构分别对应半导体祼芯片100的第一祼芯片部分100a和第二祼芯片100c部分。在一个实施例中，该第一PPI结构包括：多个PPI垫101、多个电源/接地垫114、多个第一垫104、多个第二垫106以及用于连接这些垫101、104、106和114的多条重分布线115。所述PPI垫101设置在钝化层102的第一区域102a之上并且对齐于第一祼芯片部分100a的接触垫101’。所述PPI垫101设置在一条接近并且平行于第一祼芯片部分100a的边缘的直线中，并且通过钝化层102相应地电性连接至第一祼芯片部分100a的接触垫101’。所述电源/接地垫114设置在钝化层102的第二区域102b之上。另外，所述电源/接地垫114通过重分布线115电性连接至某些PPI垫101，这些PPI垫101耦接至第一祼芯片部分100a的电源/接地垫(即接触垫)。
所述第一垫104和第二垫106设置在钝化层102中的第一区域102a上，并且分别布置在第一排(tier)201和第二排202中。在一个实施例中，第一排201和第二排202彼此平行，并且没有垫设置在第一排201和第二排202之间。另外，第一排201和第二排202平行于切割道部分100b的延伸方向。在一个实施例中，第一排201平行于第一祼芯片部分100a中平行于切割道部分100b的延伸方向的边缘，从而第一排201比第二排202更接近第一祼芯片部分100a的该边缘，以及第二排202比第一排201更接近切割道部分100b。另外，所述第一垫104和第二垫106通过重分布线115电性连接至某些PPI垫101，并且这些PPI垫101耦接至该第一祼芯片部分100a的信号垫(即接触垫)。在本实施例中，某些第一垫104可以对应某些第二垫106。另外，某些第一垫104可以对齐或者不对齐于某些第二垫106。在本实施例中，第一垫104的总数量等于或不同于第二垫106的总数量。例如，第一垫104的总数量大于第二垫106的总数量。注意，图1A所示的垫101、104、106和114的数量为示例，而本发明不限制于此。
在一个实施例中，该第二PPI结构包括：多个PPI垫103、多个电源/接地垫116、多个第三垫108、多个第四垫110、多个第五垫112和用于连接这些垫103、108、110、112和114的多条重分布线117。所述PPI垫103设置在钝化层102中的第一区域102a上，并且对齐于第二祼芯片部分100c的接触垫103’。所述PPI垫103设置在接近并且平行于第二祼芯片部分100c的边缘的直线中，并且通过钝化层102对应地电性连接至第二祼芯片部分100c的接触垫103’。所述电源/接地垫116设置在钝化层102的第二区域102b之上。另外，所述电源/接地垫116通过重分布线117电性连接至某些PPI垫103，这些PPI垫103耦接至第二祼芯片部分100c的电源/接地垫(即接触垫)。
所述第三垫108和第四垫110设置在钝化层102的第一区域102a之上并且分别设置在第三排203和第四排204中。在一个实施例中，第三排203和第四排204平行于第一排201和第二排202，并且没有垫位于第三排203和第四排204之间。另外，第三排203和第四排204也平行于切割道部分100b的延伸方向。在一个实施例中，第四排204平行第二祼芯片部分100c中平行于切割道部分100b的延伸方向的边缘，从而第四排204比第三排203更接近第二祼芯片部分100c的该边缘，以及第三排203比第四排204更接近切割道部分100b。另外，第三垫108和第四垫110通过重分布线117电性连接至某些PPI垫103，这些PPI垫103耦接至第二祼芯片部分100c的信号垫(即接触垫)。在本实施例中，某些第三垫108可以对应某些第四垫110。另外，某些第四垫110可以对齐或不对齐于对应的第三垫108。在本实施例中，第四垫110的总数量等于或不同于第三垫108的总数量。例如，第四垫110的总数量大于第三垫108的总数量。在本实施例中，第一垫104的总数量等于第四垫110的总数量，以及第二垫106的总数量等于第三垫108的总数量。
第五垫112设置在钝化层102的第二区域102b之上。在一个实施例中，第五垫112沿垂直于第一排201、第二排202、第三排203和第四排204的方向排列。另外，第五垫112通过重分布线117电性连接至某些PPI垫103，这些PPI垫103耦接至第二祼芯片部分100c的信号垫(即接触垫)。所述第五垫112通过重分布线117电性连接至第三垫108和第四垫110。另外，注意，图1A中所示的垫103、108、110、112和116的数量为示例，并且本发明不限制于此。
在本实施例中，该半导体设备进一步包括：多条第一接合线120和多条第二接合线130(在图1A中没有示出，但是在图2A中示出)。所述第一和第二接合线120和130用来作为用于半导体祼芯片100中的第一祼芯片部分100a和第二祼芯片部分100c的祼芯片至祼芯片接合线。此中，为了简化图形，在图1B中仅描绘了一条第一接合线120和一条第二接合线130。如图1B所示，第一接合线120具有两个端，分别耦接至所述第一垫104之一和所述第四垫110之一。类似地，第二接合线130具有两端，分别耦接至所述第二垫106之一以及所述第三垫108之一。在本实施例中，每条第一接合线120具有线接合高度H1，并且每条第二接合线130具有线接合高度H2。另外，线接合高度H1大于线接合高度H2以避免短路问题。在第一和第二接合线120和130分别耦接在第一和第四垫104、110之间以及第二和第三垫106、108之间后，第一祼芯片部分100a的接触垫101’可以通过第一和第二PPI结构以及第一和第二接合线120和130，电性连接至第二祼芯片部分100c的接触垫103’。
参考图2A和2B，图2A为俯视图，示出了半导体封装600的典型实施例，该半导体封装600具有图1A所示的半导体设备，以及图2B为图2A所示的半导体封装600的侧面透视图。在本实施例中，半导体封装600包括：第一基板300，例如封装基板，具有设备连接面300a(如图2B所示)。图1A所示的半导体设备中的半导体祼芯片100贴合到第一基板300的设备连接面300a之上。此中，为了简化图形，如图1A中所示的重分布线115和117均没有在图2A中描绘。在一个实施例中，该第一基板300可以包括：嵌入于该第一基板300中的导电线路(没有示出)以及在该第一基板300上的I/O垫301和303。在一个实施例中，该导电线路用于直接贴合在第一基板300之上的半导体祼芯片100的I/O连接。半导体祼芯片100的第一祼芯片部分100a和第二祼芯片部分100c的电路通过第一导电路径和第二导电路径电性连接至第一基板300的电路，该第一导电路径由第二PPI结构中的第五垫112、接合线(binding wire)203和第一基板300的I/O垫301所构建，该第二导电路径由第二PPI结构的电源/接地垫116、接合线203和第一基板300的I/O垫301所构建。此中，为了简化图形，仅描述了由第五垫112、接合线203和I/O垫301所构建的第一导电路径，如图2B所示。另外，如图2A所示，仅描述了某些导电路径。
在本实施例中，该半导体封装600进一步包括：第二半导体祼芯片400，设置在第一基板300的下方。在一个实施例中，第二半导体祼芯片400可以为存储控制器祼芯片，用于控制贴合在第一基板300之上的半导体设备。在本实施例中，该半导体封装600进一步包括：第二基板500，设置在第二半导体祼芯片400的下方，从而第二半导体祼芯片400插入于第一基板300和第二基板500之间。在一个实施例中，第二基板500(例如印刷线路板(PCB))具有设备连接面500a(如图2B所示)。该第二半导体祼芯片400贴合在该第二基板500的设备连接面500a上。在一个实施例中，导电线路为直接贴合在第二基板500之上的第二半导体祼芯片400的I/O连接。该第二半导体祼芯片400的电路通过覆晶技术电性连接至第二基板500的电路。另外，第一基板300的电路通过导电路径电性连接至第二基板500的电路，该导电路径由第一基板300的I/O垫303、接合线305和第二基板500的指状结构(finger)501所构建，从而半导体祼芯片100通过第一基板300电性连接至祼芯片400。此中，为了简化图形，如图2B所示，仅描绘了由第一基板300的I/O垫303、接合线305和第二基板500的指状结构501所构建的导电路径。
参考图3，为半导体封装600’的典型实施例的侧面透视图。以下实施例中描述的组件中，相同或类似于先前已参考图2A和2B已描述了的组件的，出于简洁而省略。在本实施例中，半导体封装600’类似于图2A和2B所示的半导体封装600。在本实施例中，半导体祼芯片100与第一基板300和第二半导体祼芯片400不对齐(misaligned)，从而半导体祼芯片100的一部分悬于第一基板300和第二半导体祼芯片400之上。在这种情形中，第二半导体祼芯片400和第一基板300具有的尺寸可以等于或大于祼芯片100具有的尺寸。根据前面的实施例，由于半导体存储器祼芯片包括：通过分割已有的晶圆而提供的两个祼芯片部分，以及由于该两个祼芯片部分通过祼芯片至祼芯片线接合垫以及祼芯片至祼芯片接合线而彼此电性连接，因此半导体存储器封装的存储容量可以增加两倍，而无需增加半导体存储器祼芯片的集成度。因此，可以降低开发和研究环境中的制造成本和时间消耗。另外，由于半导体存储器祼芯片的电路包括：两个祼芯片部分，能够经由设置在半导体封装存储器祼芯片中的其中一个祼芯片部分(如，第二祼芯片部分)上的I/O垫(如第一垫)而电性连接至封装基板(即第一基板)的电路，所以不需要改变封装基板的设计。因此，可以排除设计新封装基板的成本并维持封装尺寸。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (17)

1.一种半导体封装，其特征在于，包括：
第一半导体祼芯片，具有第一祼芯片部分、第二祼芯片部分以及切割道部分，该切割道部分位于该第一祼芯片部分和该第二祼芯片部分之间；
钝化层，在该第一半导体祼芯片之上并且具有彼此相邻的第一区域和第二区域；
第一钝化后互连结构，包括：布置在第一排中的多个第一垫以及布置在第二排中的多个第二垫，其中所述多个第一垫和所述多个第二垫设置在对应该第一祼芯片部分的该钝化层的该第一区域之上；
第二钝化后互连结构，包括：设置在第三排中的多个第三垫以及设置在第四排中的多个第四垫，其中所述多个第三垫和所述多个第四垫设置在对应该第二祼芯片部分的该钝化层的该第一区域之上；
第一接合线，具有两个端，分别耦接至所述多个第一垫之一和所述多个第四垫之一；以及
第二接合线，具有两个端，分别耦接至所述多个第二垫之一和所述多个第三垫之一。
2.如权利要求1所述的半导体封装，其特征在于，该第一排、该第二排、该第三排和该第四排彼此平行。
3.如权利要求2所述的半导体封装，其特征在于，该第一排、该第二排、该第三排和该第四排平行于该切割道部分的延伸方向。
4.如权利要求2所述的半导体封装，其特征在于，该第一排平行于该第一祼芯片部分的第一边缘，以及该第一排比该第二排更接近该第一边缘。
5.如权利要求4所述的半导体封装，其特征在于，该第二排比该第一排更接近该切割道部分。
6.如权利要求2所述的半导体封装，其特征在于，该第四排平行于该第二祼芯片部分的第二边缘，以及该第四排比该第三排更接近该第二边缘。
7.如权利要求6所述的半导体封装，其特征在于，该第三排比该第四排更接近该切割道部分。
8.如权利要求1所述的半导体封装，其特征在于，所述多个第一垫的总数量等于所述多个第四垫的总数量，以及所述多个第二垫的总数量等于所述多个第三垫的总数量。
9.如权利要求1所述的半导体封装，其特征在于，该第一接合线具有的线接合高度大于该第二接合线具有的线接合高度。
10.如权利要求1所述的半导体封装，其特征在于，该第二钝化后互连结构进一步包括：多个第五垫，设置在对应该第二祼芯片部分的该钝化层中的该第二区域之上，并且电性连接至所述多个第三垫和所述多个第四垫。
11.如权利要求10所述的半导体封装，其特征在于，所述多个第五垫沿垂直于该第一排、该第二排、该第三排和该第四排的方向排列。
12.如权利要求1所述的半导体封装，其特征在于，该第一半导体祼芯片为随机存取存储器祼芯片。
13.如权利要求1所述的半导体封装，其特征在于，进一步包括：
第一基板，该第一半导体祼芯片安装在该第一基板之上；
第二基板，设置在该第一基板的下方；以及
第二半导体祼芯片，插入在该第一和第二基板之间。
14.如权利要求13所述的半导体封装，其特征在于，该第一半导体祼芯片通过该第一基板电性连接至该第二半导体祼芯片。
15.如权利要求13所述的半导体封装，其特征在于，该第二半导体祼芯片电性连接至该第二基板。
16.如权利要求13所述的半导体封装，其特征在于，该第一半导体祼芯片不对齐于该第二半导体祼芯片，以便于该第一半导体祼芯片中的一部分悬于该第二半导体祼芯片之上。
17.如权利要求13所述的半导体封装，其特征在于，该第一半导体祼芯片不对齐于该第一基板，以便于该第一半导体祼芯片中的一部分悬于该第一基板之上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022166133A1 (zh) * 2021-02-05 2022-08-11 长鑫存储技术有限公司 封装基板及具有其的半导体结构

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
KR102612009B1 (ko) * 2017-12-11 2023-12-11 삼성전자주식회사 평행하게 배열된 패드들을 포함하는 반도체 메모리
US11508415B2 (en) * 2021-03-15 2022-11-22 Transcend Information, Inc. Semiconductor memory package structure and semiconductor memory system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060224814A1 (en) * 2005-02-28 2006-10-05 Sung-Hoon Kim Semiconductor memory devices having controllable input/output bit architectures and related methods
US20090321904A1 (en) * 2008-06-27 2009-12-31 Sony Corporation Semiconductor device and semiconductor integrated circuit
US20110062581A1 (en) * 2009-09-17 2011-03-17 Hynix Semiconductor Inc. Semiconductor package
US20140306354A1 (en) * 2013-04-10 2014-10-16 MuSeob SHIN Semiconductor package
TW201513244A (zh) * 2013-09-18 2015-04-01 China Wafer Level Csp Co Ltd 晶片封裝結構及形成方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11195669A (ja) * 1998-01-05 1999-07-21 Oki Electric Ind Co Ltd 半導体素子の接続構造
SG93278A1 (en) * 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
WO2002082540A1 (fr) * 2001-03-30 2002-10-17 Fujitsu Limited Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe
JP2003023138A (ja) * 2001-07-10 2003-01-24 Toshiba Corp メモリチップ及びこれを用いたｃｏｃデバイス、並びに、これらの製造方法
JP2003338519A (ja) * 2002-05-21 2003-11-28 Renesas Technology Corp 半導体装置及びその製造方法
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
JP4570868B2 (ja) * 2003-12-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置
US7425767B2 (en) * 2004-07-14 2008-09-16 Megica Corporation Chip structure with redistribution traces
US20060258051A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Method and system for solder die attach
US7397121B2 (en) * 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
JP5115258B2 (ja) * 2008-03-17 2013-01-09 セイコーエプソン株式会社 圧電デバイスおよび電子機器
KR100935854B1 (ko) * 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
JP2011003764A (ja) * 2009-06-19 2011-01-06 Renesas Electronics Corp 半導体装置及びその製造方法
US8391018B2 (en) * 2009-09-28 2013-03-05 Qualcomm Incorporated Semiconductor die-based packaging interconnect
JP2012114241A (ja) * 2010-11-25 2012-06-14 Renesas Electronics Corp 半導体チップおよび半導体装置
JP5968713B2 (ja) * 2012-07-30 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060224814A1 (en) * 2005-02-28 2006-10-05 Sung-Hoon Kim Semiconductor memory devices having controllable input/output bit architectures and related methods
US20090321904A1 (en) * 2008-06-27 2009-12-31 Sony Corporation Semiconductor device and semiconductor integrated circuit
US20110062581A1 (en) * 2009-09-17 2011-03-17 Hynix Semiconductor Inc. Semiconductor package
US20140306354A1 (en) * 2013-04-10 2014-10-16 MuSeob SHIN Semiconductor package
TW201513244A (zh) * 2013-09-18 2015-04-01 China Wafer Level Csp Co Ltd 晶片封裝結構及形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022166133A1 (zh) * 2021-02-05 2022-08-11 长鑫存储技术有限公司 封装基板及具有其的半导体结构

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