JP2012114241A - 半導体チップおよび半導体装置 - Google Patents
半導体チップおよび半導体装置 Download PDFInfo
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- JP2012114241A JP2012114241A JP2010261967A JP2010261967A JP2012114241A JP 2012114241 A JP2012114241 A JP 2012114241A JP 2010261967 A JP2010261967 A JP 2010261967A JP 2010261967 A JP2010261967 A JP 2010261967A JP 2012114241 A JP2012114241 A JP 2012114241A
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Abstract
【解決手段】本発明にかかる半導体チップ10は、半導体チップ10に設けられると共に、少なくとも一つの電極パッド6を備える電極パッド群1と、半導体チップ10に設けられる少なくとも一つの電極パッドであって、電極パッド6から出力される信号と同じ信号を出力可能である電極パッド7を備える電極パッド群2と、を備える。そして第1の電極パッド群の一の電極パッドおよび第2の電極パッド群の一の電極パッドうち、当該信号が供給される他の半導体チップの他の電極パッドと距離が近い方の電極パッドが、他の半導体チップの当該他の電極パッドと接続される。
【選択図】図1
Description
以下、図面を参照して本発明の実施の形態について説明する。
図1は、本発明の実施の形態1にかかる半導体チップを示す図である。図1に示す半導体チップ10は、電極パッド群(第1の電極パッド群)1と、電極パッド群(第2の電極パッド群)2と、電極パッド群(第3の電極パッド群)3、4と、内部回路5とを備える。なお、それぞれの電極パッド群は、少なくともひとつの電極パッドを備えていればよく、複数の電極パッドを備えていることに本発明の権利範囲は限定されない。しかし、以下の説明では、全体的な接続関係や構造を把握しやすくするため、電極パッド群という言葉を用いて本発明の実施の形態を説明していく。
次に、本発明の実施の形態2について説明する。図14は、本実施の形態にかかる半導体チップを示す図である。本実施の形態にかかる半導体チップ410は、内部回路5から出力された信号を、電極パッド群1および電極パッド群2のいずれか一方へ選択的に出力するためのセレクタ回路430と、設定回路422と、CPU421とを備える。これ以外の構成は実施の形態1の場合と同様であるので、同一の構成要素については同一の符号を付し重複した説明を省略する。
2 第2の電極端子群
3、4 電極端子群
5 内部回路
6、7、8、9 電極パッド
10、30 半導体チップ
20、40 パッケージ基板
50 実装基板
Claims (16)
- 半導体チップに設けられ、少なくとも一つの第1の電極パッドと、
前記半導体チップに設けられる少なくとも一つの電極パッドであって、前記第1の電極パッドから出力される信号と同じ信号を出力可能である第2の電極パッドと、
を備え、
前記第1の電極パッドおよび前記第2の電極パッドのうち、前記信号が供給される他の半導体チップの他の電極パッドと距離が近い方の電極パッドが、前記他の半導体チップの前記他の電極パッドと接続される、
半導体チップ。 - 前記第1の電極パッドは前記半導体チップの一辺に設けられ、前記第2の電極パッドは前記一辺とは異なる一辺に設けられている、請求項1に記載の半導体チップ。
- 前記信号を前記第1の電極パッドまたは前記第2の電極パッドの少なくとも一方に出力する内部回路をさらに備える、請求項1に記載の半導体チップ。
- 前記半導体チップはパッケージ基板上に設けられ、前記パッケージ基板とは別の他のパッケージ基板上に設けられた前記他の半導体チップと共に実装基板上に配置される、請求項1に記載の半導体チップ。
- 前記半導体チップはパッケージ基板上に設けられ、前記他の半導体チップは前記パッケージ基板上で前記半導体チップ上に積層されている、請求項1に記載の半導体チップ。
- 前記他の半導体チップと当該半導体チップとが水平方向に配置されており、前記第1および第2の電極パッドのうちのいずれか一方の電極パッドが前記他の電極パッドと接続される場合、
前記他の半導体チップと前記半導体チップとが積層されて互いに接続される場合には、前記第1および第2の電極パッドのうち、前記半導体チップと前記他の半導体チップとが水平方向に配置されて互いに接続される際に前記他の電極パッドと接続されていない方の電極パッドが前記他の電極パッドと接続される、
請求項1に記載の半導体チップ。 - 前記半導体チップは、更に、
前記内部回路から出力された信号を入力し、当該信号を前記第1の電極パッドまたは前記第2の電極パッドのいずれか一方に出力するセレクタ回路を備える、
請求項3に記載の半導体チップ。 - 前記セレクタ回路は、
出力端子が前記第1の電極パッドに接続され、一方の入力端子に前記内部回路から出力された信号が供給され、他方の入力端子に設定回路から出力された第1の信号が供給される第1のAND回路と、
出力端子が前記第2の電極パッドに接続され、一方の入力端子に、前記第1のAND回路の一方の入力端子に供給される前記内部回路から出力された信号と同一の信号が供給され、他方の入力端子に前記設定回路から出力された第2の信号が供給される第2のAND回路と、を備え、
前記セレクタ回路は、前記設定回路から出力される前記第1の信号と前記第2の信号の信号レベルを変化させることで前記他の半導体チップとの接続される電極パッドを切り替える、
請求項7のいずれか一項に記載の半導体チップ。 - 前記設定回路は、ユーザプログラムによって設定された電極パッドの情報に基づき、前記第1の信号と前記第2の信号の信号レベルを決定する、請求項8に記載の半導体チップ。
- 前記設定回路は、
前記第1の信号の信号レベルを決定するための第1のヒューズと、
前記第2の信号の信号レベルを決定するための第2のヒューズと、を備える、
請求項8に記載の半導体チップ。 - 前記第1の電極パッドおよび前記第2の電極パッドの少なくとも一方から出力される前記信号はアドレス信号およびコマンド信号である、請求項1に記載の半導体チップ。
- 前記第1の電極パッドは前記半導体チップの一辺に設けられ、前記第2の電極パッドは前記一辺とは異なる一辺に設けられ、さらに前記第1の電極パッドが設けられている前記一辺または前記第2の電極パッドが設けられている前記異なる一辺のいずれか一方の辺に、少なくとも一つの第3の電極パッドが設けられており、
前記第3の電極パッドから出力される信号は、データ信号である、
請求項11に記載の半導体チップ。 - 請求項12に記載の半導体チップと、
当該半導体チップと接続される他の半導体チップと、を備える半導体装置であって、
前記半導体チップが備える前記第3の電極パッドは、前記第1の電極パッドが設けられている辺に設けられており、
前記他の半導体チップはメモリチップであると共に、一辺にアドレス信号およびコマンド信号が供給される電極パッドが、当該一辺と対向する辺にデータ信号が供給される電極パッドがそれぞれ配置され、
前記半導体チップと前記他の半導体チップとが、それぞれ水平方向に配置されて互いに接続される場合、前記半導体チップの前記第1の電極パッドと、前記他の半導体チップが備えるアドレス信号およびコマンド信号が供給される前記電極パッドとが接続され、
前記半導体チップと前記メモリチップとが、それぞれ積層されて互いに接続される場合、前記半導体チップの前記第2の電極パッドと、前記メモリチップが備えるアドレス信号およびコマンド信号が供給される前記電極パッドとが接続される、
半導体装置。 - 請求項1に記載の半導体チップと、
前記半導体チップを実装する第1のパッケージ基板と、
前記他の半導体チップと、
前記他の半導体チップを実装する第2のパッケージ基板と、
前記半導体チップが実装された第1のパッケージ基板と前記他の半導体チップが実装された第2のパッケージ基板とを実装する実装基板と、を備え、
前記半導体チップと前記他の半導体チップは、前記第1のパッケージ基板、実装基板、および前記第2のパッケージ基板を介して接続される、
半導体装置。 - 請求項1に記載の半導体チップと、
前記半導体チップと積層されて実装される前記他の半導体チップと、
前記半導体チップおよび前記他の半導体チップを実装する第3のパッケージ基板と、を備え、
前記半導体チップと前記他の半導体チップは前記第3のパッケージ基板を介して接続される、
半導体装置。 - パッケージ基板と、
前記パッケージ基板上に設けられた第1の電極パッドと、
前記パッケージ基板上に設けられ、前記第1の電極パッドとは異なる第2の電極パッドと、
前記パッケージ基板上に設けられた半導体チップと、
前記半導体チップ上に設けられた第3の電極パッドと、
前記半導体チップ上に設けられ、前記第3の電極パッドから出力される信号と同じ信号が出力可能であり、前記第3の電極パッドとは異なる第4の電極パッドと、
を有し、
前記パッケージ基板上の前記第1の電極パッドは前記半導体チップ上の前記第3の電極パッドとボンディングワイヤーで接続される一方で、前記パッケージ基板上の前記第2の電極パッドは、前記半導体チップ上の前記第4の電極パッドと接続されていないことを特徴とする半導体装置。
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