JP5968713B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5968713B2 JP5968713B2 JP2012168541A JP2012168541A JP5968713B2 JP 5968713 B2 JP5968713 B2 JP 5968713B2 JP 2012168541 A JP2012168541 A JP 2012168541A JP 2012168541 A JP2012168541 A JP 2012168541A JP 5968713 B2 JP5968713 B2 JP 5968713B2
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- Prior art keywords
- pad group
- wiring board
- bonding
- semiconductor chip
- electrode
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 237
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 119
- 238000000034 method Methods 0.000 description 55
- 229920005989 resin Polymers 0.000 description 48
- 239000011347 resin Substances 0.000 description 48
- 238000007789 sealing Methods 0.000 description 31
- 239000011162 core material Substances 0.000 description 24
- 239000000758 substrate Substances 0.000 description 22
- 239000000047 product Substances 0.000 description 20
- 101100372017 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UPS3 gene Proteins 0.000 description 13
- 101150066274 gep4 gene Proteins 0.000 description 13
- 101150009585 GEP3 gene Proteins 0.000 description 11
- 101100048630 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UPS2 gene Proteins 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 238000000465 moulding Methods 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000032683 aging Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 239000007795 chemical reaction product Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 2
- 240000005523 Peganum harmala Species 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000005350 fused silica glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005243 fluidization Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
従来、フリップチップボンディング用に設計されたハイエンド品、例えば通信用メモリ向け高速SRAM(Static Random Access Memory)が形成された半導体チップをローエンド品として流用する際は、フリップチップボンディング方式を採用して半導体製品の組立てを行っていた。しかし、フリップチップボンディング方式を採用した半導体製品の組立てはプロセスが複雑であり、また、半導体製品が少量多品種であることから、組立てコストが高くなる。
実施の形態による配線基板(パッケージ基板)に半導体チップが搭載された半導体装置について図1〜図3を用いて説明する。図1は、実施の形態によるワイヤボンディング方式を採用した半導体装置の構成を示す要部平面図である。図2は、実施の形態によるワイヤボンディング方式を採用した半導体装置の構成を示す要部断面図(図1のA−A線に沿った断面図)である。図3は、実施の形態によるワイヤボンディング方式を採用した半導体装置の構成を示す要部断面図(図1のB−B線に沿った断面図)である。
半導体チップSCは、半導体素子が形成された主面と、主面と反対側の裏面とを有し、配線基板ISの上面ISxと半導体チップSCの裏面とが対向して、配線基板ISの上面ISxに搭載されている。
配線基板ISは、その厚さ方向と交差する平面形状が第1辺L1と、第1辺L1と反対側の第2辺L2と、第1辺L1に直交する第3辺L3と、第3辺L3と反対側の第4辺L4とからなる四角形になっており、例えばその平面寸法は15mm×13mmである。配線基板ISは、多層配線構造から成り、実施の形態では4つの配線層ML1,ML2,ML3,ML4を有している。
半導体チップSCの主面に形成された複数の電極パッドEPと、配線基板ISの上面ISxに形成された複数のボンディングパッドBLとが、複数の導電性ワイヤCWによってそれぞれ電気的に接続されている(図2および図3には、複数の導電性ワイヤCWのうちの一部を記載)。導電性ワイヤCWには、例えば23μmφの金線を用いる。導電性ワイヤCWは、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング(ボールボンディング)法により、半導体チップSCの主面に配置された電極パッドEPおよび配線基板ISの上面ISxに配置されたボンディングパッドBLに接続される。
半導体チップSCおよび複数の導電性ワイヤCWは、配線基板ISの上面ISx上に形成された樹脂封止体RSによって封止されている。樹脂封止体RSは、高流動化を図る目的として、例えばフェノール系硬化剤および多数(例えば質量分率で80〜90%)のフィラー(例えば溶融シリカ)等が添加されたエポキシ系の熱硬化性絶縁樹脂で形成されている。
配線基板ISの下面ISyには複数の外部端子SBが形成されており、これら外部端子SBは、複数のバンプ・ランドBLRとそれぞれ電気的に、かつ機械的に接続されている。外部端子SBとしては、鉛を実質的に含まない鉛フリー半田組成の半田バンプ、例えばSn−3[wt%]Ag−0.5[wt%]Cu組成の半田バンプが用いられる。
実施の形態による配線基板(パッケージ基板)について図4〜図8を用いて説明する。図4は、実施の形態による配線基板を構成する上層絶縁層の表面(第1面)を示す要部平面図である。図5は、実施の形態による配線基板を構成するコア材(基材)の表面(第2面)を示す要部平面図である。図6は、実施の形態による配線基板を構成するコア材(基材)の裏面(第3面)を示す要部平面図である。図7は、実施の形態による配線基板を構成する下層絶縁層の表面(第4面)を示す要部平面図である。図8は、実施の形態による配線基板の上面に形成された複数のボンディングパッドの一部を拡大して示す要部平面図である。
ところで、フリップチップボンディング用に設計された半導体チップでは、半導体チップの周縁部(半導体チップの縁から内側の一部)だけでなく中央部にも複数の電極パッドが配置されている。そのため、半導体チップの中央部に位置する電極パッドと配線基板の主面に形成されたボンディングパッドとを接続する導電性ワイヤは、半導体チップの周縁部に位置する電極パッドと配線基板の主面に形成されたボンディングパッドとを接続する導電性ワイヤよりも長くなってしまう。導電性ワイヤが長くなると、半導体チップおよび導電性ワイヤを樹脂封止する際に、ワイヤ流れが生じて、隣り合う導電性ワイヤが接触する危険性がある。
まず、半導体ウエハを準備する。半導体ウエハの主面の各チップ領域には、複数の半導体素子が形成されている。続いて、半導体ウエハの主面と反対側の裏面を研削することにより、半導体ウエハの厚さを所定の厚さまで薄くする。
次に、図10および図11に示すように、半導体チップが搭載される複数のチップ搭載領域を有する多数個取り配線基板ISAを準備する。多数個取り配線基板ISAは、その厚さ方向と交差する平面形状が2つの長辺と2つの短辺とからなる四角形(長方形)になっており、1個の半導体チップが搭載される1個のブロック(前述の図1〜図3を用いて説明した配線基板ISに該当)がマトリックス状に区画形成された基板である。図11には、1個の配線基板ISが、平面上の縦方向に3個、横方向に14個配列された多数個取り配線基板ISAを例示している。
次に、図12に示すように、半導体チップSCの主面に露出した複数の電極パッドEP(前述の図1参照)と、多数個取り配線基板ISAのチップ搭載領域の周囲に形成された複数のボンディングパッドBLとを、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング法(ボールボンディング法)により、複数の導電性ワイヤCWを用いてそれぞれ電気的に接続する。導電性ワイヤCWには、例えば23μmφの金線を用いる。
次に、図13および図14に示すように、半導体チップSCを搭載した多数個取り配線基板ISAの上面ISAxのみを樹脂封止体RS(図14では、樹脂封止体RSを透視して示す)によって封止する。封止には、例えば成型金型を備えるモールド装置を用いる。まず、モールド装置の下金型に、複数の半導体チップSCが搭載された多数個取り配線基板ISAを設置する。続いて、上金型と下金型により多数個取り配線基板ISAを固定した後、樹脂タブレットをプレヒータで加熱し、樹脂粘度を下げてから液状化した封止用樹脂を成型金型内へ圧送する。続いて、成型金型内に充填された封止用樹脂を重合反応により硬化させた後、上金型と下金型とを開けて、封止用樹脂で覆われた多数個取り配線基板ISAを取り出す。
次に、不要な封止用樹脂を除去し、さらに、例えば175℃の温度で2〜8時間の熱処理(焼き入れ、ポストキュアベーク)を行って重合反応を完成させる。これにより、複数の半導体チップSCの一部(上面および側面)、および複数の導電性ワイヤCWなどが多数個取り配線基板ISAの上面ISAx上を被覆する樹脂封止体RSによって封止される。
次に、図17に示すように、多数個取り配線基板ISAを構成する絶縁層IDの表面に形成された複数のバンプ・ランドBLRにそれぞれ外部端子SBを接続する。外部端子SBは、例えばボール状の半田剤をボール供給法で供給した後、熱処理を施すことによって形成される。この熱処理は200℃以上、例えば240〜250℃の温度で数秒間行われる。
次に、図18に示すように、多数個取り配線基板ISAをダイシングラインに沿ってダイシングして、半導体装置SMを個々に分割する。その後、製品規格に沿って選別し、さらに最終外観検査を経て製品(半導体装置SM)が完成する。
A2 第2領域
BL ボンディングパッド(電極パッド、ボンドフィンガー)
BLR バンプ・ランド(電極パッド)
C コア材(基材)
Cx 表面(第2面)
Cy 裏面(第3面)
CL 仮想中心線
CW 導電性ワイヤ
DF 接着剤(接着層、ダイパッド材)
EP 電極パッド
G GND配線
GBL1 第1ボンディングパッド群
GBL2 第2ボンディングパッド群
GBL3 第3ボンディングパッド群
GBL4 第4ボンディングパッド群
GEP1 第1電極パッド群
GEP2 第2電極パッド群
GEP3 第3電極パッド群
GEP4 第4電極パッド群
ID 絶縁層(下層絶縁層)
ILD,ILU 保護膜
IS 配線基板(パッケージ基板)
ISx 上面(主面、表面、第1面)
ISy 下面(実装面、裏面、第4面)
ISA 多数個取り配線基板
ISAx 上面(主面、表面)
ISAy 下面(実装面、裏面)
ISB 多数個取り配線基板
ISBx 上面(主面、表面)
IU 絶縁層(上層絶縁層)
L1 第1辺
L2 第2辺
L3 第3辺
L4 第4辺
ML1 配線層(第1配線層)
ML2 配線層(GND配線層、第2配線層)
ML3 配線層(第3配線層)
ML4 配線層(第4配線層)
RS 樹脂封止体(封止樹脂)
S 信号配線
SB 外部端子(バンプ電極、半田ボール)
SC 半導体チップ
SM 半導体装置
VD スルーホール
VI 貫通孔(ビア)
VU スルーホール
Claims (11)
- 上面、前記上面とは反対側の下面、第1辺、前記第1辺と対向する第2辺、前記第1および第2辺に交差する第3辺、並びに前記第3辺と対向する第4辺を有する配線基板と、
主面、前記主面とは反対側の裏面、第1長辺、前記第1長辺と対向する第2長辺、前記第1および第2長辺に交差する第1短辺、並びに前記第1短辺と対向する第2短辺を有し、前記裏面と前記配線基板の前記上面とを対向させて前記配線基板の前記上面に接着剤を介して搭載された半導体チップと、
を含む半導体装置であって、
前記配線基板は、第1配線層を含み、
前記第1配線層は、平面視において、前記配線基板の前記第1辺から前記第2辺へ向かう方向に延在する複数の配線を有し、かつ前記第3辺から前記第4辺へ向かう方向に延在する配線を有しておらず、
前記複数の配線は、平面視において、前記半導体チップと重なり、かつ前記第1辺から前記第2辺へ向かう方向に延在する第1配線と、前記半導体チップと重なり、かつ前記第2辺から前記第1辺へ向かう方向に延在する第2配線と、前記配線基板の前記第1辺と前記半導体チップの前記第1長辺との間に設置された第1ビアと、前記配線基板の前記第2辺と前記半導体チップの前記第2長辺との間に設置された第2ビアと、を含み、
前記配線基板の前記上面には、
チップ搭載領域の外側で、前記半導体チップの前記第1長辺と前記配線基板の前記第1辺との間に、前記配線基板の前記第1辺と平行して、前記半導体チップの前記第1長辺側から、複数のボンディングパッドからなる第1ボンディングパッド群と、複数のボンディングパッドからなる第2ボンディングパッド群とが形成され、
前記チップ搭載領域の外側で、前記半導体チップの前記第2長辺と前記配線基板の前記第2辺との間に、前記配線基板の前記第2辺と平行して、前記半導体チップの前記第2長辺側から、複数のボンディングパッドからなる第3ボンディングパッド群と、複数のボンディングパッドからなる第4ボンディングパッド群とが形成され、
前記半導体チップの前記主面には、
前記半導体チップの前記第1長辺と平行して、前記半導体チップの前記第1長辺側から、複数の電極パッドからなる第1電極パッド群と、複数の電極パッドからなる第2電極パッド群とが形成され、
前記半導体チップの前記第2長辺と平行して、前記半導体チップの前記第2長辺側から、複数の電極パッドからなる第3電極パッド群と、複数の電極パッドからなる第4電極パッド群とが形成され、
前記第2電極パッド群は、平面視において前記第1電極パッド群と前記第4電極パッド群との間に設置され、
前記第1電極パッド群から前記第2電極パッド群までの長さが、前記第1短辺が延在する方向において前記第2電極パッド群から前記第4電極パッド群までの長さより大きく、
前記第2電極パッド群は、前記第2短辺よりも前記第1短辺の近くに配置された第1パッド群と、前記第1短辺よりも前記第2短辺の近くに配置された第2パッド群と、を含み、
前記第1パッド群は、前記第2パッド群の最も近くに位置する第1パッドと、前記第1パッドとの間に他のパッドを介在せずに位置する第2パッドと、を含み、
前記第2パッド群は、前記第1パッド群の最も近くに位置する第3パッドを含み、
前記第1パッドから前記第3パッドまでの長さは、前記第1長辺の延在する方向に沿って前記第1パッドから前記第2パッドまでの長さよりも大きく、
前記第1ボンディングパッド群に属する第1ボンディングパッドと、前記第1電極パッド群に属する第4パッドとが、第1導電性ワイヤにより電気的に接続され、
前記第2ボンディングパッド群に属する第2ボンディングパッドと、前記第2電極パッド群に属する第5パッドとが、第2導電性ワイヤにより電気的に接続され、
前記第3ボンディングパッド群に属する第3ボンディングパッドと、前記第3電極パッド群に属する第6パッドとが、第3導電性ワイヤにより電気的に接続され、
前記第4ボンディングパッド群に属する第4ボンディングパッドと、前記第4電極パッド群に属する第7パッドとが、第4導電性ワイヤにより電気的に接続され、
前記第2導電性ワイヤの長さが前記第1導電性ワイヤの長さよりも大きく、
前記第4導電性ワイヤの長さが前記第3導電性ワイヤの長さよりも大きく、
前記配線基板の前記第1配線は、一端が前記第2ボンディングパッドに接続され、他端が前記第2ビアに接続されており、
前記配線基板の前記第2配線は、一端が前記第4ボンディングパッドに接続され、他端が前記第1ビアに接続されている。 - 請求項1記載の半導体装置において、
前記第1ボンディングパッド群は、前記配線基板の前記第1辺と平行して一列に配置された複数のボンディングパッドから構成され、
前記第2ボンディングパッド群は、前記第1ボンディングパッド群と前記配線基板の前記第1辺との間に、前記配線基板の前記第1辺と平行して一列に配置された複数のボンディングパッドから構成され、
前記第3ボンディングパッド群は、前記配線基板の前記第2辺と平行して一列に配置された複数のボンディングパッドから構成され、
前記第4ボンディングパッド群は、前記第3ボンディングパッド群と前記配線基板の前記第2辺との間に、前記配線基板の前記第2辺と平行して一列に配置された複数のボンディングパッドから構成される。 - 請求項1記載の半導体装置において、
前記第1電極パッド群は、前記半導体チップの前記第1長辺と平行し、かつ前記半導体チップの前記第1長辺と近接して、一列に配置された複数のパッドから構成され、
前記第2電極パッド群は、前記半導体チップの前記第1長辺と平行し、一列に配置された複数のパッドから構成され、
前記第3電極パッド群は、前記半導体チップの前記第2長辺と平行し、かつ前記半導体チップの前記第2長辺と近接して、一列に配置された複数のパッドから構成され、
前記第4電極パッド群は、前記第3電極パッド群と前記第2電極パッド群との間に、前記半導体チップの前記第2長辺と平行し、一列に配置された複数のパッドから構成される。 - 請求項1記載の半導体装置において、
前記第1電極パッド群から前記第2電極パッド群までの長さは、前記第1短辺の延在する方向において前記第3電極パッド群から前記第4電極パッド群までの長さと実質的に等しい。 - 請求項1記載の半導体装置において、
前記第1ボンディングパッド群から前記第2ボンディングパッド群までの長さは、前記第1短辺が延在する方向において前記第3ボンディングパッド群から前記第4ボンディングパッド群までの長さと実質的に等しい。 - 請求項1記載の半導体装置において、
前記第1導電性ワイヤ、前記第2導電性ワイヤ、前記第3導電性ワイヤおよび前記第4導電性ワイヤは金線である。 - 請求項1記載の半導体装置において、
前記配線基板は、更に、第2配線層を含み、
前記第2配線層は、平面視において前記配線基板の前記第3辺から前記第4辺へ向かう方向に延在する第3配線と、平面視において前記配線基板の前記第1辺から前記第2辺へ向かう方向に延在する第4配線と、を有し、
前記第3配線の長さは前記第4配線の長さより大きい。 - 請求項7記載の半導体装置において、
断面視において、前記第1配線層と前記第2配線層との間に第3配線層を有し、
前記第3配線層はGND配線を有する。 - 請求項1記載の半導体装置において、
前記第1ボンディングパッド群、前記第2ボンディングパッド群、前記第3ボンディングパッド群および前記第4ボンディングパッド群にそれぞれ属する複数のボンディングパッドにおいて、信号配線に繋がるボンディングパッドの両側に、GND配線に繋がるボンディングパッドが配置されている。 - 請求項1記載の半導体装置において、
前記配線基板は、前記下面に配置された複数の外部電極を有し、
前記複数の外部電極は、平面視において前記配線基板の前記第1辺と前記半導体チップの前記第1長辺との間に設置された第1外部電極と、平面視において前記配線基板の前記第2辺と前記半導体チップの前記第2長辺との間に設置された第2外部電極と、を含み、
前記第1ビアは、前記第1外部電極と電気的に接続されており、
前記第2ビアは、前記第2外部電極と電気的に接続されている。 - 請求項1記載の半導体装置において、
前記第4電極パッド群は、平面視において前記第2電極パッド群と前記第3電極パッド群との間に設置され、
前記第3電極パッド群から前記第4電極パッド群までの長さが、前記第1短辺が延在する方向において前記第2電極パッド群から前記第4電極パッド群までの長さより大きく、
前記第4電極パッド群は、前記第2短辺よりも前記第1短辺の近くに配置された第3パッド群と、前記第1短辺よりも前記第2短辺の近くに配置された第4パッド群と、を含み、
前記第3パッド群は、前記第4パッド群の最も近くに位置する第8パッドと、前記第8パッドとの間に他のパッドを介在せずに位置する第9パッドと、を含み、
前記第4パッド群は、前記第3パッド群の最も近くに位置する第10パッドを含み、
前記第8パッドから前記第10パッドまでの長さは、前記第1長辺の延在する方向に沿って前記第8パッドから前記第9パッドまでの長さよりも大きい。
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