JP4754201B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4754201B2 JP4754201B2 JP2004298611A JP2004298611A JP4754201B2 JP 4754201 B2 JP4754201 B2 JP 4754201B2 JP 2004298611 A JP2004298611 A JP 2004298611A JP 2004298611 A JP2004298611 A JP 2004298611A JP 4754201 B2 JP4754201 B2 JP 4754201B2
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- JP
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- Prior art keywords
- pad
- pads
- group
- ground
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Description
直線状に並べられた複数のパッドを含む半導体チップであって、当該半導体チップは前記基板の前記開口部から前記複数のパッドが露出するように前記基板に実装され、前記複数のパッドは、第1のパッド群と当該第1のパッド群との間に前記複数のパッドのうちの残りのいかなるパッドも挟み込むことなく前記第1のパッド群に隣接して配置される第2のパッド群とを含み、当該第1及び第2の
パッド群の各々は、電源パッドとグランドパッドと2つの信号パッドとを含む、前記半導体チップと、
前記第1のパッド群を前記第1の接続端子群のうちの対応する複数の端子群に接続する第1の配線群と、
前記第2のパッド群を前記第2の接続端子群のうちの対応する複数の端子群に接続する第2の配線群と、を備え、
前記第1の領域及び前記第2の領域は、前記第1の配線群が第1の方向に延伸し、前記第2の配線群が前記第1の方向と反対の第2の方向に延伸するように配置され、
前記第1のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第1の方向に延伸し、
前記第2のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第2の方向に延伸することを特徴とする半導体装置を提供する。
Claims (6)
- 開口部を含む基板であって、前記開口部は、当該開口部を挟んで対向する第1及び第2の領域によって規定され、前記基板は、前記第1の領域に配置された第1の接続端子群と前記第2の領域に配置された第2の接続端子群とをさらに備える、前記基板と、
直線状に並べられた複数のパッドを含む半導体チップであって、当該半導体チップは前記基板の前記開口部から前記複数のパッドが露出するように前記基板に実装され、前記複数のパッドは、第1のパッド群と当該第1のパッド群との間に前記複数のパッドのうちの残りのいかなるパッドも挟み込むことなく前記第1のパッド群に隣接して配置される第2のパッド群とを含み、当該第1及び第2の
パッド群の各々は、電源パッドとグランドパッドと2つの信号パッドとを含む、前記半導体チップと、
前記第1のパッド群を前記第1の接続端子群のうちの対応する複数の端子群に接続する第1の配線群と、
前記第2のパッド群を前記第2の接続端子群のうちの対応する複数の端子群に接続する第2の配線群と、を備え、
前記第1の領域及び前記第2の領域は、前記第1の配線群が第1の方向に延伸し、前記第2の配線群が前記第1の方向と反対の第2の方向に延伸するように配置され、
前記第1のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第1の方向に延伸し、
前記第2のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第2の方向に延伸することを特徴とする半導体装置。 - 前記複数のパッドは、第3のパッド群と、前記第2のパッド群と前記第3のパッド群とに挟まれた第4のパッド群とをさらに含み、前記第3及び第4のパッド群の各々は、電源パッドとグランドパッドと2つの信号パッドとを含み、前記第3のパッド群を前記第2の接続端子群のうちの対応する複数の端子群に接続する第3の配線群と、前記第4のパッド群を前記第1の接続端子群のうちの対応する複数の端子群に接続する第4の配線群とをさらに含むことを特徴とする請求項1に記載の半導体装置。
- 前記第3のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第2の方向に延伸し、
前記第4のパッド群に含まれる全てのパッドから延伸する全ての配線は前記第1の方向に延伸することを特徴とする請求項2に記載の半導体装置。 - 前記第1及び第2のパッド群の夫々において、前記電源パッドと前記グランドパッドとが、前記2つの信号パッドの間にはさまれていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは、複数の入出力回路を含み、前記第1及び第2のパッド群の夫々の前記2つの信号パッドは、前記複数の入出力回路のうちの2つの入出力回路にそれぞれ対応して電気的に接続され、前記第1及び第2のパッド群の夫々の前記電源パッドと前記グランドパッドの各々は、前記2つの入出力回路に共通に電気的に接続されることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップ上の全ての前記電源パッドと前記グランドパッドの総数を、前記半導体チップ上に配置可能な前記複数のパッドの総数で除した値が、0.4よりも大きいことを特徴とする請求項1に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004298611A JP4754201B2 (ja) | 2004-10-13 | 2004-10-13 | 半導体装置 |
US11/247,215 US8362614B2 (en) | 2004-10-13 | 2005-10-12 | Fine pitch grid array type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004298611A JP4754201B2 (ja) | 2004-10-13 | 2004-10-13 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006114595A JP2006114595A (ja) | 2006-04-27 |
JP4754201B2 true JP4754201B2 (ja) | 2011-08-24 |
Family
ID=36179878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004298611A Expired - Fee Related JP4754201B2 (ja) | 2004-10-13 | 2004-10-13 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8362614B2 (ja) |
JP (1) | JP4754201B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008060215A (ja) * | 2006-08-30 | 2008-03-13 | Elpida Memory Inc | 半導体装置 |
KR101211683B1 (ko) * | 2008-12-31 | 2012-12-12 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP2010192680A (ja) * | 2009-02-18 | 2010-09-02 | Elpida Memory Inc | 半導体装置 |
US9123713B2 (en) * | 2010-11-24 | 2015-09-01 | Tessera, Inc. | Lead structures with vertical offsets |
JP2012209296A (ja) * | 2011-03-29 | 2012-10-25 | Elpida Memory Inc | 半導体集積回路装置 |
KR20150100388A (ko) | 2014-02-25 | 2015-09-02 | 삼성전자주식회사 | 메모리 모듈의 모듈 탭 영역에서의 선택적 리세스드 레퍼런스 플레인 구조 및 그에 따른 선택적 리세스드 레퍼런스 플레인 형성방법 |
JP6272173B2 (ja) * | 2014-07-31 | 2018-01-31 | 京セラ株式会社 | 配線基板 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3299342B2 (ja) * | 1993-06-11 | 2002-07-08 | 株式会社日立製作所 | 半導体メモリモジュール |
JPH0738011A (ja) * | 1993-06-29 | 1995-02-07 | Hitachi Ltd | 半導体集積回路装置 |
US5604710A (en) * | 1994-05-20 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Arrangement of power supply and data input/output pads in semiconductor memory device |
US5714801A (en) * | 1995-03-31 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor package |
JPH10284678A (ja) * | 1997-04-03 | 1998-10-23 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6890796B1 (en) * | 1997-07-16 | 2005-05-10 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected |
JP3480291B2 (ja) * | 1998-01-08 | 2003-12-15 | 日立電線株式会社 | 半導体装置及び電子装置 |
JP2001185576A (ja) | 1999-12-27 | 2001-07-06 | Hitachi Ltd | 半導体装置 |
KR100408391B1 (ko) * | 2000-06-09 | 2003-12-06 | 삼성전자주식회사 | 전원 배선을 개선한 볼그리드 어레이 패키지 반도체 장치 |
JP2002217377A (ja) * | 2001-01-18 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US7323772B2 (en) * | 2002-08-28 | 2008-01-29 | Micron Technology, Inc. | Ball grid array structures and tape-based method of manufacturing same |
-
2004
- 2004-10-13 JP JP2004298611A patent/JP4754201B2/ja not_active Expired - Fee Related
-
2005
- 2005-10-12 US US11/247,215 patent/US8362614B2/en active Active
Also Published As
Publication number | Publication date |
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JP2006114595A (ja) | 2006-04-27 |
US8362614B2 (en) | 2013-01-29 |
US20060081972A1 (en) | 2006-04-20 |
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