JP2010192680A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010192680A JP2010192680A JP2009035546A JP2009035546A JP2010192680A JP 2010192680 A JP2010192680 A JP 2010192680A JP 2009035546 A JP2009035546 A JP 2009035546A JP 2009035546 A JP2009035546 A JP 2009035546A JP 2010192680 A JP2010192680 A JP 2010192680A
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Abstract
【解決手段】半導体チップ1の上面に追加基板2a及び追加基板2bが設けられている。各追加基板2a、2bに形成された第1の電源用追加配線層10d及び第1のグランド用追加配線層10sは半導体チップ1上に所定の導電領域を形成している。第1の電源配線40C1dあるいは第1のグランド配線40C1sは追加配線層10d、10sを介して接続されている。第2の電源配線40C2d及び第2のグランド配線40C2sはDQ系信号配線40CDQに対して引出方向が同一方向であり帰還電流経路を形成している。第2の電源配線40C2d及び第2のグランド配線40C2sはDQ系信号配線40CDQに対して近接して配置されている。
【選択図】図6
Description
次に、図面を参照しながら本発明を実施するための形態について説明する。
[半導体装置の構成]
本実施形態の半導体装置は、図7に示すように、配線基板2の上面(半導体チップ搭載側)に封止樹脂5にて封止された半導体チップ1を有する。本実施形態の半導体チップ1の平面形状は矩形であり、辺1Q、辺1Qと対向した側の辺1A、辺1Qと辺1Aとを結ぶ辺1d、辺1Qと辺1Aとを結び、かつ辺1dと対向した側の辺1sとを有する。
[電気的接続関係]
次に、図6を参照しながら、データ出力用回路7a、データ出力用回路7aを除くその他の回路7b、各電極パッド20、各接続ランド30、各電源配線、及び各グランド配線の電気的な接続関係について説明する。なお、DQ系パッド列20Qは、データの入出力用のパッド列であり、データ入出力系パッド列、あるいは第1のパッド列と呼称する場合がある。また、CA系パッド列20Aは、コマンド−アドレス用のパッド列であり、コマンド−アドレス系パッド列、あるいは第2のパッド列と呼称する場合がある。
・データ出力用回路
データ出力用回路7aは、第2の電源用パッド20Q2d、DQ系信号用パッド20QDQ及び第2のグランド用パッド20Q2sに接続されている。データ出力用回路7aには後述するように、第2の電源配線40C2d及び第2のグランド配線40C2sから第2の電源電位及び第2のグランド電位が供給される。
・データ出力用回路を除くその他の回路
他の回路7bは、第1の電源用パッド20Q1d及び第1のグランド用パッド20Q1s、CA系信号用パッド20ACAに接続されている。他の回路7bには、後述するように、第1の電源用追加配線層10dを経由して第1の電源配線40C1dからの第1の電源電位が供給され、かつ第1のグランド用追加配線層10sを経由して第1のグランド配線40C1sからの第1のグランド電位が供給される。
・DQ系パッド列−接続パッド−DQ系信号配線、第2の電源/グランド配線
まず、DQ系パッド列20Qと、接続ランド30と、DQ系信号配線あるいは第2の電源配線/グランド配線と、の接続関係について説明する。
・CA系パッド列−接続パッド−各配線
次に、CA系パッド列20Aと、接続ランド30と、各配線との接続関係について説明する。
・第1の電源用配線−接続ランド−追加配線層
次に、第1の電源配線40C1d、第1の電源用接続ランド30L1d及び第1の電源用追加配線層10dの配置関係について説明する。
・第1のグランド用配線−接続ランド−追加配線層
次に、第1のグランド配線40C1s、第1のグランド用接続ランド30L1s、第1のグランド用追加配線層10sの配置関係について説明する。
[半導体装置の動作]
次に、以上のような構成を特徴とする本発明の半導体装置の動作について図5、図11〜図15を用いて説明する。
[1]外部端子204
↓
[2]基板配線パターン(第1の電源配線240C1d:配線幅が減少した部分(図中A部)、及び破線で示す細長いパターン(図中B部)を含む)
↓
[3]接続ランド230
↓
[4]ボンディングワイヤ206
↓
[5]電極パッド220
一方、図11に示す本実施形態の電流経路は、以下のとおりである。
[1’]外部端子4
↓
[2’]基板配線パターン(第1の電源配線40C1d:ベタパターンに近い太さであり、配線幅が減少した部分(図中A’部)は含まない)
↓
[3’]接続ランド30L1d
↓
[4’]複数のボンディングワイヤ6
↓
[5’]第1の電源用追加配線層10d(ベタパターン)
↓
[6’]ボンディングワイヤ6
↓
[7’]電極パッド20
図5に示す構成の場合、[2]基板配線パターンにおいて、上記電流経路中に配線幅が減少した部分(図中A部)、及び破線で示す細長いパターン(図中B部)が存在する。これに対して、図11に示す本発明の[2’]基板配線パターンでは、電流経路となっている配線パターンにおいては、配線幅が減少した部分(図中A’部)や細長いパターン部分が含まれておらず、ベタパターンに近い太さを有する。従って、基板上での配線インピーダンスは、図11に示す本発明の構成のほうが図5に示す本発明に関連する技術よりも低くなる。
[半導体装置の製造プロセス]
次に、本発明の半導体装置の製造プロセスについて、図16〜図20を参照して説明する。
(第2の実施形態)
次に、図22に本発明の他の実施形態に係る半導体装置の半導体チップ周辺部概略図を示す。また、図23に、図22に示す半導体装置の縦断面図を示す。
1a パッケージ外形
2 配線基板
2a 追加基板
2b 追加基板
2c 追加基板(多層基板)
3 ビア
4 外部端子
5 封止樹脂
6 ボンディングワイヤ
7a データ出力用回路
7b データ出力用回路を除く他の回路
10d 第1の電源用追加配線層
10s 第1のグランド用追加配線層
20 電極パッド
20P パッド列
20A CA系パッド列
20ACA CA系信号用パッド
20A1d 第1の電源用パッド
20A1s 第1のグランド用パッド
20Q DQ系パッド列
20QDQ DQ系信号用パッド
20Q1d 第1の電源用パッド
20Q1s 第1のグランド用パッド
20Q2d 第2の電源用パッド
20Q2s 第2のグランド用パッド
30 接続ランド
30LCA CA系信号用接続ランド
30LDQ DQ系信号用接続ランド
30L1d 第1の電源用接続ランド
30L1s 第1のグランド用接続ランド
30L2d 第2の電源用接続ランド
30L2s 第2のグランド用パッド
40CCA CA系信号配線
40CDQ DQ系信号配線
40C1d 第1の電源配線
40C1s 第1のグランド配線
40C2d 第2の電源配線
40C2s 第2のグランド配線
40P 配線パターン
40W 信号配線
R1 第1の経路
R2 第2の経路
Claims (6)
- 配線基板と、
前記配線基板上に実装され、データ出力用回路及び前記データ出力用回路を除く他の回路を有する半導体チップと、を備え、
前記データ出力用回路を除く他の回路には、前記半導体チップ上の所定の導電領域を経由する第1の経路で前記配線基板からの第1の電源電位又は第1のグランド電位が供給され、
前記データ出力用回路には、該データ出力用回路から前記配線基板に出力されるデータ信号の帰還電流経路を形成する第2の経路で前記配線基板からの第2の電源電位又は第2のグランド電位が供給される半導体装置。 - 配線基板と、
前記配線基板上に実装され、データ出力用回路及び前記データ出力用回路を除く他の回路を有する半導体チップと、
前記半導体チップ上に配置された配線層と、を備え、
前記データ出力用回路を除く他の回路には、前記配線層を含む第1の経路で前記配線基板から第1の電源電位又は第1のグランド電位が供給され、
前記データ出力用回路には、該データ出力用回路から前記配線基板に出力されるデータ信号の帰還電流経路を形成する第2の経路で前記配線基板から第2の電源電位又は第2のグランド電位が供給される半導体装置。 - 配線基板と、
前記配線基板上に実装され、データ出力用回路及び前記データ出力用回路を除く他の回路を有する半導体チップと、
前記半導体チップ上に配置された配線層と、
前記データ出力用回路へのデータ信号の入出力に用いられるデータ信号配線と、
前記データ出力用回路に第2の電源電位を供給するための第2の電源配線及び前記データ出力用回路に第2のグランド電位を供給するための第2のグランド配線と、を備え、
前記データ出力用回路からの前記第2の電源配線及び前記第2のグランド配線は、前記データ出力用回路からの前記データ信号配線の引出方向に沿った方向に引き出されており、
前記データ出力用回路を除く他の回路には、前記配線層を含む第1の経路で前記配線基板から第1の電源電位又は第1のグランド電位が供給され、
前記データ出力用回路には、前記第2の電源配線及び前記第2のグランド配線からなる第2の経路で前記配線基板から第2の電源電位又は第2のグランド電位が供給される半導体装置。 - 前記配線層は、前記第1の電源電位を供給する電源用配線層及び前記第1のグランド電位を供給するグランド用配線層を含み、前記電源用配線層及び前記グランド用配線層は、半導体チップ上に積層して形成されている請求項2または3に記載の半導体装置。
- 前記配線層は、前記第1の電源電位を供給する電源用配線層及び前記第1のグランド電位を供給するグランド用配線層を含み、前記電源用配線層及び前記グランド用配線層は、半導体チップ上の同一面上に配置されている半導体装置。
- 前記配線基板上に形成された前記第1の電源電位を供給する第1の電源配線と、前記配線基板上に形成された前記第1のグランド電位を供給する第1のグランド配線と、を有し、
前記第1の電源配線と前記配線層とは複数のボンディングワイヤで接続され、かつ前記第1のグランド配線と前記配線層とは複数のボンディングワイヤで接続されている半導体装置。
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US12/707,996 US8243465B2 (en) | 2009-02-18 | 2010-02-18 | Semiconductor device with additional power supply paths |
US13/463,317 US20130114223A1 (en) | 2009-02-18 | 2012-05-03 | Semiconductor device |
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100950511B1 (ko) | 2009-09-22 | 2010-03-30 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리 |
KR100935854B1 (ko) | 2009-09-22 | 2010-01-08 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리 |
US9136197B2 (en) | 2010-09-16 | 2015-09-15 | Tessera, Inc. | Impedence controlled packages with metal sheet or 2-layer RDL |
US8853708B2 (en) | 2010-09-16 | 2014-10-07 | Tessera, Inc. | Stacked multi-die packages with impedance control |
US8581377B2 (en) | 2010-09-16 | 2013-11-12 | Tessera, Inc. | TSOP with impedance control |
US8786083B2 (en) | 2010-09-16 | 2014-07-22 | Tessera, Inc. | Impedance controlled packages with metal sheet or 2-layer RDL |
JP2012104707A (ja) * | 2010-11-11 | 2012-05-31 | Elpida Memory Inc | 半導体パッケージ |
US8405214B2 (en) * | 2011-08-12 | 2013-03-26 | Nanya Technology Corp. | Semiconductor package structure with common gold plated metal conductor on die and substrate |
US8867231B2 (en) * | 2012-01-13 | 2014-10-21 | Tyco Electronics Corporation | Electronic module packages and assemblies for electrical systems |
KR102043369B1 (ko) * | 2012-11-21 | 2019-11-11 | 삼성전자주식회사 | 반도체 메모리 칩 및 이를 포함하는 적층형 반도체 패키지 |
US10643192B2 (en) * | 2016-09-06 | 2020-05-05 | Bank Of American Corporation | Data transfer between self-service device and server over session or connection in response to capturing sensor data at self-service device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353365A (ja) * | 2001-05-30 | 2002-12-06 | Hitachi Ltd | 半導体装置 |
JP2003332515A (ja) * | 2002-05-09 | 2003-11-21 | Sharp Corp | 半導体集積回路装置およびその製造方法 |
JP2006114595A (ja) * | 2004-10-13 | 2006-04-27 | Hitachi Ltd | 半導体装置 |
JP2007095970A (ja) * | 2005-09-28 | 2007-04-12 | Elpida Memory Inc | 半導体パッケージの製造方法及び半導体パッケージ |
Family Cites Families (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231305A (en) * | 1990-03-19 | 1993-07-27 | Texas Instruments Incorporated | Ceramic bonding bridge |
WO1996023320A1 (en) * | 1995-01-24 | 1996-08-01 | Intel Corporation | High performance integrated circuit package |
US6005778A (en) * | 1995-06-15 | 1999-12-21 | Honeywell Inc. | Chip stacking and capacitor mounting arrangement including spacers |
US5723906A (en) * | 1996-06-07 | 1998-03-03 | Hewlett-Packard Company | High-density wirebond chip interconnect for multi-chip modules |
US5895977A (en) * | 1996-08-08 | 1999-04-20 | Intel Corporation | Bond pad functional layout on die to improve package manufacturability and assembly |
JPH1092857A (ja) * | 1996-09-10 | 1998-04-10 | Mitsubishi Electric Corp | 半導体パッケージ |
US5838072A (en) * | 1997-02-24 | 1998-11-17 | Mosel Vitalic Corporation | Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes |
US6060772A (en) * | 1997-06-30 | 2000-05-09 | Kabushiki Kaisha Toshiba | Power semiconductor module with a plurality of semiconductor chips |
JP3938617B2 (ja) * | 1997-09-09 | 2007-06-27 | 富士通株式会社 | 半導体装置及び半導体システム |
US6064113A (en) * | 1998-01-13 | 2000-05-16 | Lsi Logic Corporation | Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances |
US6410989B1 (en) * | 1999-01-04 | 2002-06-25 | International Rectifier Corporation | Chip-scale package |
US6274925B1 (en) * | 1999-07-21 | 2001-08-14 | Conexant Systems, Inc. | Low inductance top metal layer design |
JP4570809B2 (ja) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
JP3722209B2 (ja) * | 2000-09-05 | 2005-11-30 | セイコーエプソン株式会社 | 半導体装置 |
US6448639B1 (en) * | 2000-09-18 | 2002-09-10 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
JP3854054B2 (ja) * | 2000-10-10 | 2006-12-06 | 株式会社東芝 | 半導体装置 |
US6972484B2 (en) * | 2000-10-13 | 2005-12-06 | Texas Instruments Incorporated | Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface |
US6472747B2 (en) * | 2001-03-02 | 2002-10-29 | Qualcomm Incorporated | Mixed analog and digital integrated circuits |
JP4091838B2 (ja) * | 2001-03-30 | 2008-05-28 | 富士通株式会社 | 半導体装置 |
JP2002343899A (ja) * | 2001-05-17 | 2002-11-29 | Sharp Corp | 半導体パッケージ用基板、半導体パッケージ |
US8089142B2 (en) * | 2002-02-13 | 2012-01-03 | Micron Technology, Inc. | Methods and apparatus for a stacked-die interposer |
US6682955B2 (en) * | 2002-05-08 | 2004-01-27 | Micron Technology, Inc. | Stacked die module and techniques for forming a stacked die module |
JP3958156B2 (ja) * | 2002-08-30 | 2007-08-15 | 三菱電機株式会社 | 電力用半導体装置 |
JP2004103703A (ja) * | 2002-09-06 | 2004-04-02 | Ricoh Co Ltd | 半導体装置及び当該半導体装置を用いた異なるレベルの信号の処理システム |
JP2004296613A (ja) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | 半導体装置 |
JP2004327757A (ja) | 2003-04-25 | 2004-11-18 | Toshiba Corp | 半導体装置 |
US7202546B2 (en) * | 2003-10-03 | 2007-04-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated circuit with copper interconnect and top level bonding/interconnect layer |
CN100527413C (zh) * | 2004-06-07 | 2009-08-12 | 富士通微电子株式会社 | 内置有电容器的半导体装置及其制造方法 |
US7151309B2 (en) * | 2004-08-27 | 2006-12-19 | Texas Instruments Incorporated | Apparatus for improved power distribution in wirebond semiconductor packages |
US8324725B2 (en) * | 2004-09-27 | 2012-12-04 | Formfactor, Inc. | Stacked die module |
US20060087013A1 (en) * | 2004-10-21 | 2006-04-27 | Etron Technology, Inc. | Stacked multiple integrated circuit die package assembly |
JP4199724B2 (ja) * | 2004-12-03 | 2008-12-17 | エルピーダメモリ株式会社 | 積層型半導体パッケージ |
US7884454B2 (en) * | 2005-01-05 | 2011-02-08 | Alpha & Omega Semiconductor, Ltd | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
JP4827556B2 (ja) * | 2005-03-18 | 2011-11-30 | キヤノン株式会社 | 積層型半導体パッケージ |
US7265443B2 (en) * | 2005-04-29 | 2007-09-04 | Texas Instruments Incorporated | Wire bonded semiconductor device having low inductance and noise |
JP4707095B2 (ja) * | 2005-05-09 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体回路 |
JP2007103423A (ja) * | 2005-09-30 | 2007-04-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US20070164446A1 (en) * | 2006-01-13 | 2007-07-19 | Hawk Donald E Jr | Integrated circuit having second substrate to facilitate core power and ground distribution |
US7443011B2 (en) * | 2006-02-10 | 2008-10-28 | Marvell International Technology Ltd. | System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices |
US7772107B2 (en) * | 2006-10-03 | 2010-08-10 | Sandisk Corporation | Methods of forming a single layer substrate for high capacity memory cards |
US20080197474A1 (en) * | 2007-02-16 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with multi-chips and method of the same |
JP4405524B2 (ja) * | 2007-03-27 | 2010-01-27 | 株式会社東芝 | 半導体装置 |
KR101185886B1 (ko) * | 2007-07-23 | 2012-09-25 | 삼성전자주식회사 | 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템 |
JP2009038142A (ja) * | 2007-07-31 | 2009-02-19 | Elpida Memory Inc | 半導体積層パッケージ |
US7768123B2 (en) * | 2007-09-26 | 2010-08-03 | Fairchild Semiconductor Corporation | Stacked dual-die packages, methods of making, and systems incorporating said packages |
US7800208B2 (en) * | 2007-10-26 | 2010-09-21 | Infineon Technologies Ag | Device with a plurality of semiconductor chips |
US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
US20090194857A1 (en) * | 2008-02-01 | 2009-08-06 | Yong Liu | Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same |
US7687921B2 (en) * | 2008-05-05 | 2010-03-30 | Super Talent Electronics, Inc. | High density memory device manufacturing using isolated step pads |
US7884444B2 (en) * | 2008-07-22 | 2011-02-08 | Infineon Technologies Ag | Semiconductor device including a transformer on chip |
JP2010171289A (ja) * | 2009-01-26 | 2010-08-05 | Oki Data Corp | 画像表示装置 |
-
2009
- 2009-02-18 JP JP2009035546A patent/JP2010192680A/ja active Pending
-
2010
- 2010-02-18 US US12/707,996 patent/US8243465B2/en not_active Expired - Fee Related
-
2012
- 2012-05-03 US US13/463,317 patent/US20130114223A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353365A (ja) * | 2001-05-30 | 2002-12-06 | Hitachi Ltd | 半導体装置 |
JP2003332515A (ja) * | 2002-05-09 | 2003-11-21 | Sharp Corp | 半導体集積回路装置およびその製造方法 |
JP2006114595A (ja) * | 2004-10-13 | 2006-04-27 | Hitachi Ltd | 半導体装置 |
JP2007095970A (ja) * | 2005-09-28 | 2007-04-12 | Elpida Memory Inc | 半導体パッケージの製造方法及び半導体パッケージ |
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US8243465B2 (en) | 2012-08-14 |
US20130114223A1 (en) | 2013-05-09 |
US20100208443A1 (en) | 2010-08-19 |
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