CN108475671A - 用于堆叠引线接合转换的倒装芯片管芯的系统和方法 - Google Patents
用于堆叠引线接合转换的倒装芯片管芯的系统和方法 Download PDFInfo
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Abstract
各种实施例总体上涉及一种包括堆叠在彼此顶部的至少两个管芯的电子组件。不同高度的金属柱将管芯电连接至系统基板。
Description
背景技术
可以在由硅或其它材料构成的基板上创建模拟和/或数字电路;由于耐用性、可靠性或者其它类似的原因,这些基板可以被放置在封装中。为了与其它电路和/或系统通信,封装可以包括一个或多个导体,所述导体将封装内的电路中的输入和/或输出信号电连接至封装外部,以由此允许其它电路和/或系统向封装内的电路发送电信号并接收封装内的电路的电信号。封装可以进一步包括向封装内的电路供电的导体或者任何其它类型的导体。
附图说明
图1A、图1B和图1C示出了包括堆叠管芯的电子组件的示例性实施例的顶视图和底视图;
图2示出了包括堆叠管芯的电子组件的示例性实施例的截面图;
图3示出了包括堆叠管芯的电子组件的示例性实施例的底视图;
图4示出了包括堆叠管芯的电子组件的示例性实施例的截面图;
图5A、图5B和图5C示出了包括堆叠管芯的电子组件的示例性实施例的顶视图和对应截面图;
图6示出了包括堆叠管芯的电子组件的示例性实施例的截面图;
图7A、图7B、图7C、图7D和图7E示出了制造包括堆叠管芯的电子组件的示例性方法;以及
图8示出了制造包括堆叠管芯的电子组件的示例性流程。
具体实施方式
封装中的导体可以是引线接合导体,其中,基板上的金属焊盘被引线接合至封装上的引脚,从而允许其它电路和/或系统向设置在基板上、连接至金属焊盘的任何电路发送信号和/或接收所述任何电路的信号。生产和制造引线接合导体可以是简单和/或廉价的,但是它们有缺点,包括可能限制它们能够支持的信号频率和/或边沿速率的寄生电感。作为替代,导体可以是基板上的凸块,在基板被翻转过来时,所述凸块直接连接至另一基板或者其它电路或系统。然而,大量的这些“倒装芯片”基板会消耗不可接受的大量的系统基板面积。
在各种实施例中,两个或更多管芯堆叠在彼此顶上,并被设置在系统基板上并与系统基板电通信。管芯可以包括由诸如硅的半导体材料构成的基板以及形成于所述基板中或所述基板上的用以形成数字和/或模拟逻辑的晶体管、电阻器、绝缘体、导体和/或其它部件。系统基板可以是另一基板、母板或者任何其它这种装置。管芯可以包括任何电路、存储器、储存器或者任何其它器件;在一些实施例中,管芯是存储器部件,例如低功率双倍数据率3(“LPDDR3”)动态随机存取存储器(“DRAM”)。系统基板可以类似地包括任何电路、存储器、储存器或任何其它器件。一组金属柱将每个管芯与系统基板电连接。具有例如18微米的第一高度的第一组金属柱将第一管芯连接至系统基板;焊料凸块可以用于将金属柱连接至第一管芯和/或系统基板。第一管芯可以具有15-20微米的厚度;在一些实施例中,第一管芯的厚度为18微米。第二管芯至少部分地设置在第一管芯的顶上,从而使得第一管芯的至少一部分设置在第二管芯和系统基板之间。具有例如90-120微米的第二高度的第二组金属柱将第二管芯连接至系统基板;焊料凸块可以用于将金属柱连接至第二管芯和/或系统基板。粘合膜可以用于连接第一和第二管芯,并且底部填充层可以添加在第一管芯和系统基板之间。与未堆叠管芯相比,根据文中公开的实施例对管芯进行堆叠可以允许所述管芯在系统基板上的所需面积有40-50%的下降。
图1A、图1B和图1C示出了根据文中描述的实施例的包括堆叠管芯的电子组件。尽管通过示例的方式描述了特定数量的堆叠管芯,但是本领域技术人员将理解,对于给定实施方式可以使用任何数量的堆叠管芯。然而,在该上下文中,实施例不受限制。
在图1A中,示出了系统基板101上的采用非堆叠配置的四个管芯102、104、106、108的顶视图100A。由于在文中使用术语,管芯的“顶视图”是指在管芯被设置在系统基板上时就像俯视该管芯一样的管芯视图;在倒装芯片管芯的情况下,顶视图呈现了管芯的背面的视图。管芯的“底视图”是指就像从系统基板的角度来看管芯一样的管芯视图;在倒装芯片管芯的情况下,底视图呈现了管芯的柱、凸块、上金属层和/或封装层的视图。在图1B中,顶视图100B示出了相对于系统基板101堆叠在另一管芯102顶上的管芯104、以及相对于系统基板101堆叠在另一管芯108顶上的管芯106。在整个本公开中,相对于系统基板堆叠在其它基板下方的管芯(即,设置在系统基板与其它管芯之间的管芯)可以被称为下堆叠管芯或第一管芯,并且相对于系统基板堆叠在其它管芯顶上的管芯可以被称为上堆叠管芯或第二管芯。在图1C中,示出了对应于图1B的顶视图100B的底视图100C;在该视图100C中未示出系统基板。在该视图100C中,多个金属柱110(其可以附接至和/或包括焊料凸块)可以设置在上堆叠管芯104、106(现在看起来处于下堆叠管芯102、108后面)上,并且多个金属柱112(其可以附接至和/或包括焊料凸块,如下文更详细地解释的)可以设置在下堆叠管芯102、108上。上堆叠管芯104、106的至少部分114可以延伸到下堆叠管芯102、108的周界之外,以容许放置金属柱110。在该实施例中,下堆叠管芯102、108的部分116可以延伸到上堆叠管芯104、106的部分之外;然而,在其它实施例中,下堆叠管芯102、108的任何部分都不延伸到上堆叠管芯104、106的周界之外。此外,在该实施例中,只有一个下堆叠管芯102、108被设置在上堆叠管芯104、106下方;然而,在其它实施例中,可以有任何数量的下堆叠管芯102、108被设置在上堆叠管芯104、106下方。
图2示出了根据文中公开的实施例的包括堆叠管芯的电子组件200的截面图。第一下堆叠管芯202经由第一金属柱206电连接至系统基板204,并且第二上堆叠管芯208经由第二金属柱210电连接至系统基板204。在一些实施例中,粘合膜212设置在下堆叠管芯202和上堆叠管芯208之间;粘合膜212可以粘附至下堆叠管芯202和上堆叠管芯208这两者,以使它们相对于彼此保持固定。
图3示出了包括上堆叠管芯302和下堆叠管芯304的电子组件300的底视图。在该示例性实施例中,下堆叠管芯304的任何部分都不延伸到上堆叠管芯302的周界之外。多个金属柱306设置在上堆叠管芯302的表面上,并且多个金属柱308设置在下堆叠管芯304的表面上。金属柱306、308可以附接至和/或包括焊料凸块。
图4示出了根据文中公开的实施例的包括堆叠管芯的电子组件400的截面图。第一下堆叠管芯402经由第一金属柱406电连接至系统基板404,并且第二上堆叠管芯408经由第二金属柱410电连接至系统基板404。在一些实施例中,粘合膜412设置在下堆叠管芯402和上堆叠管芯408之间;粘合膜412可以粘附至下堆叠管芯402和上堆叠管芯408这两者,以使它们相对于彼此保持固定。焊料凸块414可以用于将金属柱406、410附接至系统基板404。
图5A、图5B和图5C分别示出了根据文中公开的实施例的包括堆叠管芯的电子组件500A、500B、500C的顶视图、截面图和另一截面图。图5A示出了包括金属柱504(其可以附接至和/或包括焊料凸块,如下文更详细解释的)的上堆叠管芯502和包括金属柱508(其可以附接至和/或包括焊料凸块,如下文更详细解释的)的下堆叠管芯506。图5B是沿第一参考线510的图5A的截面图,并且图5C是沿第二参考线512的图5A的截面图。
在图5B中,截面图500B包括经由金属柱504电连接至系统基板514的上堆叠管芯502;在该实施例中,金属柱504使用焊料凸块516附接至系统基板514。注意,与下堆叠管芯506相关联的金属柱508未出现在该视图500B中。在一些实施例中,粘合膜518设置在上堆叠管芯502和下堆叠管芯506之间。在图5C中,截面图500C包括经由金属柱508电连接至系统基板514的下堆叠管芯506;在该实施例中,金属柱504使用焊料凸块520附接至系统基板514。注意,与上堆叠管芯502相关联的金属柱504未出现在该视图500C中。
图6示出了包括上堆叠管芯602、下堆叠管芯604和系统基板606的电子组件600的截面图。电子组件600还包括粘合层608、与上堆叠管芯602相关联的金属柱610和焊料凸块612、以及与下堆叠管芯604相关联的金属柱614和焊料凸块616。对于任何管芯、层、金属柱或焊料凸块而言,文中描述的实施例不限于任何特定厚度。如图中所示,上堆叠管芯602的厚度可以是300微米;下堆叠管芯604的厚度可以是50微米;粘合层608的厚度可以是25微米;与上堆叠管芯602相关联的金属柱610和焊料凸块612的厚度可以分别是90微米和25微米;并且与下堆叠管芯604相关联的金属柱614和焊料凸块616的厚度可以分别为18微米和15微米。
图7A、图7B、图7C、图7D和图7E示出了根据文中公开的实施例的用于形成电子组件的方法。图7A是视图700A,其中第一组金属柱702形成在第一管芯704上并且第二组金属柱706形成在第二管芯708上。金属柱702、706可以是使用本领域已知的任何方法或技术形成的;在一些实施例中,金属柱702、706是在将引线接合管芯转换成倒装芯片管芯的重新分布层的形成之后形成的。图7B是视图700B,其中粘合膜710沉积在第二管芯708的表面712上。替代地或此外,粘合膜710可以沉积在第一管芯704的表面714上。粘合膜710可以是管芯附接膜(“DAF”)。图7C是视图700C,其中,第一管芯704的表面714附接至粘合膜710。图7D是视图700D,其中,管芯704、708使用例如热压接合工艺经由金属柱702、706附接至系统基板716。图7D是视图700E,其中,底部填充层添加在第一管芯704和系统基板716之间。
图8示出了方法800,其为用于形成电子组件的方法。具有第一高度的第一组第一金属柱形成(802)在第一管芯上,并且具有大于第一高度的第二高度的第二组第二金属柱形成(804)在第二管芯上。粘合膜沉积(806)在第二管芯的表面上。第一管芯的表面附接(808)至粘合膜。第一金属柱和第二金属柱热压接合(810)至系统基板。
在各种实施例中,包括系统基板的电子组件可以与第一(即,下堆叠)管芯和第二(即,上堆叠)管芯电子通信。系统基板可以通过第一管芯上的具有第一高度的第一组第一金属柱传送第一信号,并且通过第二管芯上的具有大于第一高度的第二高度的第二组第二金属柱传送第二信号。第一管芯的至少部分可以设置在第二管芯和系统基板之间,如上文所述。
示例1是一种电子组件,包括:系统基板;第一管芯,其设置在所述系统基板上并且使用具有第一高度的第一组第一金属柱与所述系统基板电通信;第二管芯,其设置在所述系统基板上并且使用具有大于所述第一高度的第二高度的第二组第二金属柱与所述基板电通信,从而使所述第一管芯的至少部分设置在所述第二管芯和所述系统基板之间。
示例2包括示例1的主题,还包括设置在所述第一管芯和所述第二管芯之间的粘合膜。
示例3包括示例1的主题,其中,所述第一管芯包括倒装芯片管芯,并且所述第二管芯包括倒装芯片管芯。
示例4包括示例1的主题,所述第一管芯包括经转换的引线接合管芯,并且所述第二管芯包括经转换的引线接合管芯。
示例5包括示例1的主题,还包括第三管芯,第三管芯设置在所述系统基板上并且使用具有第三高度的第三组第三金属柱与所述系统基板电通信,从而使得所述第三管芯的至少部分设置在所述第二管芯和所述系统基板之间。
示例6包括示例1的主题,其中,所述第一管芯的部分延伸到所述第二管芯的周界之外。
示例7包括示例1的主题,其中,所述第一管芯包括动态随机存取存储器。
示例8包括示例1的主题,还包括设置在所述第一管芯和所述系统基板之间的底部填充层。
示例9包括示例1的主题,其中,所述第一金属柱包括铜。
示例10包括示例1的主题,其中,所述第一金属柱包括焊料凸块。
示例11包括示例1的主题,其中,所述第一高度包括15-20微米。
示例12包括示例11的主题,其中,所述第一高度包括18微米。
示例13包括示例1的主题,其中,所述第二高度包括90-120微米。
示例14包括示例13的主题,其中,所述第二高度包括90微米。
示例15包括示例1的主题,其中,所述第一管芯的厚度包括50微米。
示例16包括示例1的主题,其中,所述第二管芯的厚度包括300微米。
示例17是一种用于形成电子组件的方法,所述方法包括:在第一管芯上形成具有第一高度的第一组第一金属柱;在第二管芯上形成具有大于第一高度的第二高度的第二组第二金属柱;在所述第二管芯的表面上沉积粘合膜;将所述第一管芯的表面附接至所述粘合膜;将所述第一金属柱和所述第二金属柱热压接合至系统基板。
示例18包括示例17的主题,还包括在所述第二管芯和所述系统基板之间沉积底部填充层。
示例19包括示例17的主题,还包括在所述第一柱和所述第二柱上沉积焊料凸块。
示例20包括示例17的主题,还包括将所述第一管芯从引线接合管芯转换成倒装芯片管芯。
示例21包括示例17的主题,还包括将所述第一管芯形成为具有包括50微米的厚度。
示例22包括示例17的主题,还包括将所述第二管芯形成为具有包括300微米的厚度。
示例23包括示例17的主题,其中,所述第一高度包括15-20微米。
示例24包括示例23的主题,其中,所述第一高度包括18微米。
示例25包括示例17的主题,其中,所述第二高度包括90-120微米。
示例26包括示例25的主题,其中,所述第二高度包括90微米。
示例27是一种用于与设置在多个管芯上的电路电子通信的方法,所述方法包括:通过电连接至系统基板并且具有第一高度的第一组第一金属柱将第一信号从所述系统基板传送至与所述第一组第一金属柱电连接的第一管芯;通过电连接至所述系统基板并且具有大于所述第一高度的第二高度的第二组第二金属柱将第二信号从所述系统基板传送至与所述第二组第二金属柱电连接的第二管芯,所述第一管芯的至少部分设置在所述第二管芯和所述系统基板之间。
示例28包括示例27的主题,还包括在所述第二管芯和所述系统基板之间沉积底部填充层。
示例29包括示例27的主题,还包括在所述第一柱和所述第二柱上沉积焊料凸块。
示例30包括示例27的主题,还包括将所述第一管芯从引线接合管芯转换为倒装芯片管芯。
示例31包括示例27的主题,还包括将所述第一管芯形成为具有包括50微米的厚度。
示例32包括示例27的主题,还包括将所述第二管芯形成为具有包括300微米的厚度。
示例33包括示例27的主题,其中,所述第一管芯包括动态随机存取存储器。
示例34包括示例27的主题,其中,所述第一金属柱包括铜。
示例35包括示例27的主题,其中,所述第一金属柱包括焊料凸块。
一些实施例可以是使用表述“一个实施例”或“实施例”及其派生词描述的。这些术语意味着在至少一个实施例中包含了联系所述实施例描述的特定特征、结构或特性。在说明书的各个地方出现的短语“在一个实施例中”未必全都是指相同的实施例。此外,一些实施例可以是使用表述“耦合”和“连接”及其派生词描述的。这些术语未必意在充当彼此的同义词。例如,一些实施例可以是通过使用术语“连接”和/或“耦合”指示两个或更多元件相互直接物理或电接触来描述的。然而,术语“耦合”也可以指两个或更多元件不相互直接接触,但是仍然相互协作或交互。
要强调的是,提供本公开的摘要是为了允许读者快速地确定本技术公开的实质。在理解了摘要并非用于解释或限制权利要求的范围和含义的情况下提交所述摘要。此外,在前面的具体实施方式中可以看出,各种特征一起分组在单个实施例中,以用于简化本公开的目的。不应将本公开的该方法解释成反映了这样的意图,即所要求保护的实施例所需要的特征比每一权利要求中明确表述的特征多。相反,如下述权利要求所反映的,本发明的主题可以存在于单个所公开的实施例的所有特征中的部分特征中。因而,在此将下述权利要求并入到具体实施方式中,其中每个权利要求自身代表单独的实施例。在所附权利要求中,术语“包括”和“在其中”分别用作相应术语“包含”和“其中”的通俗英语等同物。此外,术语“第一”、“第二”、“第三”等仅用作标记,而非意在为其对象施加数字上的要求。
上文所描述的内容包括所公开架构的示例。当然,不可能描述部件和/或方法的每一种可以设想的组合,但是本领域普通技术人员可以认识到很多其它的组合和置换也是可能的。相应地,所述新颖架构意在包含落在所附权利要求的实质和范围内的所有这种变更、修改和变化。
Claims (25)
1.一种电子组件,包括:
系统基板;
第一管芯,其设置在所述系统基板上并且使用具有第一高度的第一组第一金属柱与所述系统基板电通信;
第二管芯,其设置在所述系统基板上并且使用具有大于所述第一高度的第二高度的第二组第二金属柱与所述系统基板电通信,从而使得所述第一管芯的至少部分设置在所述第二管芯和所述系统基板之间。
2.根据权利要求1所述的电子组件,还包括设置在所述第一管芯和所述第二管芯之间的粘合膜。
3.根据权利要求1所述的电子组件,所述第一管芯包括倒装芯片管芯,并且所述第二管芯包括倒装芯片管芯。
4.根据权利要求1所述的电子组件,所述第一管芯包括经转换的引线接合管芯,并且所述第二管芯包括经转换的引线接合管芯。
5.根据权利要求1所述的电子组件,还包括第三管芯,所述第三管芯设置在所述系统基板上并且使用具有第三高度的第三组第三金属柱与所述系统基板电通信,从而使得所述第三管芯的至少部分设置在所述第二管芯和所述系统基板之间。
6.根据权利要求1所述的电子组件,所述第一管芯的部分延伸到所述第二管芯的周界之外。
7.根据权利要求1所述的电子组件,所述第一管芯包括动态随机存取存储器。
8.根据权利要求1所述的电子组件,还包括设置在所述第一管芯和所述系统基板之间的底部填充层。
9.根据权利要求1所述的电子组件,所述第一金属柱包括铜。
10.根据权利要求1所述的电子组件,所述第一金属柱包括焊料凸块。
11.一种用于形成电子组件的方法,所述方法包括:
在第一管芯上形成具有第一高度的第一组第一金属柱;
在第二管芯上形成具有大于所述第一高度的第二高度的第二组第二金属柱;
在所述第二管芯的表面上沉积粘合膜;
将所述第一管芯的表面附接至所述粘合膜;
将所述第一金属柱和所述第二金属柱热压接合至系统基板。
12.根据权利要求11所述的方法,还包括在所述第二管芯和所述系统基板之间沉积底部填充层。
13.根据权利要求11所述的方法,还包括在所述第一柱和所述第二柱上沉积焊料凸块。
14.根据权利要求11所述的方法,还包括将所述第一管芯从引线接合管芯转换为倒装芯片管芯。
15.根据权利要求11所述的方法,还包括将所述第一管芯形成为具有包含50微米的厚度。
16.根据权利要求11所述的方法,还包括将所述第二管芯形成为具有包含300微米的厚度。
17.一种用于与设置在多个管芯上的电路电子通信的方法,所述方法包括:
通过电连接至系统基板并且具有第一高度的第一组第一金属柱将第一信号从所述系统基板传送至与所述第一组第一金属柱电连接的第一管芯;
通过电连接至所述系统基板并且具有大于所述第一高度的第二高度的第二组第二金属柱将第二信号从所述系统基板传送至与所述第二组第二金属柱电连接的第二管芯,所述第一管芯的至少部分设置在所述第二管芯和所述系统基板之间。
18.根据权利要求17所述的方法,还包括在所述第二管芯和所述系统基板之间沉积底部填充层。
19.根据权利要求17所述的方法,还包括在所述第一柱和所述第二柱上沉积焊料凸块。
20.根据权利要求17所述的方法,还包括将第一管芯从引线接合管芯转换为倒装芯片管芯。
21.根据权利要求17所述的方法,还包括将所述第一管芯形成为具有包括50微米的厚度。
22.根据权利要求17所述的方法,还包括将第二管芯形成为具有包括300微米的厚度。
23.根据权利要求17所述的方法,所述第一管芯包括动态随机存取存储器。
24.根据权利要求17所述的方法,所述第一金属柱包括铜。
25.根据权利要求17所述的方法,所述第一金属柱包括焊料凸块。
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KR20120096754A (ko) * | 2011-02-23 | 2012-08-31 | 삼성전자주식회사 | 인터포저를 이용한 웨이퍼 칩의 3차원 스택 구조 |
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