CN105575931A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN105575931A
CN105575931A CN201510644970.XA CN201510644970A CN105575931A CN 105575931 A CN105575931 A CN 105575931A CN 201510644970 A CN201510644970 A CN 201510644970A CN 105575931 A CN105575931 A CN 105575931A
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China
Prior art keywords
connection pad
hole
projection connection
semiconductor
crystalline substance
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Granted
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CN201510644970.XA
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CN105575931B (zh
Inventor
方家伟
林子闳
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MediaTek Inc
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MediaTek Inc
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Publication of CN105575931B publication Critical patent/CN105575931B/zh
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本发明提供了一种半导体封装，包括：封装基板和半导体裸晶，该封装基板具有第一表面和与该第一表面相对的第二表面；该半导体裸晶装配在该封装基板的该第一表面上。该半导体裸晶包括第一凸块接垫、第二凸块接垫、设置在该第一凸块接垫上的第一通孔和设置在该第二凸块接垫上的第二通孔；其中，该第一凸块接垫和该第二凸块接垫设置在该半导体裸晶的活性表面上，以及，该第一通孔的直径小于该第二通孔的直径。采用本发明，可以提高半导体封装体的电气特性。

Description

半导体封装
技术领域
本发明涉及半导体封装领域，更特别地，涉及一种具有混合的通孔或凸块接垫尺寸的半导体封装。
背景技术
为了确保电子产品或通信设备的小型化和多功能性，通常要求半导体封装具有小尺寸、多针连接(multi-pinconnection)、高速和高功能化的特性。输入-输出(Input-Output，I/O)引脚数量的增加连同对高性能集成电路的需求的增加，导致了倒装芯片(flipchip)封装的发展。
倒装芯片技术通常使用芯片上的焊接凸块(solderbump)来互连封装媒介，如封装基板。倒装芯片经过最短的路径正面朝下的接合至封装基板。这些技术可以不仅适用于单芯片封装，而且还可以适用于更高集成度的封装(该封装更大)以及更加复杂的基板中，其中，该基板能够容纳几个芯片以形成更大的功能单元。使用面积阵列(areaarray)的倒装芯片技术具有能够实现与设备的更高密度互连及与封装体的非常低的电感互连的优点。
最近，提出了一种铜柱凸块(copperpillarbump)技术。电子元件通过铜柱凸块而非焊接凸块(solderbump)的方式与基板连接，这样能使得间距更小，且使得凸块之间的桥接的可能性降为最低，降低了电路的电容负担以及允许电子元件在更高频率上操作。
然而，现有技术中，利用铜柱凸块的传统倒装芯片封装均由具有单一的铜柱尺寸(singlecopperpillarsize)来实现，即封装体中所有铜柱的尺寸均相同，这导致半导体封装的电气特性受到限制。
发明内容
有鉴于此，本发明的目的之一在于提供一种半导体封装，以解决上述问题。
根据本发明的一实施例，半导体封装包括封装基板和半导体裸晶，该封装基板具有第一表面和与该第一表面相对的第二表面；该半导体裸晶装配在该封装基板的该第一表面上。该半导体裸晶包括在该半导体裸晶的活性表面上的多个第一凸块接垫和多个第二凸块接垫、在该多个第一凸块接垫上的多个第一通孔以及在该多个第二凸块接垫上的多个第二通孔。每个第一通孔的直径小于每个第二通孔的直径。
根据本发明的一实施例，该多个第一通孔和该多个第二通孔是铜柱。
根据本发明的一实施例，该半导体封装还包括填充层，该填充层设置在该半导体裸晶和该封装基板之间，以环绕该多个第一通孔和该多个第二通孔。
根据本发明的另一实施例，半导体封装包括封装基板和半导体裸晶，该封装基板具有第一表面和与该第一表面相对的第二表面；以及，该半导体裸晶装配在该封装基板的该第一表面上。该半导体裸晶包括在该半导体裸晶的活性表面上的多个第一凸块接垫和多个第二凸块接垫、在该多个第二凸块接垫上的多个通孔。该第一凸块接垫的接垫尺寸小于该第二凸块接垫的接垫尺寸。
根据本发明的另一实施例，半导体封装包括封装基板、第一半导体裸晶和第二半导体裸晶，该封装基板具有第一表面和与该第一表面相对的第二表面；该第一半导体裸晶装配在该封装基板的该第一表面上；以及，该第二半导体裸晶装配在该封装基板的该第一表面上。其中，该第一半导体裸晶包括在该第一半导体裸晶的活性表面上的多个第一凸块接垫和多个第二凸块接垫、在该多个第一凸块接垫上的多个第一通孔以及在该多个第二凸块接垫上的多个第二通孔。该第一通孔的直径小于该第二通孔的直径。
在其中一种实现方式中，该第二半导体裸晶包括在该第二半导体裸晶的活性表面上的多个第三凸块接垫和多个第四凸块接垫、在该多个第三凸块接垫上的多个第三通孔以及在该多个第四凸块接垫上的多个第四通孔；其中，该第三通孔的直径小于该第四通孔的直径。
在另一种实现方式中，该多个第一凸块接垫、该多个第一通孔、该多个第三凸块接垫和该多个第三通孔通过金属线形成该第一半导体裸晶和该第二半导体裸晶之间的裸晶至裸晶连接；其中，该金属线位于该封装基板中或该封装基板上。
采用本发明，可以提高半导体封装的电气特性。
本领域技术人员在阅读附图所示优选实施例的下述详细描述之后，可以毫无疑义地理解本发明的这些目的及其它目的。
附图说明
图1是根据本发明一实施例的多裸晶倒装芯片封装的截面示意图；
图2是根据本发明一实施例的第一裸晶的活性表面上的一种布局示意图；
图3示出了根据本发明另一实施例的一种倒装芯片封装的有关部分的截面示意图。
具体实施方式
应当理解的是，以下公开的内容提供了许多不同的实施例或示例，用于实现各种实施例的不同特征。为了简化本发明，各元件及安排的具体实例描述如下。这些仅仅是示例，并不旨在进行限制。
另外，本发明可以在各种示例中重复附图标记和/或字母。这种重复是为了简化和清楚的目的，其本身并不表示所讨论的各种实施例和/或配置之间的关系。
此外，后附的描述中在第二特征上形成的第一特征可以包括与第二特征直接接触或非直接接触所形成的第一特征的实施方式。
以下描述为本发明实施的较佳实施例。以下实施例仅用来例举阐释本发明的技术特征，并非用来限制本发明的范畴。在通篇说明书及权利要求书当中使用了某些词汇来指称特定的元件。所属领域技术人员应可理解，制造商可能会用不同的名词来称呼同样的元件。本说明书及权利要求书并不以名称的差异来作为区别元件的方式，而是以元件在功能上的差异来作为区别的基准。本发明中使用的术语“元件”、“系统”和“装置”可以是与计算机相关的实体，其中，该计算机可以是硬件、软件、或硬件和软件的结合。在以下描述和权利要求书当中所提及的术语“包含”和“包括”为开放式用语，故应解释成“包含，但不限定于…”的意思。此外，术语“耦接”意指间接或直接的电气连接。因此，若文中描述一个装置耦接于另一装置，则代表该装置可直接电气连接于该另一装置，或者透过其它装置或连接手段间接地电气连接至该另一装置。
在通篇说明书中，所使用的术语“裸晶(die)”、“半导体芯片(semiconductorchip)”和“半导体裸晶(semiconductordie)”可以互换。在集成电路背景下的裸晶是一小块的半导体材料，给定的功能电路在该裸晶上实现(fabricate)。
图1是根据本发明一实施例的多裸晶倒装芯片封装(multi-dieflip-chippackage)的截面示意图。如图1所示，多裸晶倒装芯片封装1包括第一裸晶10和第二裸晶20，第一裸晶10和第二裸晶20的活性表面(activesurface)均面向封装基板(packagingsubstrate)30的第一表面30a。封装基板30的前述第一表面30a也可以被定义为“芯片侧”。根据本发明实施例，第一裸晶10可以通过多个通孔(via)111和112装配至封装基板30的第一表面30a，如铜孔(coppervia)或铜柱(copperpillar)；以及，第二裸晶20可以通过多个通孔211和212装配至封装基板30的第一表面30a，如铜孔或铜柱。为便于描述，部分实施例中的通孔以铜柱为例进行说明。
封装基板30可以是塑料基板(plasticsubstrate)、陶瓷基板(ceramicsubstrate)或硅基板(如中介层interposer)。根据本发明实施例，例如，封装基板30可以具有从双面覆铜板(CopperCladLamination，CCL)开始制作的叠层塑料结构，但本发明并不限于此情形。应当理解的是，封装基板30可以具有多个金属配线层(multiplemetalwiringlayers)，例如，根据本发明实施例的2层、4层或6层等。
填充层(underfilllayer)130可以设置在(bedisposed)第一裸晶10和封装基板30之间，以环绕(surround)该多个通孔111和112。填充层230可以设置在第二裸晶20和封装基板30之间，以环绕该多个通孔211和212。其中，填充层130和230可以控制由裸晶和封装基板之间的热膨胀差异所引起的应力(stress)。因此，一旦被加工处理(cured)，该填充层会吸收该应力，从而减少在凸块或通孔(如铜孔、铜柱)上的应变，大大增加成品封装体的寿命。应当理解的是，在一些情形中，可以省略该填充层或可以使用其它合适的材料来替代该填充层。
根据本发明实施例，通孔111和211分别设置在第一裸晶10和第二裸晶20的活性表面上的凸块接垫(bumppad)11和21上。通孔111和211具有一个相对较小的直径尺寸(diametersize)，该相对较小的直径尺寸小于第一预设值，例如，小于50微米(micrometer，μm)的直径，但本发明并不限于此情形。凸块接垫11和21以及通孔111和211用于形成裸晶至裸晶连接(die-to-dieconnection)，且还主要用于通过金属线(metalwire)302来传送第一裸晶10和第二裸晶20之间的数字信号，金属线302位于封装基板30中或位于封装基板30上。
根据本发明实施例，通孔112和212分别设置在第一裸晶10和第二裸晶20的活性表面的凸块接垫12和22上。通孔112和212具有相对较大的直径尺寸，该相对较大的直径尺寸大于第二预设值，例如，第二预设值可以是80微米，以使通孔112和212的直径尺寸大于80微米，但本发明并不限于此情形。凸块接垫12和22以及通孔(如通孔或铜柱)112和212用于形成裸晶至基板的连接(die-to-substrateconnection)，且还主要用于通过封装基板30中的至少一根金属线或导线(trace)304来传送第一裸晶10/第二裸晶20与封装基板30之间的模拟信号、电源信号、地信号等。其中，第二预设值不小于第一预设值。换句话说，通孔111的直径小于通孔112的直径，通孔211的直径小于通孔212的直径。
根据本发明实施例，通孔112与通孔111之间的直径比率大于1。根据本发明另一实施例，通孔112与通孔111之间的直径比率大于2。
根据本发明实施例，通孔212与通孔211之间的直径比率大于1。根据本发明另一实施例，通孔212与通孔211之间的直径比率大于2。
根据本发明实施例，凸块接垫12与凸块接垫11的直径比率大于1，即凸块接垫11的接垫尺寸小于凸块接垫12的接垫尺寸。根据本发明另一实施例，凸块接垫12与凸块接垫11的直径比率大于2。
根据本发明实施例，凸块接垫22与凸块接垫21的直径比率大于1，即凸块接垫21的接垫尺寸小于凸块接垫22的接垫尺寸。根据本发明另一实施例，凸块接垫22与凸块接垫21的直径比率大于2。
特别地，在另一种实现方式中，凸块接垫11的接垫尺寸可以与凸块接垫21的接垫尺寸相同，以及，通孔111的直径可以与通孔211的直径相同。进一步地，凸块接垫12的接垫尺寸可以与凸块接垫22的接垫尺寸相同，通孔112的直径可以与通孔212的直径相同。
根据本发明实施例，多个焊球(solderball)310可以设置在封装基板30的第二表面30b上，用于裸晶(如第一裸晶10和/或第二裸晶20)和印刷电路板(PrintedCircuitBoard，PCB；图中未示出)之间的电气连接。封装基板30的第二表面30b也可以被定义为“PCB侧”。
在本发明提供的半导体封装中，通过采用具有混合的通孔尺寸和/或混合的凸块接垫尺寸，即使半导体封装具有不同尺寸的通孔和/或凸块接垫，可以提高半导体封装的电气性能。例如，在一块半导体封装体中可以采用小尺寸的通孔和/或凸块接垫用于裸晶至裸晶连接，采用大尺寸的通孔和/或凸块接垫用于裸晶至基板连接，从而，不仅可以满足大量的裸晶至裸晶连接，而且还可实现封装体设计的高速度、满足功率消耗等电气约束的优点。
请参照图2。图2是根据本发明一实施例的第一裸晶10的活性表面上的一种布局示意图，该布局示意图示出了一种在半导体裸晶的活性表面上设置有具有混合的通孔尺寸(mixedcopperpillarsizes)或通孔(如铜柱)尺寸不全部相同的例子，其中，相同的层、区域或元件使用相同的数字标号。如图2所示，多个凸块接垫11和12设置在第一裸晶10的活性表面上。用于裸晶至裸晶连接的凸块接垫11具有相对较小的尺寸，例如，小于50微米的直径，但本发明并不限于此情形。用于裸晶至基板连接的凸块接垫12具有相对较大的尺寸，例如，大于80微米的直径，但本发明并不限于此情形。应当理解的是，在一些情形中，该裸晶10的活性表面上的凸块接垫也可以使用第三尺寸(即不同于上述相对较小的尺寸和上述相对较大的尺寸)。通孔112(如铜柱)设置在凸块接垫12上。
图3示出了根据本发明另一实施例的一种倒装芯片封装2的有关部分的截面示意图，其中，相同的层、区域或元件使用相同的数字标号。该倒装芯片封装2可以是单裸晶(single-die)封装，但本发明并不限于此情形。如图3所示，倒装芯片封装2包括半导体裸晶100，该半导体裸晶100装配在封装基板300的芯片侧。根据本发明实施例，半导体裸晶100可以通过多个通孔112(如铜柱)装配至封装基板300的第一表面300a。
多个凸块接垫11和12设置在该半导体裸晶100的活性表面上。凸块接垫11具有相对较小的尺寸，例如，直径小于50微米。用于裸晶至基板连接的凸块接垫12具有相对较大的尺寸，例如，直径大于80微米，但本发明并不限于此情形。本发明实施例中，凸块接垫12的(接垫)尺寸大于凸块接垫11的(接垫)尺寸。通孔112可以设置在凸块接垫12上。根据本发明实施例，凸块接垫11是被禁用的接垫(disabledpad)及凸块接垫11上没有形成通孔(如铜柱或铜孔)。
根据本发明实施例，封装基板300可以是塑料基板、陶瓷基板或硅基板(如中介层)。根据本发明实施例，例如，封装基板300可以具有从双面覆铜板开始制作的叠层塑料结构，但本发明并不限于此情形。应当理解的是，封装基板300可以具有多个金属配线层，例如，根据本发明实施例的2层、4层或6层等。填充层130可以设置在半导体裸晶100和封装基板300之间，以环绕通孔(如铜柱)112。多个焊球310可以设置在封装基板300的第二表面300b上，用于倒装芯片封装2和印刷电路板(图中未示出)之间的电气连接。应当说明的是，本说明书中描述的不同实施例中的特征可以相互结合或组合，因此为简洁起见，针对各实施例中的相似描述不一一赘述。
在不脱离本发明的精神以及范围内，本发明可以其它特定格式呈现。所描述的实施例在所有方面仅用于说明的目的而并非用于限制本发明。本发明的保护范围当视所附的权利要求所界定者为准。本领域技术人员皆在不脱离本发明之精神以及范围内做些许更动与润饰。

Claims (21)

1.一种半导体封装，其特征在于，包括：
封装基板，具有第一表面和与该第一表面相对的第二表面；
半导体裸晶，装配在该封装基板的该第一表面上；其中，该半导体裸晶包括第一凸块接垫、第二凸块接垫、在该第一凸块接垫上的第一通孔和在该第二凸块接垫上的第二通孔；该第一凸块接垫和该第二凸块接垫在该半导体裸晶的活性表面上；
其中，该第一通孔的直径小于该第二通孔的直径。
2.如权利要求1所述的半导体封装，其特征在于，该第一通孔和该第二通孔是铜柱或铜孔。
3.如权利要求1所述的半导体封装，其特征在于，该第一通孔的直径小于50微米；和/或，该第二通孔的直径大于80微米。
4.如权利要求1所述的半导体封装，其特征在于，该第一凸块接垫的接垫尺寸小于该第二凸块接垫的接垫尺寸；或者，该第二凸块接垫与该第一凸块接垫的直径比率大于2。
5.如权利要求1所述的半导体封装，其特征在于，该半导体封装还包括：
填充层，设置在该半导体裸晶和该封装基板之间，以环绕该第一通孔和该第二通孔。
6.如权利要求1所述的半导体封装，其特征在于，该第二通孔与该第一通孔的直径比率大于2。
7.如权利要求1-6任一项所述的半导体封装，其特征在于，该第二凸块接垫与该第二通孔用于裸晶至基板连接。
8.一种半导体封装，其特征在于，包括：
封装基板，具有第一表面和与该第一表面相对的第二表面；
半导体裸晶，装配在该封装基板的该第一表面上；其中，该半导体裸晶包括第一凸块接垫、第二凸块接垫和在该第二凸块接垫上的通孔；该第一凸块接垫和该第二凸块接垫在该半导体裸晶的活性表面上；
其中，第一凸块接垫的接垫尺寸小于第二凸块接垫的接垫尺寸。
9.如权利要求8所述的半导体封装，其特征在于，该通孔是铜柱或铜孔。
10.如权利要求8所述的半导体封装，其特征在于，该第一凸块接垫是被禁用的接垫以及该第一凸块接垫上没有设置通孔。
11.如权利要求10所述的半导体封装，其特征在于，该半导体封装还包括：
填充层，设置在该半导体裸晶和该半导体基板之间，以环绕该通孔。
12.如权利要求8所述的半导体封装，其特征在于，该第二凸块接垫与该第一凸块接垫的直径比率大于2。
13.如权利要求8-12任一项所述的半导体封装，其特征在于，该第二凸块接垫用于裸晶至基板连接。
14.一种半导体封装，其特征在于，包括：
封装基板，具有第一表面和与该第一表面相对的第二表面；
第一半导体裸晶，装配在该封装基板的该第一表面上；其中，该第一半导体裸晶包括第一凸块接垫、第二凸块接垫、在该第一凸块接垫上的第一通孔和在该第二凸块接垫上的第二通孔；该第一凸块接垫和该第二凸块接垫在该半导体裸晶的活性表面上，以及，该第一通孔的直径小于该第二通孔的直径；
第二半导体裸晶，装配在该封装基板的该第一表面上。
15.如权利要求14所述的半导体封装，其特征在于，该第二半导体裸晶包括：
第三凸块接垫、第四凸块接垫、在该第三凸块接垫上的第三通孔和在该第四凸块接垫上的第四通孔；
其中，该第三凸块接垫和该第四凸块接垫在该第二半导体裸晶的活性表面上，该第三通孔的直径小于该第四通孔的直径。
16.如权利要求15所述的半导体封装，其特征在于，该第一凸块接垫、该第一通孔、该第三凸块接垫和该第三通孔通过金属线形成该第一半导体裸晶和该第二半导体裸晶之间的裸晶至裸晶连接；其中，该金属线在该封装基板中或在该封装基板上。
17.如权利要求15所述的半导体封装，其特征在于，该第一通孔、该第二通孔、该第三通孔和该第四通孔是铜柱或铜孔。
18.如权利要求14所述的半导体封装，其特征在于，该第一通孔的直径小于50微米；和/或，该第二通孔的直径大于80微米。
19.如权利要求15或16所述的半导体封装，其特征在于，该第二凸块接垫、该第二通孔、该第四凸块接垫和该第四通孔用于裸晶至基板连接。
20.如权利要求15或18所述的半导体封装，其特征在于，该第三通孔的直径小于50微米；和/或，该第四通孔的直径大于80微米。
21.如权利要求14所述的半导体封装，其特征在于，该第一凸块接垫与该第二凸块接垫的直径比率大于2。
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