CN110914984A - 具有封装级可配置性的半导体装置 - Google Patents

具有封装级可配置性的半导体装置 Download PDF

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Publication number
CN110914984A
CN110914984A CN201880047609.0A CN201880047609A CN110914984A CN 110914984 A CN110914984 A CN 110914984A CN 201880047609 A CN201880047609 A CN 201880047609A CN 110914984 A CN110914984 A CN 110914984A
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die
circuit
contact pad
substrate
semiconductor
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CN110914984B (zh
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J·E·戴维斯
J·B·普西
尹治平
K·G·杜斯曼
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明提供一种半导体装置组合件，其包含衬底及耦合到所述衬底的裸片。所述裸片包含：第一接触垫，其电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件；及第二接触垫，其电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件。所述衬底包含电耦合到所述第一接触垫及所述第二接触垫两者的衬底接触件。所述半导体装置组合件可进一步包含第二裸片，所述第二裸片包含：第三接触垫，其电耦合到所述第二裸片上的第三电路，所述第三电路包含至少第二有源电路元件；及第四接触垫，其电耦合到所述第二裸片上的第四电路，所述第四电路仅包含无源电路元件。所述衬底接触件可电耦合到所述第三接触垫且与所述第四接触垫电切断。

Description

具有封装级可配置性的半导体装置
相关申请案的交叉参考
本申请案含有与詹姆斯E.戴维斯(James E.Davis)、凯文G.杜斯曼(KevinG.Duesman)、杰弗里P.莱特(Jeffrey P.Wright)及沃伦L.波伊尔(Warren L.Boyer)的标题为“具有后探针可配置性的半导体装置(SEMICONDUCTOR DEVICES WITH POST-PROBECONFIGURABILITY)”的共同申请的美国专利申请案相关的标的物。所述相关申请案(其揭示内容以引用方式并入本文中)被转让给美光科技公司(Micron Technology,Inc.)，且由代理人档案号010829-9271.US00识别。
技术领域
本发明大体上涉及半导体装置，且更特定来说，涉及具有封装级可配置性的半导体装置。
背景技术
封装半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装在衬底上且围封在塑料保护罩中或被导热盖覆盖的一或多个半导体裸片。裸片可包含有源电路(例如，提供例如存储器单元、处理器电路及/或成像器装置的功能特征)及/或无源特征(例如，电容器、电阻器等)以及电连接到所述电路的接合垫。接合垫可电连接到保护罩外部的端子以允许将裸片连接到较高级电路。
例如，图1是半导体装置组合件100的简化部分横截面视图，其包含以叠瓦式方式堆叠在衬底101上且被囊封剂170覆盖的多个半导体裸片102及103。每一裸片包含一或多个接触垫(例如接触垫122及123)以提供到对应集成电路(例如电路162及163)的连接性。接触垫122及123可通过接线131及132(以菊炼配置展示)连接到衬底接触件121，以经由焊料球151(通过通路152)提供到电路162及163的连接性。
运用一些半导体裸片，可将各种接合垫连接到裸片中的多个电路。例如，在NAND存储器裸片中，单个接合垫可经连接到有源驱动器电路及无源ESD保护电路(例如，包含一或多个电容器)两者。ESD保护电路可经设计以提供所要电容量而保护单个有源驱动器电路。在包含具有有源驱动器电路的并联连接的多个此类NAND存储器裸片(例如，具有来自连接到相同外部端子的每一NAND存储器裸片的对应接合垫)的半导体装置组合件中，由来自并联连接的每一裸片的ESD保护电路提供的过量电容可使装置性能降级。这可通过对于不同封装密度设计不同NAND存储器裸片(例如，经配置以单独封装的NAND存储器裸片、经配置以呈两个一组的堆叠封装的具有较小电容ESD保护电路的不同NAND存储器裸片及经配置以呈四个一组的堆叠封装的具有甚至更小电容ESD保护电路的又一NAND存储器裸片等)而解决，但对于每一可能封装配置设计及制作多个不同半导体裸片极其昂贵。因此，需要一种可取决于封装裸片的配置而配置有不同量的ESD保护的半导体裸片。
附图说明
图1是包含堆叠在衬底上的多个半导体裸片的半导体装置组合件的简化部分横截面视图。
图2是半导体装置组合件的简化示意图。
图3是根据本技术的实施例的半导体装置的简化示意图。
图4到6是根据本技术的实施例的半导体装置组合件的简化示意图。
图7是根据本技术的实施例的半导体装置的简化示意图。
图8到14是根据本技术的实施例的半导体装置组合件的简化示意图。
图15到17是根据本技术的实施例的半导体装置的简化部分横截面视图。
图18是展示包含根据本技术的实施例配置的半导体装置组合件的系统的示意图。
图19是说明根据本技术的实施例的制造半导体装置的方法的流程图。
具体实施方式
在以下描述中，论述众多特定细节以提供对本技术的实施例的透彻且详尽描述。然而，所属领域的技术人员将认识到，本发明可在无一或多个特定细节的情况下实践。在其它情况中，未展示或未详细描述通常与半导体装置相关联的众所周知结构或操作以避免使本技术的其它方面不清楚。一般来说，应了解，除本文中揭示的所述特定实施例以外，各种其它装置、系统及方法也可在本技术的范围内。
如上文论述，当具有连接到与有源电路(例如，驱动器电路)相同的接合垫的ESD保护电路的半导体裸片呈不同封装密度连接在一起时，由ESD保护电路提供的电容量无法对于每一封装密度优化。因此，根据本技术的半导体装置的若干实施例可提供所提供电容的封装级可配置性以克服这个挑战。
本技术的若干实施例涉及半导体装置组合件，其包含衬底及耦合到所述衬底的裸片。所述裸片包含：第一接触垫，其电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件；及第二接触垫，其电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件。所述衬底包含电耦合到所述第一接触垫及所述第二接触垫两者的衬底接触件。所述半导体装置组合件可进一步包含第二裸片，所述第二裸片包含：第三接触垫，其电耦合到所述第二裸片上的第三电路，所述第三电路包含至少第二有源电路元件；及第四接触垫，其电耦合到所述第二裸片上的第四电路，所述第四电路仅包含无源电路元件。所述衬底接触件可电耦合到所述第三接触垫且与所述第四接触垫电切断。
下文描述半导体装置的若干实施例的特定细节。术语“半导体装置”通常是指包含半导体材料的固态装置。半导体装置可包含例如半导体衬底、晶片、或从晶片或衬底单粒化的裸片。贯穿本发明，通常在半导体裸片的背景中描述半导体装置；然而，半导体装置不限于半导体裸片。
术语“半导体装置封装”可指具有并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分或完全囊封至少一个半导体装置的外壳或壳体。半导体装置封装也可包含承载一或多个半导体装置且附接到或以其它方式并入到壳体中的中介衬底。术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装及/或衬底(例如，中介衬底、支撑衬底或其它适合衬底)的组合件。可例如呈离散封装形式、条带或矩阵形式及/或晶片面板形式制造半导体装置组合件。如本文中使用，术语“垂直”、“横向”、“上”及“下”可指半导体装置或装置组合件中的特征鉴于图中所展示的定向的相对方向或位置。例如，“上”或“最上”可分别指定位成比另一特征或相同特征的部分更靠近或最靠近页面顶部的特征。然而，这些术语应广义地被解释为包含具有其它定向的半导体装置，例如倒转或倾斜定向，其中顶部/底部、上方/下方、上面/下面、上/下及左/右可取决于定向而互换。
图2是半导体装置组合件200的简化示意图，其包含耦合到衬底201的半导体裸片202。所述裸片包含接触垫(例如接触垫211及212)，其各自连接到具有有源组件的集成电路(示意性地说明为驱动器(DRV)电路)及具有无源组件的集成电路(示意性地说明为静电放电(ESD)保护电路)两者。接触垫211及212通过接线230电耦合到衬底接触件221及222。如参考图2可见，如果半导体裸片202已配置有适于为单个驱动器电路提供ESD保护的电容量，那么将另一此类半导体裸片添加到组合件200可非所要地增加衬底接触件221及222所“经受”的电容。
为解决这个问题，本技术的实施例可提供一种半导体裸片，其中有源电路及经配置以对其提供ESD保护的无源电路经连接到单独接触垫，使得不管提供在封装组合件中的裸片数是多少，都可提供所要电容量。例如，图3是根据本技术的实施例的半导体装置300的简化示意图。半导体装置300包含用于提供到半导体装置300中的电路的连接性的多个接触垫，例如第一到第四接触垫311到314。例如，第一接触垫311提供到具有有源组件的第一电路371(例如，驱动器电路)的连接性，且第二接触垫312提供到具有无源组件的第二电路372(例如，ESD保护电路)的连接性。类似地，第三接触垫313提供到具有有源组件的第三电路373(例如，驱动器电路)的连接性，且第四接触垫314提供到具有无源组件的第四电路374(例如，ESD保护电路)的连接性。通过为每一无源电路提供专用接触垫，半导体装置300利用多个相同半导体裸片形成可能的不同封装密度，同时提供所要量的ESD保护且无(例如)引起驱动器电路371及373消耗过量电力的过量电容。
这参考图4可更好地理解，图4是根据本技术的实施例的半导体装置组合件400的简化示意图。组合件400包含衬底401以及两个半导体裸片402及403(例如，相同半导体裸片)。如同上文在图3中说明的半导体装置300，每一半导体裸片402及403包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第四接触垫411到414。因为每一ESD保护电路具备专用接触垫，所以组合件400可配置有针对每一驱动器电路的所要量的ESD保护。
如参考图4可见，衬底401包含两个衬底接触件421及422。第一衬底接触件421(例如，通过接线430)经连接到组合件400中的每一半导体裸片402及403的第一接触垫411(对应于驱动器电路)，但其经连接到组合件400中的仅一个半导体裸片402的第二接触垫412(对应于ESD保护电路)。类似地，第二衬底接触件422(例如，通过接线430)经连接到组合件400中的每一半导体裸片402及403的第三接触垫413(对应于驱动器电路)，但其经连接到组合件400中的仅一个半导体裸片402的第四接触垫414(对应于ESD保护电路)。通过使上半导体裸片403上的第二接触垫412及第四接触垫414(对应于ESD保护电路)与衬底接触件421及422电切断，每一衬底接触件421及422所连接的电路的电容小于来自组合件400中的每一裸片的ESD保护电路被连接时的电容。
尽管已将图4描述且说明为包含多个相同半导体裸片，但在本技术的其它实施例中，可提供具有类似特征的具不同类型裸片的半导体装置组合件。例如，在一个实施例中，半导体装置组合件可包含逻辑裸片及存储器裸片，其中的一者或两者可包含用于在封装期间视需要连接无源电路的离散接触垫。此外，尽管已将图4描述且说明为包含具有两个驱动器电路的半导体裸片，但所属领域的技术人员将容易明白，这个实施例仅为一个实例，且也可提供具有不同数目个驱动器电路的半导体裸片。此外，已将图4描述且说明为提供与用于驱动器电路的接触垫分离的用于ESD保护电路的接触垫，在其它实施例中可提供具有除驱动器以外的其它有源元件的电路，且同样可提供仅包含无源组件(例如，电阻器、电容器、电感器等)的其它电路。
尽管已将图4描述且说明为在每一衬底接触件421及422处具有用于提供到组合件400中的半导体裸片402中的一者中的多个接触垫的连接性的多个接线，但在本技术的其它实施例中，可使用其它接线布置。例如，图5是根据本技术的实施例的半导体装置组合件500的简化示意图。组合件500包含衬底501以及两个半导体裸片502及503，其各自包含多个接触垫(例如第一到第四接触垫511到514)以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性。
如参考图5可见，衬底501包含两个衬底接触件521及522。第一衬底接触件521通过接线530连接到第一半导体裸片502的第一接触垫511(对应于驱动器电路)，第一半导体裸片502的第一接触垫511又通过另一接线530连接到第二半导体裸片503的第一接触垫511(对应于驱动器电路)。第一衬底接触件521(例如，通过第一半导体裸片502的第一接触垫511与第二接触垫512之间的接线)进一步连接到组合件500中的仅一个半导体裸片502的第二接触垫512(对应于ESD保护电路)。类似地，第二衬底接触件522通过接线530连接到第一半导体裸片502的第三接触垫513(对应于驱动器电路)，第一半导体裸片502的第三接触垫513又通过另一接线530连接到第二半导体裸片503的第三接触垫513(对应于驱动器电路)。第二衬底接触件522(例如，通过第一半导体裸片502的第三接触垫513与第四接触垫514之间的接线)进一步连接到组合件500中的仅一个半导体裸片502的第四接触垫514(对应于ESD保护电路)。
又其它接线布置是可行的(例如如图6中说明)，图6是根据本技术的实施例的半导体装置组合件600的简化示意图。组合件600包含衬底601以及两个半导体裸片602及603，其各自包含多个接触垫(例如第一到第四接触垫611到614)以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性。
如参考图6可见，衬底601包含两个衬底接触件621及622。第一衬底接触件621通过接线630直接连接到第一半导体裸片602的第一接触垫611(对应于驱动器电路)，且通过另一接线直接连接到第二半导体裸片603的第一接触垫611(对应于驱动器电路)。第一衬底接触件621(例如，通过第一半导体裸片602的第一接触垫611与第二接触垫612之间的接线)进一步连接到组合件600中的仅一个半导体裸片602的第二接触垫612(对应于ESD保护电路)。类似地，第二衬底接触件622通过接线630直接连接到第一半导体裸片602的第三接触垫613(对应于驱动器电路)，且通过另一接线直接连接到第二半导体裸片603的第三接触垫613(对应于驱动器电路)。第二衬底接触件622(例如，通过第一半导体裸片602的第三接触垫613与第四接触垫614之间的接线)进一步连接到组合件600中的仅一个半导体裸片602的第四接触垫614(对应于ESD保护电路)。
尽管在前述实例中，已将半导体裸片描述且说明为包含对应于每一驱动器电路的单个ESD保护电路，但在本技术的其它实施例中，可通过包含具有对应于半导体裸片上的每一驱动器电路的专用接触垫的多个ESD保护电路而提供额外可配置性。例如，图7是根据本技术的实施例的半导体装置700的简化示意图。半导体装置700包含用于提供到半导体装置700中的电路的连接性的多个接触垫，例如第一到第六接触垫711到716。例如，第一接触垫711提供到具有有源组件的第一电路771(例如，驱动器电路)的连接性，且第二接触垫712及第三接触垫713分别提供到仅包含无源组件的第二电路772及第三电路773(例如，ESD保护电路)的连接性。类似地，第四接触垫714提供到具有有源组件的第四电路774(例如，驱动器电路)的连接性，且第五接触垫715及第六接触垫716分别提供到仅包含无源组件的第五电路775及第六电路776(例如，ESD保护电路)的连接性。通过为每一有源电路提供各自具有其自身专用接触垫的多个对应无源电路，半导体装置700利用多个相同半导体裸片形成可能的不同封装密度，同时提供所要量的ESD保护而无(例如)引起驱动器电路771及774消耗过量电力的过量电容。
这参考图8可更好地理解，图8是根据本技术的实施例的半导体装置组合件800的简化示意图。组合件800包含衬底801以及两个半导体裸片802及803(例如，相同半导体裸片)。如同上文在图7中说明的半导体装置700，每一半导体裸片802及803包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第六接触垫811到816。因为每一ESD保护电路具备专用接触垫，所以组合件800可配置有针对每一驱动器电路的所要量的ESD保护。
如参考图8可见，衬底801包含两个衬底接触件821及822。第一衬底接触件821(例如，通过接线830)经连接到组合件800中的每一半导体裸片802及803的第一接触垫811(对应于驱动器电路)，且经连接到组合件800中的每一半导体裸片802及803的第二接触垫812(对应于ESD保护电路)，但其经连接到组合件800中的仅一个半导体裸片802的第三接触垫813(对应于另一ESD保护电路)。类似地，第二衬底接触件822(例如，通过接线830)经连接到组合件800中的每一半导体裸片802及803的第四接触垫814(对应于驱动器电路)，且经连接到组合件800中的每一半导体裸片802及803的第五接触垫815(对应于ESD保护电路)，但其经连接到组合件800中的仅一个半导体裸片802的第六接触垫816(对应于另一ESD保护电路)。通过使上半导体裸片803上的第三接触垫813及第六接触垫816(对应于ESD保护电路)与衬底接触件821及822电切断，每一衬底接触件821及822所连接的电路的电容小于来自组合件800中的每一裸片的ESD保护电路被连接时的电容。
尽管在前述实施例中，已将半导体装置组合件说明且描述为具有两个半导体裸片，但在本技术的其它实施例中，半导体装置组合件可包含不同数目个裸片。例如，图9是根据本技术的实施例的包含四个半导体裸片的半导体装置组合件900的简化示意图。组合件900包含衬底901以及四个半导体裸片902到905(例如，相同半导体裸片)。如同上文在图3中说明的半导体装置300，每一半导体裸片902到905包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第四接触垫911到914。因为每一ESD保护电路具备专用接触垫，所以组合件900可配置有针对每一驱动器电路的所要量的ESD保护。
如参考图9可见，衬底901包含两个衬底接触件921及922。第一衬底接触件921(例如，通过接线930)经连接到组合件900中的每一半导体裸片902到905的第一接触垫911(对应于驱动器电路)，但其经连接到组合件900中的仅一个半导体裸片902的第二接触垫912(对应于ESD保护电路)。类似地，第二衬底接触件922(例如，通过接线930)经连接到组合件900中的每一半导体裸片902到905的第三接触垫913(对应于驱动器电路)，但其经连接到组合件900中的仅一个半导体裸片902的第四接触垫914(对应于ESD保护电路)。通过使三个半导体裸片903到905上的第二接触垫912及第四接触垫914(对应于ESD保护电路)与衬底接触件921及922电切断，每一衬底接触件921及922所连接的电路的电容小于来自组合件900中的每一裸片的ESD保护电路都被连接时的电容。
尽管在图9中说明的实施例中将组合件中的仅一个裸片的ESD保护电路连接到衬底接触件，但在其它实施例中，半导体装置组合件可包含具有连接到(若干)其衬底接触件的ESD保护电路的多个裸片。例如，图10是根据本技术的实施例的半导体装置组合件1000的简化示意图。组合件1000包含衬底1001及四个半导体裸片1002到1005(例如，相同半导体裸片)，其各自包含多个接触垫(例如第一到第四接触垫1011到1014)以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性。
如参考图10可见，衬底1001包含两个衬底接触件1021及1022。第一衬底接触件1021(例如，通过接线1030)经连接到组合件1000中的每一半导体裸片1002到1005的第一接触垫1011(对应于驱动器电路)，但其经连接到组合件1000中的仅两个半导体裸片1002及1003的第二接触垫1012(对应于ESD保护电路)。类似地，第二衬底接触件1022(例如，通过接线1030)经连接到组合件1000中的每一半导体裸片1002到1005的第三接触垫1013(对应于驱动器电路)，但其经连接到组合件1000中的仅两个半导体裸片1002及1003的第四接触垫1014(对应于ESD保护电路)。通过使两个半导体裸片1004到1005上的第二接触垫1012及第四接触垫1014(对应于ESD保护电路)与衬底接触件1021及1022电切断，每一衬底接触件1021及1022所连接的电路的电容小于来自组合件1000中的每一裸片的ESD保护电路被连接时的电容。
尽管在前述实施例中，已说明其中至少一个裸片包含所附接ESD保护电路的半导体装置组合件，但在本技术的其它实施例中，半导体装置组合件可包含所有包含未连接的ESD保护电路的多个裸片(例如，依赖于多个驱动器电路的固有电容，使得不需要额外电容)。例如，图11是根据本技术的实施例的半导体装置组合件1100的简化示意图。组合件1100包含衬底1101及四个半导体裸片1102到1105(例如，相同半导体裸片)，其各自包含多个接触垫(例如第一到第四接触垫1111到1114)以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性。
如参考图11可见，衬底1101包含两个衬底接触件1121及1122。第一衬底接触件1121(例如，通过接线1130)经连接到组合件1100中的每一半导体裸片1102到1105的第一接触垫1111(对应于驱动器电路)，但其未经连接到组合件1100中的半导体裸片1102到1105中的任一者的第二接触垫1112(对应于ESD保护电路)。类似地，第二衬底接触件1122(例如，通过接线1130)经连接到组合件1100中的每一半导体裸片1102到1105的第三接触垫1113(对应于驱动器电路)，但其未经连接到组合件1100中的半导体裸片1102到1105中的任一者的第四接触垫1114(对应于ESD保护电路)。通过使所有半导体裸片1102到1105上的第二接触垫1112及第四接触垫1114(对应于ESD保护电路)与衬底接触件1121及1122电切断，每一衬底接触件1121及1122所连接的电路的电容小于来自组合件1100中的裸片中的任一者的ESD保护电路被连接时的电容。
尽管在前述实施例中，将用于每一所连接ESD保护电路的专用接触垫说明且描述为具有对应专用接线，但在本技术的其它实施例中，可以其它方式连接接触垫。例如，图12是根据本技术的实施例的半导体装置组合件1200的简化示意图。组合件1200包含衬底1201以及两个半导体裸片1202及1203(例如，相同半导体裸片)。每一半导体裸片1202及1203包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第四接触垫1211到1214。第二接触垫1212及第四接触垫1214分别经安置成紧邻对应第一接触垫1211及第三接触垫1213，使得可使用单个接线1230来连接两个垫。
如参考图12可见，衬底1201包含两个衬底接触件1221及1222。第一衬底接触件1221通过单个接线1230(例如，运用焊键1241)连接到第一半导体裸片1202的第一接触垫1211(对应于驱动器电路)及第二接触垫1212(对应于ESD保护电路)两者。第一衬底接触件1221通过接线1230进一步连接在连接第一半导体裸片1202的第一接触垫1211及第二接触垫1212的焊键1241与第二半导体裸片1203的第一接触垫1211(对应于驱动器电路)之间。类似地，第二衬底接触件1222通过单个接线1230(例如，运用焊键1241)连接到第一半导体裸片1202的第三接触垫1213(对应于驱动器电路)及第四接触垫1214(对应于ESD保护电路)两者。第二衬底接触件1222通过接线1230进一步连接在连接第一半导体裸片1202的第三接触垫1213及第四接触垫1214的焊键1241与第二半导体裸片1203的第三接触垫1213(对应于驱动器电路)之间。
运用单个接线连接到多个接触垫的前述方法可扩展到其中对于每一驱动器电路提供一个以上ESD保护电路的本技术的实施例。例如，图13是根据本技术的实施例的半导体装置组合件1300的简化示意图。组合件1300包含衬底1301以及两个半导体裸片1302及1303(例如，相同半导体裸片)。每一半导体裸片1302及1303包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第六接触垫1311到1316。第二接触垫1312及第三接触垫1313经安置成紧邻对应第一接触垫1311，使得可使用单个接线1330来将第一接触垫1311连接到第二接触垫1312及第三接触垫1313中的一者或两者(或两者都不连接)。类似地，第五接触垫1315及第六接触垫1316经安置成紧邻对应第四接触垫1314，使得可使用单个接线1330来将第四接触垫1314连接到第五接触垫1315及第六接触垫1316中的一者或两者(或两者都不连接)。
如参考图13可见，衬底1301包含两个衬底接触件1321及1322。第一衬底接触件1321通过单个接线1330(例如，运用第一焊键1341)连接到第一半导体裸片1302的第一、第二及第三接触垫1311到1313。第一衬底接触件1321通过接线1330进一步连接在第一焊键1341与跨越第二半导体裸片1303的第一接触垫1311及第三接触垫1313的第二焊键1342之间。类似地，第二衬底接触件1322通过单个接线1330(例如，运用第一焊键1341)连接到第一半导体裸片1302的第四、第五及第六接触垫1314到1316。第二衬底接触件1322通过接线1330进一步连接在第一焊键1341与跨越第二半导体裸片1303的第四接触垫1314及第六接触垫1316的第二焊键1342之间。
运用单个接线连接到多个接触垫的前述方法可扩展到其中可任选地通过单个接线连接裸片上的多个电路的本技术的实施例。例如，图14是根据本技术的实施例的半导体装置组合件1400的简化示意图。组合件1400包含衬底1401以及两个半导体裸片1402及1403(例如，相同半导体裸片)。每一半导体裸片1402及1403包含各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接性的多个接触垫，例如第一到第六接触垫1411到1416。以上文在图13中说明的方式，将第二接触垫1412及第三接触垫1414安置成紧邻对应第一接触垫1411，使得可使用单个接线1430来将第一接触垫1411连接到第二接触垫1412及第三接触垫1414中的一者或两者(或两者都不连接)。类似地，将第五接触垫1415及第六接触垫1416安置成紧邻对应第四接触垫1414，使得可使用单个接线1430来将第四接触垫1414连接到第五接触垫1415及第六接触垫1416中的一者或两者(或两者都不连接)。然而，不同于图13中，第三接触垫1413及第六接触垫1416未经连接到额外ESD保护电路，而是连接到第二驱动器电路。
如参考图14可见，衬底1401包含两个衬底接触件1421及1422。第一衬底接触件1421通过单个接线1430(例如，运用第一焊键1441)连接到第一半导体裸片1402的第一、第二及第三接触垫1411到1414。第一衬底接触件1421通过接线1430进一步连接在第一焊键1441与跨越第二半导体裸片1403的第一接触垫1411及第三接触垫1414的第二焊键1442之间。类似地，第二衬底接触件1422通过单个接线1430(例如，运用第一焊键1441)连接到第一半导体裸片1402的第四、第五及第六接触垫1414到1416。第二衬底接触件1422通过接线1430进一步连接在第一焊键1441与跨越第二半导体裸片1403的第四接触垫1414及第六接触垫1416的第二焊键1442之间。
以类似方式，本技术的其它实施例可提供具有用于任选地连接任何数目个不同电路的紧密间隔的接合垫、除ESD保护电路及驱动器电路以外还具有其它所要功能或具有代替ESD保护电路及驱动器电路的任何所要功能的半导体裸片。此外，可以若干方式中的任一者提供紧密间隔的接合垫，例如上文在图12到14的实例中说明的接合垫。例如，图15说明根据本技术的实施例的半导体装置的简化部分横截面视图。在图15中说明的半导体装置1501中，紧密间隔的接合垫1502及1503经提供在钝化或聚酰亚胺材料层1505下方，且因此通过小的钝化或聚酰亚胺材料区1506分离。可提供足够体积的焊料球1504以桥接这个钝化或聚酰亚胺材料区1506，且因此连接紧密间隔的接合垫1502及1503。
通过进一步实例，图16说明根据本技术的实施例的另一半导体装置的简化部分横截面视图。在图16中说明的半导体装置1601中，紧密间隔的接合垫1602及1603经提供在钝化或聚酰亚胺材料层1605下方，但已进行额外工艺步骤以从紧密间隔的接合垫1602与1603之间消除钝化或聚酰亚胺材料1605(例如，通过在紧密间隔的接合垫1602与1603之间的区下方包含蚀刻停止材料1606而允许从其间蚀除钝化或聚酰亚胺材料1605)。这个布置促进容易地将焊料球1604连接到紧密间隔的接合垫1602及1603两者(由于其间不存在不可湿润材料)。
在又一实例中，图17说明根据本技术的实施例的另一半导体装置的简化部分横截面视图。在图17中说明的半导体装置1701中，紧密间隔的接合垫1702及1703经提供在钝化或聚酰亚胺材料层1705上方(例如，在重布层中)。这个布置也促进容易地将焊料球1704连接到紧密间隔的接合垫1702及1703两者(由于其间不存在不可湿润材料)。
尽管在前述实例中，已说明其中将具有无源元件的电路(例如，ESD保护电路)说明且描述为具有用于经由接线提供连接性的专用接触垫的半导体装置封装，但所属领域的技术人员将容易了解，也可使用裸片到裸片或裸片到衬底连接的其它方法来提供封装级连接可配置性。例如，其中无源组件的电路具有专用TSV的半导体裸片可以非叠瓦式堆叠布置，其中通过包含或省略堆叠中的相邻TSV之间的焊料接头而提供任选连接性。同样可提供其它互连技术。
此外，尽管在前述实例中，已将半导体装置组合件描述为包含单个半导体裸片堆叠，但在本技术的其它实施例中，半导体装置组合件可包含其中可任选地经由专用接触垫连接无源电路的多个半导体裸片堆叠。例如，在本技术的一个实施例中，半导体装置组合件可包含多个横向分离的半导体裸片堆叠(例如，各自四个裸片的两个堆叠、各自八个裸片的两个堆叠、各自四个裸片的四个堆叠等)，其中每一堆叠中并非所有可用ESD电路电耦合到有源电路。在另一实施例中，半导体装置组合件可包含单个半导体裸片堆叠，其中所述堆叠中的裸片的子组单独地连接到衬底(例如，具有八个裸片的叠瓦式堆叠被分组为电耦合到衬底的第一子组，其中第一子组中并非所有可用裸片都具有电耦合的ESD电路，且前八个裸片上方的另外八个裸片(其具有与第一子组的方向相反的叠瓦偏移方向)被分组为与第一子组单独地电耦合到衬底的第二子组，其中第二子组中并非所有可用裸片都具有电耦合的ESD电路等)。
上文参考图3到17描述的半导体装置组合件中的任一者可并入到无数更大及/或更复杂系统中的任一者中，所述系统的代表性实例是图18中示意性地展示的系统1800。系统1800可包含半导体装置组合件1802、电源1804、驱动器1806、处理器1808及/或其它子系统或组件1810。半导体装置组合件1802可包含通常与上文参考图3到15描述的半导体装置的特征类似的特征。所得系统1800可执行多种功能中的任一者，例如存储器存储、数据处理及/或其它适合功能。因此，代表性系统1800可包含(不限于)手持装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、车辆、电器及其它产品。系统1800的组件可经容置在单个单元中或经分布在多个互连单元上(例如，通过通信网络)。系统1800的组件还可包含远程装置及多种计算机可读媒体中的任一者。
图19是说明制造半导体装置组合件的方法的流程图。所述方法包含：提供包含衬底接触件的衬底(框1910)，且将一或多个半导体裸片耦合到衬底(框1920)。一或多个半导体裸片中的每一者包含：第一接触垫，其电耦合到半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件；及第二接触垫，其电耦合到半导体裸片上的第二电路，所述第二电路仅包含无源电路元件。所述方法进一步包含：将所有一或多个半导体裸片的第一接触垫电耦合到衬底接触件(框1930)，且将一或多个半导体裸片中的至少一者的第二接触垫电耦合到衬底接触件(框1940)。
从前文将明白，本文中已出于说明目的描述本发明的特定实施例，但可在不脱离本发明的范围的情况下进行各种修改。因此，本发明除受所附权利要求书限制外并不受限。

Claims (21)

1.一种半导体装置组合件，其包括：
衬底；
裸片，其经耦合到所述衬底，所述裸片包含：
第一接触垫，其电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件，及
第二接触垫，其电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件；
其中所述衬底包含电耦合到所述裸片上的所述第一接触垫及所述第二接触垫两者的衬底接触件。
2.根据权利要求1所述的半导体装置组合件，其中所述裸片是第一裸片，所述半导体装置组合件进一步包括：
第二裸片，其包含：
第三接触垫，其电耦合到所述第二裸片上的第三电路，所述第三电路包含至少第二有源电路元件，及
第四接触垫，其电耦合到所述第二裸片上的第四电路，所述第四电路仅包含无源电路元件；
其中所述衬底接触件电耦合到所述第二裸片上的所述第三接触垫，且
其中所述第二裸片上的所述第四接触垫与所述衬底接触件电切断。
3.根据权利要求2所述的半导体装置组合件，其中所述第一裸片及所述第二裸片是相同裸片，其中所述第一裸片上的所述第一接触垫对应于所述第二裸片上的所述第三接触垫，且所述第一裸片上的所述第二接触垫对应于所述第二裸片上的所述第四接触垫。
4.根据权利要求2所述的半导体装置组合件，其中所述第一裸片及所述第二裸片是以叠瓦式配置堆叠。
5.根据权利要求2所述的半导体装置组合件，其中所述第一裸片进一步包含第五接触垫，所述第五接触垫电耦合到所述第一裸片上的第五电路，所述第五电路仅包含无源电路元件，且其中所述衬底接触件电耦合到所述第一裸片上的所述第五接触垫。
6.根据权利要求1所述的半导体装置组合件，其中所述第一电路是驱动器电路。
7.根据权利要求1所述的半导体装置组合件，其中所述第二电路包含用于提供静电放电ESD保护的一或多个电容器。
8.根据权利要求1所述的半导体装置组合件，其中所述衬底接触件通过一或多个接线电耦合到所述第一接触垫及所述第二接触垫。
9.根据权利要求1所述的半导体装置组合件，其中所述衬底接触件通过所述第一接触垫与所述第三接触垫之间的接线电耦合到所述第三接触垫。
10.根据权利要求1所述的半导体装置组合件，其中裸片是NAND存储器裸片。
11.一种半导体装置组合件，其包括：
衬底，其包含衬底接触件；及
多个半导体裸片，其各自包含：
第一接触垫，其电耦合到所述半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件，及
第二接触垫，其电耦合到所述半导体裸片上的第二电路，所述第二电路仅包含无源电路元件；
其中所有所述多个半导体裸片的所述第一接触垫电耦合到所述衬底接触件，且其中一些但并非所有所述多个半导体裸片的所述第二接触垫电耦合到所述衬底接触件。
12.根据权利要求11所述的半导体装置组合件，其中所述多个半导体裸片中的每一者的所述第一电路是驱动器电路。
13.根据权利要求11所述的半导体装置组合件，其中所述多个半导体裸片中的每一者的所述第二电路包含用于提供静电放电ESD保护的一或多个电容器。
14.根据权利要求11所述的半导体装置组合件，其中所述多个半导体裸片是相同半导体裸片。
15.根据权利要求11所述的半导体装置组合件，其中所述多个半导体裸片包括NAND存储器裸片。
16.根据权利要求11所述的半导体装置组合件，其中所述多个半导体裸片包括两个以上半导体裸片。
17.一种制造半导体装置组合件的方法，其包括：
提供包含衬底接触件的衬底；
将一或多个半导体裸片耦合到所述衬底，其中所述一或多个半导体裸片中的每一者包含：
第一接触垫，其电耦合到所述半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件，及
第二接触垫，其电耦合到所述半导体裸片上的第二电路，所述第二电路仅包含无源电路元件；
将所有所述一或多个半导体裸片的所述第一接触垫电耦合到所述衬底接触件；及
将所述一或多个半导体裸片中的至少一者的所述第二接触垫电耦合到所述衬底接触件。
18.根据权利要求17所述的方法，其中所述一或多个半导体裸片包括多个半导体裸片，且其中将所述一或多个半导体裸片中的至少一者的所述第二接触垫电耦合到所述衬底接触件包括将一些但并非所有所述多个半导体裸片的所述第二接触垫电耦合到所述衬底接触件。
19.根据权利要求18所述的方法，其中所述多个半导体裸片是相同半导体裸片。
20.根据权利要求17所述的方法，其中所述一或多个半导体裸片中的每一者的所述第一电路是驱动器电路。
21.根据权利要求17所述的方法，其中所述一或多个半导体裸片中的每一者的所述第二电路包含用于提供静电放电ESD保护的一或多个电容器。
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