TW201933581A - 具有封裝階段可組態性之半導體裝置 - Google Patents

具有封裝階段可組態性之半導體裝置 Download PDF

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Publication number
TW201933581A
TW201933581A TW107133099A TW107133099A TW201933581A TW 201933581 A TW201933581 A TW 201933581A TW 107133099 A TW107133099 A TW 107133099A TW 107133099 A TW107133099 A TW 107133099A TW 201933581 A TW201933581 A TW 201933581A
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Taiwan
Prior art keywords
circuit
contact pad
die
contact
substrate
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TW107133099A
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TWI680565B (zh
Inventor
詹姆斯 Ｅ 戴维斯
約翰 Ｂ 普斯
治平 尹
凱文 Ｇ 都斯曼
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美商美光科技公司
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    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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Abstract

一種半導體裝置總成包含一基板及經耦合至該基板之一晶粒。該晶粒包含：一第一接觸墊，其經電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其經電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件。該基板包含經電耦合至該第一接觸墊及該第二接觸墊兩者之一基板接觸件。該半導體裝置總成進一步可包含一第二晶粒，該第二晶粒包含：一第三接觸墊，其經電耦合至該第二晶粒上之一第三電路，該第三電路包含至少一第二主動電路元件；及一第四接觸墊，其經電耦合至該第二晶粒上之一第四電路，該第四電路僅包含被動電路元件。該基板接觸件可經電耦合至該第三接觸墊，且係與該第四接觸墊電性斷開。

Description

具有封裝階段可組態性之半導體裝置
本發明大體上係關於半導體裝置，且更特定言之係關於具有封裝階段可組態性之半導體裝置。
封裝半導體晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於一基板上且圍封於一塑膠保護罩中或由一導熱蓋覆蓋之一或多個半導體晶粒。晶粒可包含主動電路(例如，其等提供諸如記憶體胞、處理器電路及/或成像器裝置之功能構件)及/或被動構件(例如，電容器、電阻器等)，以及電連接至該等電路之接合墊。接合墊可電連接至保護罩外部之端子以容許將晶粒連接至較高層級電路。
例如，圖1係一半導體裝置總成100之一簡化部分橫截面視圖，其包含以一疊瓦式方式堆疊於一基板101上且由一囊封劑170覆蓋之多個半導體晶粒102及103。各晶粒包含一或多個接觸墊(諸如接觸墊122及123)以提供至一對應積體電路(諸如電路162及163)之連接性。接觸墊122及123可藉由接線131及132 (以一菊鍊組態展示)連接至一基板接觸件121，以經由焊料球151藉由通路152提供至電路162及163之連接性。
運用一些半導體晶粒，可將各種接合墊連接至一晶粒中之多個電路。例如，在一NAND記憶體晶粒中，一單一接合墊可連接至一主動驅動器電路及一被動ESD保護電路(例如，其包含一或多個電容器)兩者。ESD保護電路可經設計以提供一所要電容量而保護單一主動驅動器電路。在包含並聯連接之具有主動驅動器電路之多個此等NAND記憶體晶粒(例如，具有連接至相同外部端子之來自各NAND記憶體晶粒之對應接合墊)之一半導體裝置總成中，由來自並聯連接之各晶粒之ESD保護電路提供的過量電容可使裝置效能降級。此可藉由針對不同封裝密度設計不同NAND記憶體晶粒(例如，經組態以單獨封裝之一NAND記憶體晶粒、經組態以依兩個之一堆疊封裝之具有較小電容ESD保護電路的一不同NAND記憶體晶粒，及經組態以依四個之一堆疊封裝之具有甚至更小電容ESD保護電路之另一NAND記憶體晶粒等)而解決，但針對各可能封裝組態設計及製作多個不同半導體晶粒極其昂貴。因此，需要一種可取決於封裝晶粒之組態而組態有不同量之ESD保護的半導體晶粒。
在一些實施例中，一種半導體裝置總成包括一基板及耦合至該基板之一晶粒。該晶粒包含：一第一接觸墊，其電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件。該基板包含電耦合至該晶粒上之該第一接觸墊及該第二接觸墊兩者之一基板接觸件。
在一些實施例中，一種半導體裝置總成包括包含一基板接觸件之一基板及複數個半導體晶粒。該複數個半導體晶粒之各者包含：一第一接觸墊，其電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件。全部該複數個半導體晶粒之該等第一接觸墊電耦合至該基板接觸件。一些但少於全部之該複數個半導體晶粒之該等第二接觸墊電耦合至該基板接觸件。
在一些實施例中，一種製造一半導體裝置總成之方法包括：提供包含一基板接觸件之一基板；將一或多個半導體晶粒耦合至該基板，其中該一或多個半導體晶粒之各者包含：一第一接觸墊，其電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件；將全部該一或多個半導體晶粒之該等第一接觸墊電耦合至該基板接觸件；及將該一或多個半導體晶粒之至少一者之該等第二接觸墊電耦合至該基板接觸件。
相關申請案之交叉參考
本申請案含有與James E. Davis、Kevin G. Duesman、Jeffrey P. Wright及Warren L. Boyer之標題為「SEMICONDUCTOR DEVICES WITH POST-PROBE CONFIGURABILITY」之一共同申請之美國專利申請案有關的標的物。該相關申請案(其之揭示內容係以引用的方式併入本文中)被讓與Micron Technology公司，且係由代理人檔案號010829-9271.US00識別。
在以下描述中，論述許多具體細節以提供對本技術之實施例之一透徹且詳盡(enabling)描述。然而，熟習相關技術者將認識到，本發明可在無該等具體細節之一或多者之情況下實踐。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以避免使本技術之其他態樣不清楚。一般而言，應瞭解，除本文中揭示之該等特定實施例之外，各種其他裝置、系統及方法亦可在本技術之範疇內。
如上文論述，當具有連接至與一主動電路(例如，一驅動器電路)相同之接合墊之一ESD保護電路的半導體晶粒依不同封裝密度連接在一起時，由ESD保護電路提供之電容量無法針對各封裝密度最佳化。因此，根據本技術之半導體裝置之若干實施例可提供一經提供電容之封裝階段可組態性以克服此挑戰。
本技術之若干實施例係關於半導體裝置總成，該半導體裝置總成包含一基板及耦合至該基板之一晶粒。該晶粒包含：一第一接觸墊，其電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件。該基板包含電耦合至該第一接觸墊及該第二接觸墊兩者之一基板接觸件。該等半導體裝置總成進一步可包含：一第二晶粒，其包含：一第三接觸墊，其電耦合至該第二晶粒上之一第三電路，該第三電路包含至少一第二主動電路元件；及一第四接觸墊，其電耦合至該第二晶粒上之一第四電路，該第四電路僅包含被動電路元件。該基板接觸件可電耦合至該第三接觸墊且與該第四接觸墊電性斷開。
下文描述半導體裝置之若干實施例之具體細節。術語「半導體裝置」大體上指代包含一半導體材料之一固態裝置。一半導體裝置可包含例如一半導體基板、晶圓或自一晶圓或基板單粒化之晶粒。在本發明各處，大體上在半導體晶粒之內容背景中描述半導體裝置；然而，半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可指代具有併入至一共同封裝中之一或多個半導體裝置的一配置。一半導體封裝可包含部分或完全囊封至少一個半導體裝置之一外殼或殼體(casing)。一半導體裝置封裝亦可包含承載一或多個半導體裝置且附接至或以其他方式併入至殼體中之一中介基板(interposer substrate)。術語「半導體裝置總成」可指代一或多個半導體裝置、半導體裝置封裝及/或基板(例如，中介基板、支撐基板或其他適合基板)之一總成。可例如以離散封裝形式、條帶或矩陣形式及/或晶圓面板形式製造半導體裝置總成。如本文中使用，術語「垂直」、「橫向」、「上」及「下」可指代依據圖中所示之定向，半導體裝置或裝置總成中之構件之相對方向或位置。例如，「上」或「最上」可分別指代定位成比另一構件或相同構件之部分更靠近或最靠近一頁面之頂部的一構件。然而，此等術語應廣泛解釋為包含具有其他定向之半導體裝置，諸如倒轉或傾斜定向，其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換。
圖2係一半導體裝置總成200之一簡化示意圖，其包含耦合至一基板201之一半導體晶粒202。晶粒包含接觸墊(諸如接觸墊211及212)，其等各自連接至具有主動組件之一積體電路(示意性地繪示為一驅動器(DRV)電路)及具有被動組件之一積體電路(示意性地繪示為一靜電放電(ESD)保護電路)兩者。接觸墊211及212藉由接線230電耦合至基板接觸件221及222。如參考圖2可見，若半導體晶粒202已組態有適於為一單一驅動器電路提供ESD保護之一電容量，則將另一此半導體晶粒添加至總成200可非所要地增加基板接觸件221及222所「經受」之電容。
為處理這個問題，本技術之實施例可提供一種半導體晶粒，其中一主動電路及經組態以提供對其之ESD保護的被動電路經連接至分離接觸墊，使得不管經提供於一封裝總成中之晶粒的數目為何，皆可提供一所要電容量。例如，圖3係根據本技術之一實施例之一半導體裝置300之一簡化示意圖。半導體裝置300包含複數個接觸墊，諸如第一至第四接觸墊311至314，其等用於提供至半導體裝置300中之電路的連接性。例如，第一接觸墊311提供至具有主動組件之一第一電路371 (例如，一驅動器電路)的連接性，且第二接觸墊312提供至具有被動組件之一第二電路372 (例如，一ESD保護電路)的連接性。類似地，第三接觸墊313提供至具有主動組件之一第三電路373 (例如，一驅動器電路)的連接性，且第四接觸墊314提供至具有被動組件之一第四電路374 (例如，一ESD保護電路)的連接性。藉由為各被動電路提供一專用接觸墊，半導體裝置300利用多個相同半導體晶粒形成可能不同封裝密度，同時提供所要量之ESD保護，且無(例如)引起驅動器電路371及373消耗過量電力的過量電容。
參考圖4可更佳理解此點，圖4係根據本技術之一實施例之一半導體裝置總成400之一簡化示意圖。總成400包含一基板401及兩個半導體晶粒402及403 (例如，相同半導體晶粒)。與上文在圖3中繪示之半導體裝置300相同，各半導體晶粒402及403包含多個接觸墊，諸如第一至第四接觸墊411至414，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。因為各ESD保護電路具備一專用接觸墊，所以總成400可經組態具有對各驅動器電路之所要量之ESD保護。
如參考圖4可見，基板401包含兩個基板接觸件421及422。第一基板接觸件421 (例如，藉由接線430)經連接至總成400中之各半導體晶粒402及403之第一接觸墊411 (其對應於一驅動器電路)，但其係連接至總成400中之僅一個半導體晶粒402之第二接觸墊412 (其對應於一ESD保護電路)。類似地，第二基板接觸件422 (例如，藉由接線430)經連接至總成400中之各半導體晶粒402及403之第三接觸墊413 (其對應於一驅動器電路)，但其係連接至總成400中之僅一個半導體晶粒402之第四接觸墊414 (其對應於一ESD保護電路)。藉由使上半導體晶粒403上之第二接觸墊412及第四接觸墊414 (其等對應於ESD保護電路)與基板接觸件421及422電性斷開，各基板接觸件421及422所連接之電路的電容小於來自總成400中之各晶粒之ESD保護電路皆被連接時的電容。
儘管已將圖4描述且繪示為包含多個相同半導體晶粒，然在本技術之其他實施例中，可提供具有類似特徵之具不同晶粒類型的半導體裝置總成。例如，在一項實施例中，一半導體裝置總成可包含一邏輯晶粒及一記憶體晶粒，其等之一者或兩者可包含用於在封裝期間視需要連接被動電路之離散接觸墊。此外，儘管已將圖4描述且繪示為包含具有兩個驅動器電路之半導體晶粒，然熟習此項技術者將容易明白，此實施例僅為一項實例，且亦可提供具有不同數目之驅動器電路的半導體晶粒。此外，已將圖4描述且繪示為提供用於ESD保護電路的接觸墊與用於驅動器電路的接觸墊分離，在其他實施例中，可提供具有除驅動器之外之其他主動元件的電路，且同樣可提供僅包含被動組件(例如，電阻器、電容器、電感器等)的其他電路。
儘管已將圖4描述且繪示為在各基板接觸件421及422處具有用於提供至總成400中之半導體晶粒402之一者中之多個接觸墊之連接性的多個接線，然在本技術之其他實施例中，可使用其他接線配置。例如，圖5係根據本技術之一實施例之一半導體裝置總成500之一簡化示意圖。總成500包含一基板501及兩個半導體晶粒502及503，其等各自包含多個接觸墊(諸如第一至第四接觸墊511至514)以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。
如參考圖5可見，基板501包含兩個基板接觸件521及522。第一基板接觸件521藉由一接線530連接至第一半導體晶粒502之第一接觸墊511 (其對應於一驅動器電路)，第一半導體晶粒502之第一接觸墊511繼而藉由另一接線530連接至第二半導體晶粒503之第一接觸墊511 (其對應於一驅動器電路)。第一基板接觸件521進一步(例如，藉由第一半導體晶粒502之第一接觸墊511與第二接觸墊512之間之一接線)連接至總成500中之僅一個半導體晶粒502之第二接觸墊512 (其對應於一ESD保護電路)。類似地，第二基板接觸件522藉由一接線530連接至第一半導體晶粒502之第三接觸墊513 (其對應於一驅動器電路)，第一半導體晶粒502之第三接觸墊513繼而藉由另一接線530連接至第二半導體晶粒503之第三接觸墊513 (其對應於一驅動器電路)。第二基板接觸件522進一步(例如，藉由第一半導體晶粒502之第三接觸墊513與第四接觸墊514之間之一接線)連接至總成500中之僅一個半導體晶粒502之第四接觸墊514 (其對應於一ESD保護電路)。
其他接線配置係可行的(舉例而言，如圖6中繪示)，圖6係根據本技術之一實施例之一半導體裝置總成600之一簡化示意圖。總成600包含一基板601及兩個半導體晶粒602及603，其等各自包含多個接觸墊(諸如第一至第四接觸墊611至614)以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。
如參考圖6可見，基板601包含兩個基板接觸件621及622。第一基板接觸件621藉由一接線630直接連接至第一半導體晶粒602之第一接觸墊611 (其對應於一驅動器電路)，且藉由另一接線直接連接至第二半導體晶粒603之第一接觸墊611 (其對應於一驅動器電路)。第一基板接觸件621進一步(例如，藉由第一半導體晶粒602之第一接觸墊611與第二接觸墊612之間之一接線)連接至總成600中之僅一個半導體晶粒602之第二接觸墊612 (其對應於一ESD保護電路)。類似地，第二基板接觸件622藉由一接線630直接連接至第一半導體晶粒602之第三接觸墊613 (其對應於一驅動器電路)，且藉由另一接線直接連接至第二半導體晶粒603之第三接觸墊613 (其對應於一驅動器電路)。第二基板接觸件622進一步(例如，藉由第一半導體晶粒602之第三接觸墊613與第四接觸墊614之間之一接線)連接至總成600中之僅一個半導體晶粒602之第四接觸墊614 (其對應於一ESD保護電路)。
儘管在前述實例中，已將半導體晶粒描述且繪示為包含對應於各驅動器電路之一單一ESD保護電路，然在本技術之其他實施例中，可藉由包含具有對應於一半導體晶粒上之各驅動器電路之專用接觸墊的多個ESD保護電路而提供額外可組態性。例如，圖7係根據本技術之一實施例之一半導體裝置700之一簡化示意圖。半導體裝置700包含複數個接觸墊，諸如第一至第六接觸墊711至716，其等用於提供至半導體裝置700中之電路之連接性。例如，第一接觸墊711提供至具有主動組件之一第一電路771 (例如，一驅動器電路)之連接性，且第二接觸墊712及第三接觸墊713分別提供至僅包含被動組件之第二電路772及第三電路773 (例如，ESD保護電路)之連接性。類似地，第四接觸墊714提供至具有主動組件之一第四電路774 (例如，一驅動器電路)之連接性，且第五接觸墊715及第六接觸墊716分別提供至僅包含被動組件之第五電路775及第六電路776 (例如，ESD保護電路)之連接性。藉由為各主動電路提供各自具有其等自身之專用接觸墊的多個對應被動電路，半導體裝置700利用多個相同半導體晶粒形成可能不同封裝密度，同時提供所要量之ESD保護而無例如引起驅動器電路771及774消耗過量電力之過量電容。
參考圖8可更佳理解此，圖8係根據本技術之一實施例之一半導體裝置總成800之一簡化示意圖。總成800包含一基板801及兩個半導體晶粒802及803 (例如，相同半導體晶粒)。與上文在圖7中繪示之半導體裝置700相同，各半導體晶粒802及803包含多個接觸墊，諸如第一至第六接觸墊811至816，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。因為各ESD保護電路具備一專用接觸墊，所以總成800可經組態具有對各驅動器電路之所要量之ESD保護。
如參考圖8可見，基板801包含兩個基板接觸件821及822。第一基板接觸件821 (例如，藉由接線830)連接至總成800中之各半導體晶粒802及803之第一接觸墊811 (其對應於一驅動器電路)，且連接至總成800中之各半導體晶粒802及803之第二接觸墊812 (其對應於一ESD保護電路)，但其連接至總成800中之僅一個半導體晶粒802之第三接觸墊813 (其對應於另一ESD保護電路)。類似地，第二基板接觸件822 (例如，藉由接線830)連接至總成800中之各半導體晶粒802及803之第四接觸墊814 (其對應於一驅動器電路)，且連接至總成800中之各半導體晶粒802及803之第五接觸墊815 (其對應於一ESD保護電路)，但其連接至總成800中之僅一個半導體晶粒802之第六接觸墊816 (其對應於另一ESD保護電路)。藉由使上半導體晶粒803上之第三接觸墊813及第六接觸墊816 (其等對應於ESD保護電路)與基板接觸件821及822電性斷開，各基板接觸件821及822所連接之電路之電容小於來自總成800中之各晶粒之ESD保護電路皆被連接時之電容。
儘管在前述實施例中，已將半導體裝置總成繪示且描述為具有兩個半導體晶粒，然在本技術之其他實施例中，半導體裝置總成可包含不同數目之晶粒。例如，圖9係根據本技術之一實施例之包含四個半導體晶粒之一半導體裝置總成900之一簡化示意圖。總成900包含一基板901及四個半導體晶粒902至905 (例如，相同半導體晶粒)。與上文在圖3中繪示之半導體裝置300相同，各半導體晶粒902至905包含多個接觸墊，諸如第一至第四接觸墊911至914，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。因為各ESD保護電路具備一專用接觸墊，所以總成900可經組態具有對各驅動器電路之所要量之ESD保護。
如參考圖9可見，基板901包含兩個基板接觸件921及922。第一基板接觸件921 (例如，藉由接線930)連接至總成900中之各半導體晶粒902至905之第一接觸墊911 (其對應於一驅動器電路)，但其連接至總成900中之僅一個半導體晶粒902之第二接觸墊912 (其對應於一ESD保護電路)。類似地，第二基板接觸件922 (例如，藉由接線930)連接至總成900中之各半導體晶粒902至905之第三接觸墊913 (其對應於一驅動器電路)，但其連接至總成900中之僅一個半導體晶粒902之第四接觸墊914 (其對應於一ESD保護電路)。藉由使三個半導體晶粒903至905上之第二接觸墊912及第四接觸墊914 (其等對應於ESD保護電路)與基板接觸件921及922電性斷開，各基板接觸件921及922所連接之電路之電容小於來自總成900中之各晶粒之ESD保護電路皆被連接時之電容。
儘管在圖9中繪示之實施例中將總成中之僅一個晶粒之ESD保護電路連接至基板接觸件，然在其他實施例中，一半導體裝置總成可包含具有連接至其之(若干)基板接觸件之ESD保護電路的多個晶粒。例如，圖10係根據本技術之一實施例之一半導體裝置總成1000之一簡化示意圖。總成1000包含一基板1001及四個半導體晶粒1002至1005 (例如，相同半導體晶粒)，其等各自包含多個接觸墊(諸如第一至第四接觸墊1011至1014)以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。
如參考圖10可見，基板1001包含兩個基板接觸件1021及1022。第一基板接觸件1021 (例如，藉由接線1030)連接至總成1000中之各半導體晶粒1002至1005之第一接觸墊1011 (其對應於一驅動器電路)，但其連接至總成1000中之僅兩個半導體晶粒1002及1003之第二接觸墊1012 (其對應於一ESD保護電路)。類似地，第二基板接觸件1022 (例如，藉由接線1030)連接至總成1000中之各半導體晶粒1002至1005之第三接觸墊1013 (其對應於一驅動器電路)，但其連接至總成1000中之僅兩個半導體晶粒1002及1003之第四接觸墊1014 (其對應於一ESD保護電路)。藉由使兩個半導體晶粒1004至1005上之第二接觸墊1012及第四接觸墊1014 (其等對應於ESD保護電路)與基板接觸件1021及1022電性斷開，各基板接觸件1021及1022所連接之電路之電容小於來自總成1000中之各晶粒之ESD保護電路皆被連接時之電容。
儘管在前述實施例中，已繪示其中至少一個晶粒包含經附接ESD保護電路之半導體裝置總成，然在本技術之其他實施例中，半導體裝置總成可包含全部包含未連接之ESD保護電路之多個晶粒(例如，其依賴於多個驅動器電路之固有電容，使得不需要額外電容)。例如，圖11係根據本技術之一實施例之一半導體裝置總成1100之一簡化示意圖。總成1100包含一基板1101及四個半導體晶粒1102至1105 (例如，相同半導體晶粒)，其等各自包含多個接觸墊(諸如第一至第四接觸墊1111至1114)以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一电路(例如，一ESD保護電路)之連接性。
如參考圖11可見，基板1101包含兩個基板接觸件1121及1122。第一基板接觸件1121 (例如，藉由接線1130)經連接至總成1100中之各半導體晶粒1102至1105之第一接觸墊1111 (其對應於一驅動器電路)，但其未被連接至總成1100中之半導體晶粒1102至1105之任一者之第二接觸墊1112 (其等對應於一ESD保護電路)。類似地，第二基板接觸件1122 (例如，藉由接線1130)經連接至總成1100中之各半導體晶粒1102至1105之第三接觸墊1113 (其對應於一驅動器電路)，但其未被連接至總成1100中之半導體晶粒1102至1105之任一者之第四接觸墊1114 (其等對應於一ESD保護電路)。藉由使全部半導體晶粒1102至1105上之第二接觸墊1112及第四接觸墊1114 (其等對應於ESD保護電路)與基板接觸件1121及1122電性斷開，各基板接觸件1121及1122所連接之電路的電容小於來自總成1100中之晶粒之任一者之ESD保護電路被連接時的電容。
儘管在前述實施例中，將用於各經連接ESD保護電路之專用接觸墊繪示且描述為具有一對應專用接線，然在本技術之其他實施例中，可以其他方式來連接接觸墊。例如，圖12係根據本技術之一實施例之一半導體裝置總成1200之一簡化示意圖。總成1200包含一基板1201及兩個半導體晶粒1202及1203 (例如，相同半導體晶粒)。各半導體晶粒1202及1203包含多個接觸墊，諸如第一至第四接觸墊1211至1214，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)的連接性。第二接觸墊1212及第四接觸墊1214分別被安置成緊鄰對應第一接觸墊1211及第三接觸墊1213，使得可使用一單一接線1230來連接兩個墊。
如參考圖12可見，基板1201包含兩個基板接觸件1221及1222。第一基板接觸件1221係藉由一單一接線1230 (例如，運用一焊鍵(solder bond) 1241)連接至第一半導體晶粒1202之第一接觸墊1211 (其對應於一驅動器電路)及第二接觸墊1212 (其對應於一ESD保護電路)兩者。第一基板接觸件1221進一步係藉由一接線1230連接於連接第一半導體晶粒1202之第一接觸墊1211及第二接觸墊1212的焊鍵1241與第二半導體晶粒1203的第一接觸墊1211 (其對應於一驅動器電路)之間。類似地，第二基板接觸件1222係藉由一單一接線1230 (例如，運用一焊鍵1241)連接至第一半導體晶粒1202之第三接觸墊1213 (其對應於一驅動器電路)及第四接觸墊1214 (其對應於一ESD保護電路)兩者。第二基板接觸件1222進一步係藉由一接線1230連接於連接第一半導體晶粒1202之第三接觸墊1213及第四接觸墊1214的焊鍵1241與第二半導體晶粒1203的第三接觸墊1213 (其對應於一驅動器電路)之間。
運用一單一接線連接至多個接觸墊之前述方法可擴展至其中針對各驅動器電路提供一個以上ESD保護電路之本技術之實施例。例如，圖13係根據本技術之一實施例之一半導體裝置總成1300之一簡化示意圖。總成1300包含一基板1301及兩個半導體晶粒1302及1303 (例如，相同半導體晶粒)。各半導體晶粒1302及1303包含多個接觸墊，諸如第一至第六接觸墊1311至1316，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。第二接觸墊1312及第三接觸墊1313安置成緊鄰對應第一接觸墊1311，使得可使用一單一接線1330將第一接觸墊1311連接至第二接觸墊1312及第三接觸墊1313之一者或兩者(或兩者皆不)。類似地，第五接觸墊1315及第六接觸墊1316安置成緊鄰對應第四接觸墊1314，使得可使用一單一接線1330將第四接觸墊1314連接至第五接觸墊1315及第六接觸墊1316之一者或兩者(或兩者皆不)。
如參考圖13可見，基板1301包含兩個基板接觸件1321及1322。第一基板接觸件1321藉由一單一接線1330 (例如，運用一第一焊鍵1341)連接至第一半導體晶粒1302之第一、第二及第三接觸墊1311至1313。第一基板接觸件1321進一步藉由一接線1330連接於第一焊鍵1341與跨越第二半導體晶粒1303之第一接觸墊1311及第三接觸墊1313的一第二焊鍵1342之間。類似地，第二基板接觸件1322藉由一單一接線1330 (例如，運用一第一焊鍵1341)連接至第一半導體晶粒1302之第四、第五及第六接觸墊1314至1316。第二基板接觸件1322進一步藉由一接線1330連接於第一焊鍵1341與跨越第二半導體晶粒1303之第四接觸墊1314及第六接觸墊1316的一第二焊鍵1342之間。
運用一單一接線連接至多個接觸墊之前述方法可擴展至其中可視情況藉由一單一接線連接一晶粒上之多個電路的本技術之實施例。例如，圖14係根據本技術之一實施例之一半導體裝置總成1400之一簡化示意圖。總成1400包含一基板1401及兩個半導體晶粒1402及1403 (例如，相同半導體晶粒)。各半導體晶粒1402及1403包含多個接觸墊，諸如第一至第六接觸墊1411至1416，其等各自提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接性。以上文在圖13中繪示之一方式，將第二接觸墊1412及第三接觸墊1413安置成緊鄰對應第一接觸墊1411，使得可使用一單一接線1430將第一接觸墊1411連接至第二接觸墊1412及第三接觸墊1413之一者或兩者(或兩者皆不)。類似地，將第五接觸墊1415及第六接觸墊1416安置成緊鄰對應第四接觸墊1414，使得可使用一單一接線1430將第四接觸墊1414連接至第五接觸墊1415及第六接觸墊1416之一者或兩者(或兩者皆不)。然而，與圖13中不同，第三接觸墊1413及第六接觸墊1416未連接至一額外ESD保護電路，而是連接至一第二驅動器電路。
如參考圖14可見，基板1401包含兩個基板接觸件1421及1422。第一基板接觸件1421藉由一單一接線1430 (例如，運用一第一焊鍵1441)連接至第一半導體晶粒1402之第一、第二及第三接觸墊1411至1413。第一基板接觸件1421進一步藉由一接線1430連接於第一焊鍵1441與跨越第二半導體晶粒1403之第一接觸墊1411及第三接觸墊1413的一第二焊鍵1442之間。類似地，第二基板接觸件1422藉由一單一接線1430 (例如，運用一第一焊鍵1441)連接至第一半導體晶粒1402之第四、第五及第六接觸墊1414至1416。第二基板接觸件1422進一步藉由一接線1430連接於第一焊鍵1441與跨越第二半導體晶粒1403之第四接觸墊1414及第六接觸墊1416的一第二焊鍵1442之間。
以一類似方式，本技術之其他實施例可提供具有用於視情況連接任何數目之不同電路的緊密間隔之接合墊、除ESD保護電路及驅動器電路之外亦具有其他所要功能或具有代替ESD保護電路及驅動器電路之任何所要功能的半導體晶粒。此外，可以若干方式之任一者提供緊密間隔之接合墊，諸如上文在圖12至圖14之實例中繪示之接合墊。例如，圖15繪示根據本技術之一實施例之一半導體裝置之一簡化部分橫截面視圖。在圖15中繪示之半導體裝置1501中，緊密間隔之接合墊1502及1503提供於一鈍化或聚醯亞胺材料層1505下方，且因此由一小的鈍化或聚醯亞胺材料區1506分離。可提供足夠體積之一焊料球1504以橋接此鈍化或聚醯亞胺材料區1506，且因此連接緊密間隔之接合墊1502及1503。
藉由進一步實例，圖16繪示根據本技術之一實施例之另一半導體裝置之一簡化部分橫截面視圖。在圖16中繪示之半導體裝置1601中，緊密間隔之接合墊1602及1603提供於一鈍化或聚醯亞胺材料層1605下方，但已進行額外製程步驟以從緊密間隔之接合墊1602與1603之間消除鈍化或聚醯亞胺材料1605 (例如，藉由在緊密間隔之接合墊1602與1603之間之區下方包含一蝕刻停止材料1606而允許從其等之間蝕除鈍化或聚醯亞胺材料1605)。此配置有利於容易將一焊料球1604連接至緊密間隔之接合墊1602及1603兩者(歸因於其等之間不存在不可濕潤材料)。
在另一實例中，圖17繪示根據本技術之一實施例之另一半導體裝置之一簡化部分橫截面視圖。在圖17中繪示之半導體裝置1701中，緊密間隔之接合墊1702及1703提供於一鈍化或聚醯亞胺材料層1705上方(例如，在一重佈層中)。此配置亦有利於容易將一焊料球1704連接至緊密間隔之接合墊1702及1703兩者(歸因於其等之間不存在不可濕潤材料)。
儘管在前述實例中，已繪示其中將具有被動元件之電路(例如，ESD保護電路)繪示且描述為具有用於經由接線提供連接性之專用接觸墊的半導體裝置封裝，然熟習此項技術者將容易瞭解，亦可使用晶粒至晶粒或晶粒至基板連接之其他方法來提供封裝階段連接可組態性。例如，其中被動組件之電路具有專用TSV之半導體晶粒可以非疊瓦式堆疊配置，其中藉由包含或省略堆疊中之鄰近TSV之間的焊料接頭而提供選用連接性。同樣可提供其他互連技術。
此外，儘管在前述實例中，已將半導體裝置總成描述為包含一單一半導體晶粒堆疊，然在本技術之其他實施例中，一半導體裝置總成可包含其中可視情況經由專用接觸墊連接被動電路之多個半導體晶粒堆疊。例如，在本技術之一項實施例中，一半導體裝置總成可包含多個橫向分離之半導體晶粒堆疊(例如，各自四個晶粒之兩個堆疊、各自八個晶粒之兩個堆疊、各自四個晶粒之四個堆疊等)，其中各堆疊中少於全部之可存取ESD電路電耦合至一主動電路。在另一實施例中，一半導體裝置總成可包含一單一半導體晶粒堆疊，其中堆疊中之晶粒之子組分開連接至基板(例如，具有八個晶粒之一疊瓦式堆疊群組為電耦合至基板之一第一子組，其中第一子組中少於全部之可用晶粒具有電耦合之ESD電路，且前八個晶粒上方之另外八個晶粒(其具有與第一子組之方向相反之一疊瓦偏移方向)群組為與第一子組分開電耦合至基板之一第二子組，其中第二子組中少於全部之可用晶粒具有電耦合之ESD電路等)。
上文關於圖3至圖17描述之半導體裝置總成之任一者可併入至無數較大及/或更複雜系統之任一者中，該等系統之一代表實例係圖18中示意性地展示之系統1800。系統1800可包含一半導體裝置總成1802、一電源1804、一驅動器1806、一處理器1808及/或其他子系統或組件1810。半導體裝置總成1802可包含大體上類似於上文關於圖3至圖15描述之半導體裝置之構件的構件。所得系統1800可執行多種功能之任一者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表系統1800可包含(不限於)手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、車輛、電器及其他產品。系統1800之組件可容置於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。系統1800之組件亦可包含遠端裝置及多種電腦可讀媒體之任一者。
圖19係繪示製造一半導體裝置總成之一方法之一流程圖。該方法包含：提供包含一基板接觸件之一基板(方塊1910)，且將一或多個半導體晶粒耦合至基板(方塊1920)。一或多個半導體晶粒之各者包含：一第一接觸墊，其電耦合至半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件。該方法進一步包含：將全部一或多個半導體晶粒之該等第一接觸墊電耦合至基板接觸件(方塊1930)，且將一或多個半導體晶粒之至少一者之該等第二接觸墊電耦合至基板接觸件(方塊1940)。
從前文將明白，本文中已出於繪示之目的在描述本發明之特定實施例，但可在不脫離本發明之範疇之情況下進行各種修改。因此，本發明除如藉由隨附發明申請專利範圍限制外並不受限。
100‧‧‧半導體裝置總成
101‧‧‧基板
102‧‧‧半導體晶粒
103‧‧‧半導體晶粒
121‧‧‧基板接觸件
122‧‧‧接觸墊
123‧‧‧接觸墊
131‧‧‧接線
132‧‧‧接線
151‧‧‧焊料球
152‧‧‧通路
162‧‧‧電路
163‧‧‧電路
170‧‧‧囊封劑
200‧‧‧半導體裝置總成
201‧‧‧基板
202‧‧‧半導體晶粒
211‧‧‧接觸墊
212‧‧‧接觸墊
221‧‧‧基板接觸件
222‧‧‧基板接觸件
230‧‧‧接線
300‧‧‧半導體裝置
311‧‧‧第一接觸墊
312‧‧‧第二接觸墊
313‧‧‧第三接觸墊
314‧‧‧第四接觸墊
371‧‧‧第一電路/驅動器電路
372‧‧‧第二電路
373‧‧‧第三電路/驅動器電路
374‧‧‧第四電路
400‧‧‧半導體裝置總成
401‧‧‧基板
402‧‧‧半導體晶粒
403‧‧‧半導體晶粒
411‧‧‧第一接觸墊
412‧‧‧第二接觸墊
413‧‧‧第三接觸墊
414‧‧‧第四接觸墊
421‧‧‧第一基板接觸件
422‧‧‧第二基板接觸件
430‧‧‧接線
500‧‧‧半導體裝置總成
501‧‧‧基板
502‧‧‧第一半導體晶粒
503‧‧‧第二半導體晶粒
511‧‧‧第一接觸墊
512‧‧‧第二接觸墊
513‧‧‧第三接觸墊
514‧‧‧第四接觸墊
521‧‧‧第一基板接觸件
522‧‧‧第二基板接觸件
530‧‧‧接線
600‧‧‧半導體裝置總成
601‧‧‧基板
602‧‧‧第一半導體晶粒
603‧‧‧第二半導體晶粒
611‧‧‧第一接觸墊
612‧‧‧第二接觸墊
613‧‧‧第三接觸墊
614‧‧‧第四接觸墊
621‧‧‧第一基板接觸件
622‧‧‧第二基板接觸件
630‧‧‧接線
700‧‧‧半導體裝置
711‧‧‧第一接觸墊
712‧‧‧第二接觸墊
713‧‧‧第三接觸墊
714‧‧‧第四接觸墊
715‧‧‧第五接觸墊
716‧‧‧第六接觸墊
771‧‧‧第一電路/驅動器電路
772‧‧‧第二電路
773‧‧‧第三電路
774‧‧‧第四電路/驅動器電路
775‧‧‧第五電路
776‧‧‧第六電路
800‧‧‧半導體裝置總成
801‧‧‧基板
802‧‧‧半導體晶粒
803‧‧‧半導體晶粒
811‧‧‧第一接觸墊
812‧‧‧第二接觸墊
813‧‧‧第三接觸墊
814‧‧‧第四接觸墊
815‧‧‧第五接觸墊
816‧‧‧第六接觸墊
821‧‧‧第一基板接觸件
822‧‧‧第二基板接觸件
830‧‧‧接線
900‧‧‧半導體裝置總成
901‧‧‧基板
902‧‧‧半導體晶粒
903‧‧‧半導體晶粒
904‧‧‧半導體晶粒
905‧‧‧半導體晶粒
911‧‧‧第一接觸墊
912‧‧‧第二接觸墊
913‧‧‧第三接觸墊
914‧‧‧第四接觸墊
921‧‧‧第一基板接觸件
922‧‧‧第二基板接觸件
930‧‧‧接線
1000‧‧‧半導體裝置總成
1001‧‧‧基板
1002‧‧‧半導體晶粒
1003‧‧‧半導體晶粒
1004‧‧‧半導體晶粒
1005‧‧‧半導體晶粒
1011‧‧‧第一接觸墊
1012‧‧‧第二接觸墊
1013‧‧‧第二接觸墊
1014‧‧‧第四接觸墊
1021‧‧‧第一基板接觸件
1022‧‧‧第二基板接觸件
1030‧‧‧接線
1100‧‧‧半導體裝置總成
1101‧‧‧基板
1102‧‧‧半導體晶粒
1103‧‧‧半導體晶粒
1104‧‧‧半導體晶粒
1105‧‧‧半導體晶粒
1111‧‧‧第一接觸墊
1112‧‧‧第二接觸墊
1113‧‧‧第三接觸墊
1114‧‧‧第四接觸墊
1121‧‧‧第一基板接觸件
1122‧‧‧第二基板接觸件
1130‧‧‧接線
1200‧‧‧半導體裝置總成
1201‧‧‧基板
1202‧‧‧第一半導體晶粒
1203‧‧‧第二半導體晶粒
1211‧‧‧第一接觸墊
1212‧‧‧第二接觸墊
1213‧‧‧第三接觸墊
1214‧‧‧第四接觸墊
1221‧‧‧第一基板接觸件
1222‧‧‧第二基板接觸件
1230‧‧‧接線
1241‧‧‧焊鍵
1300‧‧‧半導體裝置總成
1301‧‧‧基板
1302‧‧‧第一半導體晶粒
1303‧‧‧第二半導體晶粒
1311‧‧‧第一接觸墊
1312‧‧‧第二接觸墊
1313‧‧‧第三接觸墊
1314‧‧‧第四接觸墊
1315‧‧‧第五接觸墊
1316‧‧‧第六接觸墊
1321‧‧‧第一基板接觸件
1322‧‧‧第二基板接觸件
1330‧‧‧接線
1341‧‧‧第一焊鍵
1342‧‧‧第二焊鍵
1400‧‧‧半導體裝置總成
1401‧‧‧基板
1402‧‧‧第一半導體晶粒
1403‧‧‧第二半導體晶粒
1411‧‧‧第一接觸墊
1412‧‧‧第二接觸墊
1413‧‧‧第三接觸墊
1414‧‧‧第四接觸墊
1415‧‧‧第五接觸墊
1416‧‧‧第六接觸墊
1421‧‧‧第一基板接觸件
1422‧‧‧第二基板接觸件
1430‧‧‧接線
1441‧‧‧第一焊鍵
1442‧‧‧第二焊鍵
1501‧‧‧半導體裝置
1502‧‧‧接合墊
1503‧‧‧接合墊
1504‧‧‧焊料球
1505‧‧‧鈍化或聚醯亞胺材料層
1506‧‧‧鈍化或聚醯亞胺材料區
1601‧‧‧半導體裝置
1602‧‧‧接合墊
1603‧‧‧接合墊
1604‧‧‧焊料球
1605‧‧‧鈍化或聚醯亞胺材料
1606‧‧‧蝕刻停止材料
1701‧‧‧半導體裝置
1702‧‧‧接合墊
1703‧‧‧接合墊
1704‧‧‧焊料球
1705‧‧‧鈍化或聚醯亞胺材料
1800‧‧‧系統
1802‧‧‧半導體裝置總成
1804‧‧‧電源
1806‧‧‧驅動器
1808‧‧‧處理器
1810‧‧‧其他子系統或組件
1910‧‧‧方塊
1920‧‧‧方塊
1930‧‧‧方塊
1940‧‧‧方塊
圖1係一半導體裝置總成之一簡化部分橫截面視圖，其包含堆疊於一基板上之多個半導體晶粒。
圖2係一半導體裝置總成之一簡化示意圖。
圖3係根據本技術之一實施例之一半導體裝置之一簡化示意圖。
圖4至圖6係根據本技術之實施例之半導體裝置總成之簡化示意圖。
圖7係根據本技術之一實施例之一半導體裝置之一簡化示意圖。
圖8至圖14係根據本技術之實施例之半導體裝置總成之簡化示意圖。
圖15至圖17係根據本技術之實施例之半導體裝置之簡化部分橫截面視圖。
圖18係展示包含根據本技術之一實施例組態之一半導體裝置總成的一系統之一示意圖。
圖19係繪示根據本技術之一實施例之製造一半導體裝置之一方法之一流程圖。

Claims (21)

  1. 一種半導體裝置總成，其包括： 一基板； 一晶粒，其經耦合至該基板，該晶粒包含： 一第一接觸墊，其經電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件，及 一第二接觸墊，其經電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件； 其中該基板包含經電耦合至該晶粒上之該第一接觸墊及該第二接觸墊兩者之一基板接觸件。
  2. 如請求項1之半導體裝置總成，其中該晶粒係一第一晶粒，其進一步包括： 一第二晶粒，其包含： 一第三接觸墊，其經電耦合至該第二晶粒上之一第三電路，該第三電路包含至少一第二主動電路元件，及 一第四接觸墊，其經電耦合至該第二晶粒上之一第四電路，該第四電路僅包含被動電路元件； 其中該基板接觸件經電耦合至該第二晶粒上之該第三接觸墊，及 其中該第二晶粒上之該第四接觸墊係與該基板接觸件電性斷開。
  3. 如請求項2之半導體裝置總成，其中該第一晶粒及該第二晶粒係相同晶粒，其中該第一晶粒上之該第一接觸墊對應於該第二晶粒上之該第三接觸墊，且該第一晶粒上之該第二接觸墊對應於該第二晶粒上之該第四接觸墊。
  4. 如請求項2之半導體裝置總成，其中該第一晶粒及該第二晶粒係以一疊瓦式組態堆疊。
  5. 如請求項2之半導體裝置總成，其中該第一晶粒進一步包含一第五接觸墊，該第五接觸墊經電耦合至該第一晶粒上之一第五電路，該第五電路僅包含被動電路元件，且其中該基板接觸件經電耦合至該第一晶粒上之該第五接觸墊。
  6. 如請求項1之半導體裝置總成，其中該第一電路係一驅動器電路。
  7. 如請求項1之半導體裝置總成，其中該第二電路包含用於提供靜電放電(ESD)保護之一或多個電容器。
  8. 如請求項1之半導體裝置總成，其中該基板接觸件係藉由一或多個接線電耦合至該第一接觸墊及該第二接觸墊。
  9. 如請求項1之半導體裝置總成，其中該基板接觸件係藉由該第一接觸墊與該第三接觸墊之間之一接線電耦合至該第三接觸墊。
  10. 如請求項1之半導體裝置總成，其中晶粒係一NAND記憶體晶粒。
  11. 一種半導體裝置總成，其包括： 一基板，其包含一基板接觸件；及 複數個半導體晶粒，其等各自包含： 一第一接觸墊，其經電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件，及 一第二接觸墊，其經電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件； 其中全部該複數個半導體晶粒之該等第一接觸墊經電耦合至該基板接觸件，及 其中一些但少於全部之該複數個半導體晶粒之該等第二接觸墊經電耦合至該基板接觸件。
  12. 如請求項11之半導體裝置總成，其中該複數個半導體晶粒之各者之該第一電路係一驅動器電路。
  13. 如請求項11之半導體裝置總成，其中該複數個半導體晶粒之各者之該第二電路包含用於提供靜電放電(ESD)保護之一或多個電容器。
  14. 如請求項11之半導體裝置總成，其中該複數個半導體晶粒係相同半導體晶粒。
  15. 如請求項11之半導體裝置總成，其中該複數個半導體晶粒包括NAND記憶體晶粒。
  16. 如請求項11之半導體裝置總成，其中該複數個半導體晶粒包括兩個以上半導體晶粒。
  17. 一種製造一半導體裝置總成之方法，其包括： 提供包含一基板接觸件之一基板； 將一或多個半導體晶粒耦合至該基板，其中該一或多個半導體晶粒之各者包含： 一第一接觸墊，其經電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件，及 一第二接觸墊，其經電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件； 將全部該一或多個半導體晶粒之該等第一接觸墊電耦合至該基板接觸件；及 將該一或多個半導體晶粒之至少一者之該等第二接觸墊電耦合至該基板接觸件。
  18. 如請求項17之方法，其中該一或多個半導體晶粒包括複數個半導體晶粒，且其中將該一或多個半導體晶粒之至少一者之該等第二接觸墊電耦合至該基板接觸件包括：將一些但少於全部之該複數個半導體晶粒之該等第二接觸墊電耦合至該基板接觸件。
  19. 如請求項18之方法，其中該複數個半導體晶粒係相同半導體晶粒。
  20. 如請求項17之方法，其中該一或多個半導體晶粒之各者之該第一電路係一驅動器電路。
  21. 如請求項17之方法，其中該一或多個半導體晶粒之各者之該第二電路包含用於提供靜電放電(ESD)保護之一或多個電容器。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756093B (zh) * 2021-03-31 2022-02-21 新唐科技股份有限公司 記憶體

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10483241B1 (en) 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability
US10867991B2 (en) * 2018-12-27 2020-12-15 Micron Technology, Inc. Semiconductor devices with package-level configurability
US11908812B2 (en) * 2020-12-17 2024-02-20 Micron Technology, Inc. Multi-die memory device with peak current reduction
US11695003B2 (en) 2021-08-06 2023-07-04 Nanya Technology Corporation Semiconductor device, electronic system, and electrostatic discharge protection method for semiconductor device thereof

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW289153B (zh) 1994-09-26 1996-10-21 Ibm
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5982018A (en) 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
JP3720999B2 (ja) 1999-02-18 2005-11-30 沖電気工業株式会社 入力保護回路
US6459343B1 (en) 1999-02-25 2002-10-01 Formfactor, Inc. Integrated circuit interconnect system forming a multi-pole filter
US6448865B1 (en) 1999-02-25 2002-09-10 Formfactor, Inc. Integrated circuit interconnect system
US6784558B2 (en) * 1999-12-30 2004-08-31 Intel Corporation Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads
WO2001063672A2 (en) * 2000-02-22 2001-08-30 Formfactor, Inc. Integrated circuit interconnect system having matched impedance and capacitance
SG97938A1 (en) 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
TW531867B (en) 2000-10-13 2003-05-11 Texas Instruments Inc Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface
TW502459B (en) 2001-01-03 2002-09-11 Taiwan Semiconductor Mfg Diode structure with high electrostatic discharge protection and electrostatic discharge protection circuit design of the diode
TW475250B (en) 2001-03-14 2002-02-01 Taiwan Semiconductor Mfg ESD protection circuit to be used in high-frequency input/output port with low capacitance load
US6803633B2 (en) 2001-03-16 2004-10-12 Sarnoff Corporation Electrostatic discharge protection structures having high holding current for latch-up immunity
JP3792635B2 (ja) 2001-12-14 2006-07-05 富士通株式会社 電子装置
JP3966747B2 (ja) 2002-03-13 2007-08-29 ローム株式会社 半導体集積回路装置
TW548823B (en) 2002-07-25 2003-08-21 Winbond Electronics Corp ESD protection device coupled between a first high power line and a second high power line
JP5008840B2 (ja) 2004-07-02 2012-08-22 ローム株式会社 半導体装置
US7737553B2 (en) * 2004-10-06 2010-06-15 Panasonic Corporation Semiconductor device
JP2006135302A (ja) 2004-10-06 2006-05-25 Matsushita Electric Ind Co Ltd 半導体装置
CN1905177B (zh) 2005-07-29 2010-10-20 米辑电子股份有限公司 线路组件结构及其制作方法
US7649214B2 (en) 2005-10-17 2010-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection system for multiple-domain integrated circuits
US7679198B2 (en) * 2007-05-04 2010-03-16 Micron Technology, Inc. Circuit and method for interconnecting stacked integrated circuit dies
US8367471B2 (en) 2007-06-15 2013-02-05 Micron Technology, Inc. Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US8154134B2 (en) * 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP2009295750A (ja) 2008-06-04 2009-12-17 Toshiba Corp 半導体装置
KR100997787B1 (ko) 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US8338044B2 (en) * 2009-01-15 2012-12-25 Ford Motor Company System and method for detecting a fuel cell anode gas composition
JP5503208B2 (ja) 2009-07-24 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
US8232137B2 (en) 2009-12-10 2012-07-31 Intersil Americas Inc. Heat conduction for chip stacks and 3-D circuits
KR20120017564A (ko) 2010-08-19 2012-02-29 주식회사 하이닉스반도체 메모리 카드 및 그 제조방법
KR20120088013A (ko) 2010-09-20 2012-08-08 삼성전자주식회사 디커플링 반도체 커패시터를 포함하는 반도체 패키지
US8399961B2 (en) 2010-12-21 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps
JP2013004644A (ja) 2011-06-15 2013-01-07 Elpida Memory Inc 半導体装置
KR20130004783A (ko) 2011-07-04 2013-01-14 삼성전자주식회사 정전기 방전 보호회로를 포함하는 적층 반도체 장치 및 적층 반도체 장치의 제조 방법
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130228867A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device protected from electrostatic discharge
US9030010B2 (en) 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
JP6215645B2 (ja) 2012-11-28 2017-10-18 ルネサスエレクトロニクス株式会社 半導体集積回路
US8906743B2 (en) 2013-01-11 2014-12-09 Micron Technology, Inc. Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods
EP2838114A3 (en) * 2013-08-12 2015-04-08 Xintec Inc. Chip package
US9355892B2 (en) * 2013-09-09 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with active and passive devices in different tiers
US10103128B2 (en) * 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US9111846B1 (en) 2014-04-16 2015-08-18 Gloval Unichip Corp. Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
US9502369B2 (en) * 2015-02-04 2016-11-22 Micron Technology, Inc. Semiconductor devices and packages
US9922970B2 (en) 2015-02-13 2018-03-20 Qualcomm Incorporated Interposer having stacked devices
GB2536034B (en) * 2015-03-05 2018-09-26 Jaguar Land Rover Ltd A noise-reducing device for a vehicle
US20170025402A1 (en) * 2015-03-06 2017-01-26 Texas Instruments Incorporated Semiconductor esd protection circuit
US9587369B2 (en) * 2015-07-02 2017-03-07 Caterpillar Inc. Excavation system having adaptive dig control
US9786632B2 (en) * 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
JP6531603B2 (ja) 2015-10-01 2019-06-19 富士通株式会社 電子部品、電子装置及び電子装置の製造方法
US9711500B1 (en) 2016-02-16 2017-07-18 Darryl G. Walker Package including a plurality of stacked semiconductor devices having area efficient ESD protection
US11373974B2 (en) * 2016-07-01 2022-06-28 Intel Corporation Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size
US10250250B2 (en) * 2016-09-12 2019-04-02 Analog Devices, Inc. Bootstrapped switching circuit
US10756720B2 (en) * 2016-10-17 2020-08-25 Infineon Technologies Ag Driver circuit for electronic switch
CN108695284A (zh) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
US10319690B2 (en) 2017-04-28 2019-06-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10236263B1 (en) 2017-08-24 2019-03-19 Globalfoundries Inc. Methods and structures for mitigating ESD during wafer bonding
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10483241B1 (en) 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability
US10867991B2 (en) 2018-12-27 2020-12-15 Micron Technology, Inc. Semiconductor devices with package-level configurability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756093B (zh) * 2021-03-31 2022-02-21 新唐科技股份有限公司 記憶體

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