JP5503208B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5503208B2 JP5503208B2 JP2009173356A JP2009173356A JP5503208B2 JP 5503208 B2 JP5503208 B2 JP 5503208B2 JP 2009173356 A JP2009173356 A JP 2009173356A JP 2009173356 A JP2009173356 A JP 2009173356A JP 5503208 B2 JP5503208 B2 JP 5503208B2
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- bump electrode
- semiconductor chip
- bump electrodes
- long side
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Description
LCDドライバでは、上述の通り半導体チップの小型化が進められており、特に半導体チップの短辺方向を縮小化することが検討されている。
前記実施の形態1では、例えば、図4に示すように、複数の入力用バンプ電極IBMPのうち一部の入力用バンプ電極IBMPの下層には入力保護回路3a〜3cが配置されている一方、複数の入力用バンプ電極IBMPのうち他の一部の入力用バンプ電極IBMPの下層には入力保護回路3a〜3cが配置されずにSRAM2a〜2c(内部回路)が配置されている構成について説明した。
前記実施の形態1では、図4に示すように、入力保護回路3a〜3cをSRAM2a〜2cや制御部1を長辺方向に並べたときに生じるスペースに配置するという第1特徴点により、LCDドライバを構成する半導体チップCHP2の短辺方向の長さを縮小化している。したがって、前記実施の形態1では、入力用バンプ電極IBMPと平面的に重ならない領域に入力保護回路3a〜3cが形成されていることになる。このため、前記実施の形態1では、入力用バンプ電極IBMPと入力保護回路3a〜3cを接続するために、半導体チップCHP2の平面方向に延在する引き回し配線を使用する必要がある。この場合、引き回し配線のレイアウト構成を工夫しないと、半導体チップCHP2の配線レイアウトが複雑になってしまう。
本実施の形態4では、入力用バンプ電極の形状と、出力用バンプ電極の形状とを同じ形状にするのではなく、大きさの異なる形状にする例について説明する。
本実施の形態5では、入力用バンプ電極の下層に形成されているデバイス構造について説明する。図13は、1つの入力用バンプ電極IBMP1を示す図である。図13において、半導体チップCHP2の長辺LS1の延在する方向をX方向とし、半導体チップCHP2の短辺方向をY方向としている。図13に示すように、入力用バンプ電極IBMP1は、長方形形状をしており、この入力用バンプ電極IBMP1の下層に3本の最上層配線
TM1〜TM3が配置されている。入力用バンプ電極IBMP1は、開口部CNT1に埋め込まれた導電材料を介して、最上層配線TM1と電気的に接続されている。このように構成されている入力用バンプ電極IBMP1の下層に形成されているデバイス構造について図14を参照しながら説明する。
本実施の形態6では、LCDドライバを構成する半導体チップCHP2を実装基板(ガラス基板)に実装する工程について説明する。まず、通常の半導体製造技術を使用することにより、半導体基板にMISFETなどの半導体素子を形成し、その後、半導体素子を形成した半導体基板上に多層配線を形成する。そして、多層配線の最上層に形成される最上層配線を形成した後、この最上層配線上を覆う表面保護膜を形成する。その後、表面保護膜に最上層配線に達する開口部を形成し、この開口部を埋め込むとともに表面保護膜上にバンプ電極(入力用バンプ電極および出力用バンプ電極)を形成する。その後、半導体基板をダイシングすることにより、図4に示すような個片化した半導体チップCHP2を得ることができる。
本実施の形態7では、出力用バンプ電極、最上層配線および出力保護回路の平面レイアウトについて説明する。図22は、図4で示したLCDドライバを構成する半導体チップCHP2の長辺LS2の近傍領域を拡大して示す図である。
本実施の形態8では、入力用バンプ電極IBMP1、IBMP2と平面的に重なる領域に、半導体素子が形成されないダミー領域を配置した場合を例示する。図23は、図13のA−A線で切断した断面図であり、本実施の形態8を例示する断面図である。
1S 半導体基板
2a SRAM
2b SRAM
2c SRAM
3 入力保護回路
3a 入力保護回路
3b 入力保護回路
3c 入力保護回路
3A 入力保護回路
3B 入力保護回路
4 出力保護回路
10 ガラス基板
10a 電極
11 ガラス基板
12 絶縁層
13 金属粒子
14 表示部
15 液晶表示装置
A 端子
ACF 異方性導電フィルム
a 長さ
b 長さ
C カメラ
CHP1 半導体チップ
CHP2 半導体チップ
CIL コンタクト層間絶縁膜
CNT1 開口部
CNT1a 開口部
CNT1b 開口部
CNT2 開口部
CNT2a 開口部
CNT2b 開口部
CNT3 開口部
CNT3a 開口部
CNT3b 開口部
CNT4a 開口部
CNT4b 開口部
CNT5 開口部
CNT6 開口部
CNT7 開口部
CS コバルトシリサイド膜
D1 ダイオード
D2 ダイオード
DP ダミーパターン
EX1 浅いn型不純物拡散領域
EX2 浅いp型不純物拡散領域
FPC フレキシブルプリント基板
G1 ゲート電極
G2 ゲート電極
GOX ゲート絶縁膜
IBMP 入力用バンプ電極
IBMP1 入力用バンプ電極
IBMP2 入力用バンプ電極
IBMP3 入力用バンプ電極
IBMP4 入力用バンプ電極
IBMP5 入力用バンプ電極
IL1 層間絶縁膜
IL2 層間絶縁膜
IL3 層間絶縁膜
IL4 層間絶縁膜
IL5 層間絶縁膜
IU 内部回路
L1 第1層配線
L2 第2層配線
L3 第3層配線
L4 第4層配線
LS1 長辺
LS2 長辺
NR 深いn型不純物拡散領域
NWL n型ウェル
OBMP 出力用バンプ電極
OBMP1 出力用バンプ電極
OBMP2 出力用バンプ電極
PF ポリシリコン膜
PLG1 プラグ
PLG2 プラグ
PLG3 プラグ
PLG4 プラグ
PLG5 プラグ
PR 深いp型不純物拡散領域
PWL p型ウェル
Q1 nチャネル型MISFET
Q2 pチャネル型MISFET
SS1 短辺
SS2 短辺
STI 素子分離領域
SW サイドウォール
TM1 最上層配線
TM1a 最上層配線
TM1b 最上層配線
TM2 最上層配線
TM2a 最上層配線
TM2b 最上層配線
TM3 最上層配線
TM3a 最上層配線
TM3b 最上層配線
TM4 最上層配線
TM5 最上層配線
TM6 最上層配線
TM7 最上層配線(Vss)
TM8 最上層配線(Vcc)
Tr1 nチャネル型MISFET
Tr2 pチャネル型MISFET
Vdd 電源電位
Vss 接地電位
Y1 距離
Y2 距離
Claims (14)
- 一対の短辺と一対の長辺を有する矩形形状の半導体チップを備える半導体装置であって、
前記半導体チップは、
(a)前記半導体チップの第1長辺に沿って一直線上に配置され、かつ、前記第1長辺と対向する第2長辺よりも前記第1長辺側に近い位置に配置されている複数の第1バンプ電極と、
(b)前記半導体チップに形成されている内部回路と、
(c)前記内部回路を静電気から保護し、かつ、前記複数の第1バンプ電極と電気的に接続する複数の第1静電保護回路とを有し、
前記複数の第1バンプ電極のうち一部の第1バンプ電極と電気的に接続する前記複数の第1静電保護回路のうち一部の第1静電保護回路は、前記一部の第1バンプ電極と平面的に重なる位置に配置されており、
前記複数の第1バンプ電極のうち他の第1バンプ電極と電気的に接続する前記複数の第1静電保護回路のうちの他の第1静電保護回路は、前記他の第1バンプ電極と平面的に重なる位置とは異なる位置に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の第1バンプ電極と前記内部回路とは、前記複数の第1静電保護回路を介して電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記一部の第1バンプ電極の数は、前記他の第1バンプ電極の数よりも少ないことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記他の第1バンプ電極の下層には前記内部回路が配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数の第1バンプ電極は、入力用バンプ電極であることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体チップは、
(d)前記第2長辺に沿って配置され、かつ、前記第1長辺よりも前記第2長辺側に近い位置に配置されている複数の第2バンプ電極と、
(e)前記内部回路を静電気から保護し、かつ、前記複数の第2バンプ電極と電気的に接続する複数の第2静電保護回路とを有することを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記複数の第2バンプ電極と前記内部回路とは、前記複数の第2静電保護回路を介して電気的に接続されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記複数の第2バンプ電極の下層には、前記複数の第2静電保護回路が配置されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記複数の第2バンプ電極は、出力用バンプ電極であることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記複数の第1バンプ電極が形成されている領域と、前記複数の第2バンプ電極が形成されている領域とに挟まれた内部領域に、前記他の第1静電保護回路が配置されていることを特徴とする半導体装置。 - 請求項10記載の半導体装置であって、
前記他の第1静電保護回路は、前記内部領域内の複数の領域に分割されて配置されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置であって、
前記複数の第2バンプ電極は、千鳥状に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体チップは、液晶表示装置を駆動するLCDドライバであることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記他の第1バンプ電極の下層には前記他の第1静電保護回路が配置されていないことを特徴とする半導体装置。
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CN201510407800.XA CN105070706B (zh) | 2009-07-24 | 2010-07-08 | 半导体器件 |
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US20140008793A1 (en) | 2014-01-09 |
KR101707687B1 (ko) | 2017-02-16 |
KR20170094108A (ko) | 2017-08-17 |
US20170243847A1 (en) | 2017-08-24 |
TW201104818A (en) | 2011-02-01 |
US20150255452A1 (en) | 2015-09-10 |
US10461053B2 (en) | 2019-10-29 |
TWI624919B (zh) | 2018-05-21 |
JP2011029396A (ja) | 2011-02-10 |
KR20110010578A (ko) | 2011-02-01 |
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US9659926B2 (en) | 2017-05-23 |
US9391066B2 (en) | 2016-07-12 |
US8564127B2 (en) | 2013-10-22 |
KR20170018285A (ko) | 2017-02-16 |
CN105070706A (zh) | 2015-11-18 |
CN101964342A (zh) | 2011-02-02 |
US20110018129A1 (en) | 2011-01-27 |
TW201616628A (zh) | 2016-05-01 |
KR20180019013A (ko) | 2018-02-22 |
TWI523173B (zh) | 2016-02-21 |
US20190027455A1 (en) | 2019-01-24 |
KR101932376B1 (ko) | 2018-12-24 |
CN105070706B (zh) | 2019-04-02 |
TW201820567A (zh) | 2018-06-01 |
US20160315078A1 (en) | 2016-10-27 |
CN101964342B (zh) | 2015-08-12 |
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