JP5395407B2 - 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法 - Google Patents
表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法 Download PDFInfo
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- JP5395407B2 JP5395407B2 JP2008289570A JP2008289570A JP5395407B2 JP 5395407 B2 JP5395407 B2 JP 5395407B2 JP 2008289570 A JP2008289570 A JP 2008289570A JP 2008289570 A JP2008289570 A JP 2008289570A JP 5395407 B2 JP5395407 B2 JP 5395407B2
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- bump electrode
- output bump
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- G—PHYSICS
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Description
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。
(a)第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する矩形半導体チップ;
(b)前記矩形半導体チップのデバイス面上の前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(c)前記矩形半導体チップの前記デバイス面上の前記表示装置駆動信号出力用の外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の内側出力バンプ電極列、
ここで、
(1)前記外側出力バンプ電極列に属する各外側出力バンプ電極および、前記内側出力バンプ電極列に属する各内側出力バンプ電極のそれぞれの主要部は金を主要な成分とする金系金属から構成されており、
(2)各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、各内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされており、
(3)前記矩形半導体チップの前記デバイス面上には、各外側出力バンプ電極には、プローブ針を接触させることなく、前記外側出力バンプ電極列に属さない他のバンプ電極にプローブ針を接触させることにより電気的テストを可能とするテスト回路が設けられている。
(d)前記矩形半導体チップの前記デバイス面上の前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記内側出力バンプ電極列に属する各内側出力バンプ電極の面積よりも大きい。
(a)第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する矩形半導体チップ;
(b)前記矩形半導体チップのデバイス面上の前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(c)前記矩形半導体チップの前記デバイス面上の前記表示装置駆動信号出力用の外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の内側出力バンプ電極列、
ここで、
(1)前記外側出力バンプ電極列に属する各外側出力バンプ電極と、前記内側出力バンプ電極列に属する各内側出力バンプ電極とは、ほぼ同一の面積を有し、それらの主要部は金を主要な成分とする金系金属から構成されており、
(2)各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、各内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされている。
(d)前記矩形半導体チップの前記デバイス面上の前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記内側出力バンプ電極列に属する各内側出力バンプ電極の面積よりも大きい。
(a)第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する矩形半導体チップ;
(b)前記矩形半導体チップのデバイス面上の前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(c)前記矩形半導体チップの前記デバイス面上の前記表示装置駆動信号出力用の外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の第1内側出力バンプ電極列;
(d)前記矩形半導体チップの前記デバイス面上の前記表示装置駆動信号出力用の前記第1内側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の第2内側出力バンプ電極列、
ここで、
(1)前記外側出力バンプ電極列に属する各外側出力バンプ電極、前記第1内側出力バンプ電極列に属する各第1内側出力バンプ電極、および前記第2内側出力バンプ電極列に属する各第2内側出力バンプ電極は、ほぼ同一の面積を有し、それらの主要部は金を主要な成分とする金系金属から構成されており、
(2)各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、各第1内側出力バンプ電極および各第2内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされている。
(d)前記矩形半導体チップの前記デバイス面上の前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記第1内側出力バンプ電極列に属する各第1内側出力バンプ電極および前記第2内側出力バンプ電極列に属する各第2内側出力バンプ電極の面積よりも大きい。
(x)ウエハのデバイス面上に第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する複数の矩形半導体チップ領域を形成する工程;
(y)前記複数の矩形半導体チップ領域の内の少なくとも一つの矩形半導体チップ領域に対する電気的試験を実行する工程、
ここで、前記複数の矩形半導体チップ領域の各矩形半導体チップ領域は以下を含む:
(a)前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(b)前記表示装置駆動信号出力用の外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の内側出力バンプ電極列、
ここで更に、
(1)前記外側出力バンプ電極列に属する各外側出力バンプ電極および、前記内側出力バンプ電極列に属する各内側出力バンプ電極のそれぞれの主要部は金を主要な成分とする金系金属から構成されており、
(2)各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、各内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされており、
(3)前記工程(y)の前記電気的試験は、各外側出力バンプ電極には、プローブ針を接触させることなく、前記外側出力バンプ電極列に属さない他のバンプ電極にプローブ針を接触させることにより電気的テストを実行する。
(c)前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記内側出力バンプ電極列に属する各内側出力バンプ電極の面積よりも大きい。
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。
次に、図1から図7に基づいて、本願発明の一実施の形態の半導体集積回路装置の製造方法におけるバンプ形成プロセスを説明する。この断面は、基本的に(バンプの繰り返し数は、ここでは2個である)図25のX2−X1断面に対応する。図1に示すように多数のデバイスや配線(酸化シリコン膜や種々のメタル層で形成されている)が形成されたウエハ1の主面上にたとえばシリコン・ナイトライド等(無機系のみでなく有機系の膜でもよい)のファイナル・パッシベーション膜61が形成されており、そのアルミニウム・パッド62に対応する部分には、パッド開口63が設けられている。次に図2に示すようにスパッタリングによりUBM(Under Bump Metal)膜すなわちアンダー・バンプ・メタル膜67、たとえば厚さ175マイクロ・メータ程度のチタン膜64(下層)、たとえば厚さ175マイクロ・メータ程度のパラジウム膜65(上層)が順次形成される(これらのUBM材料はあくまでも例示であって、他の同様の材料を排除するものではない。たとえば、パラジウム膜は金膜でもよいが、パラジウム膜を用いると、より信頼度が高くなる。また、金より、材料価格が若干安いメリットがある。)。図3に示すように、その上に、塗布システムを用いて、たとえば19から25マイクロ・メートル程度(たとえば20マイクロ・メートル)の厚さのポジ型レジスト膜12が形成される。ここで用いるレジスト液は、たとえば東京応化工業株式会社(Tokyo Ohka Kogyo Co., LTD.)製のジアゾ・ナフトキノン・ノボラック系厚膜用ポジ型レジスト、製品名称「PMER P-LA900PM」等がある。塗布系レジストの変わりにフィルムレジストを用いてもよい。図4に示すように、レジストを露光、現像することで開口66を形成する。図5に示すように、開口66に電気メッキでたとえば15マイクロ・メータ程度の厚さのバンプ電極15となる金層を埋め込む。次に図6に示すように、レジスト膜12を除去する。最後に図7に示すように、金バンプ15をマスクにしてウエットエッチングで不要なUBM膜を選択除去する。これでバンプ電極が一応完成したことになる。金バンプ15は、通常、比較的純粋な金材料から構成されている(通常、ビッカース強度30から110程度である)。しかし、基本的には、金を主要な成分とする金系合金で構成することができる。
図20は本願発明の一実施の形態の半導体集積回路装置の半導体チップ上面全体レイアウト図である。これに基づいて、本願の各実施の形態の半導体集積回路装置のデバイス・回路構成等を説明する。なお、本実施の形態では、LCD用ICとして、液晶表示装置を駆動する液晶表示駆動用の半導体集積回路装置(LCDドライバ)を例示する。
これまでの説明に基づき、本願発明の一実施の形態の半導体集積回路装置(液晶ドライバ)の製造方法におけるウエハ・プローブ検査工程等を説明する。
以下では、セクション2の図20において、説明した回路レイアウトと同様な回路レイアウトを有するが、駆動出力用バンプ電極のレイアウトは若干異なる液晶ドライバチップ2について説明する。
図20に示すように、一般に駆動出力バンプ電極列3dの占める領域は、レイアウト制限やアルミニウム・エッチング・プロセスの関係で、ウエハの残余領域全体に拡大することは困難である。すなわち、図25および図27に示すように、駆動出力用バンプ電極15dの平坦化の観点から、多くのアルミニウム系配線68を配置する必要があるが、アルミニウム系配線68の面積が言って以上になると、エッチング終点検出が困難になる等の問題がある。従って、駆動出力バンプ電極列3dのレイアウトには、あまり自由度がなく、図12又は図13の例(第1の駆動出力用バンプ電極レイアウト)、図22の例(第2の駆動出力用バンプ電極レイアウト)および、これらの変形例に実質的に限られる。
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
1a ウエハのデバイス面
2 (一部配線層等を含む)半導体チップ(チップ領域)
2a 半導体チップのデバイス面
3 バンプ電極列
3d 駆動出力バンプ電極列
3p 非駆動出力バンプ電極列
3dp 外側出力バンプ電極列
3di 内側出力バンプ電極列
3dia 第1内側出力バンプ電極列
3dib 第2内側出力バンプ電極列
4 半導体チップ(チップ領域)の長辺
4a 半導体チップ(チップ領域)の第1の長辺
4b 半導体チップ(チップ領域)の第2の長辺
5 半導体チップ(チップ領域)の短辺
5a 半導体チップ(チップ領域)の第1の短辺
5b 半導体チップ(チップ領域)の第2の短辺
12 ポジ型レジスト膜
15 バンプ電極
15d 駆動出力用バンプ電極
15dp 外側駆動出力バンプ電極
15di 内側駆動出力バンプ電極
15dia 第1内側駆動出力バンプ電極
15dib 第2内側駆動出力バンプ電極
15p 非駆動出力用バンプ電極(I/Oおよび電源用バンプ電極)
16 第1内側駆動出力バンプ電極のピッチ方向中心線
17 第2内側駆動出力バンプ電極のピッチ方向中心線
18 外側駆動出力バンプ電極のピッチ方向中心線
42 ドライバ回路部
43 チップ内電源回路部
44 メモリ回路部
46 コントローラ部
47 不揮発性冗長ヒューズ回路部
61 ファイナル・パッシベーション膜
62 アルミニウム・パッド
63 パッド開口
64 チタン膜
65 パラジウム膜
66 レジスト開口
67 アンダー・バンプ・メタル膜(UBM膜)
68 実またはダミー・アルミニウム配線層
70 ウエハ・プローバ
71,77a,77b,77c,77d プローブ針
72 プローブ・カード
73 ウエハ・ステージ
74 テスト・ヘッド
75 テスタ
76 プローブ針先端部
77 プローブ針根元側
78a,78b,78c バッファ
79a,79b,79c,79d,79e トランスファ・ゲートMISFETスイッチ
80 テスト回路
101 ACF(Anisotropic Conductive Film)
102 ITO(Indium−Tin Oxide)リード
102d 駆動出力用ITOリード
102p 非駆動出力用ITOリード
500 液晶表示装置(液晶パネル)
501 ソース・ドライバ・チップ
502 ゲート・ドライバ・チップ
503 電源回路
510 画素
511 トランジスタ
512 コンデンサ
601 加圧力(圧着力)
A,B,C 出力信号
d プローブ針先端径
E チップ端部拡大部
G バンプ列間ギャップ
L1 外側駆動出力バンプ電極の長さ
L2 第1内側駆動出力バンプ電極および第2内側駆動出力バンプ電極の長さ
L3 非駆動出力用バンプ電極の長さ
P1 駆動出力バンプ・ピッチ
P2 I/Oおよび電源バンプ・ピッチ
W1 外側駆動出力バンプ電極の幅
W2 第1内側駆動出力バンプ電極および第2内側駆動出力バンプ電極の幅
W3 I/Oおよび電源バンプ電極の幅
Claims (16)
- 表示装置を駆動するための半導体集積回路装置であって以下を含む半導体集積回路装置:
(a)第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する矩形半導体チップ;
(b)前記矩形半導体チップのデバイス面上の前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(c)前記外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の内側出力バンプ電極列、
ここで、
前記外側出力バンプ電極列に属する各外側出力バンプ電極および、前記内側出力バンプ電極列に属する各内側出力バンプ電極のそれぞれの主要部は金を主要な成分とする金系金属から構成されており、
前記各外側出力バンプ電極および前記各内側出力バンプ電極は、それぞれの対応するアルミニウムを主要な成分とするアルミニウム系金属ボンディング・パッド上に形成されており、
前記各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、前記各内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされており、
前記矩形半導体チップの前記デバイス面上には、前記各外側出力バンプ電極にプローブ針を接触させることなく、前記各内側出力バンプ電極に前記プローブ針を接触させることにより電気的テストを可能とするテスト回路が設けられている。 - 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、前記各外側出力バンプ電極と、前記各内側出力バンプ電極とは、ほぼ同一の面積を有する。
- 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、
前記各外側出力バンプ電極および前記各内側出力バンプ電極のそれぞれの面積は、前記対応するボンディング・パッドの面積よりも大きい。 - 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、前記各外側出力バンプ電極および、前記各内側出力バンプ電極のそれぞれのピッチは、ほぼ同一、且つ、一定である。
- 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、前記各内側出力バンプ電極のピッチ方向の中心位置は、表示装置側の対応する配線のピッチ方向の中心位置から実質的にシフトしている。
- 請求項1に記載の表示装置を駆動するための半導体集積回路装置は、更に以下を含む:
(d)前記矩形半導体チップの前記デバイス面上の前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記各内側出力バンプ電極の面積よりも大きい。 - 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、前記表示装置は、液晶表示装置である。
- 請求項1に記載の表示装置を駆動するための半導体集積回路装置において、前記各内側出力バンプ電極の前記第1の長辺に沿った幅は、前記プローブ針の先端部の径よりも広い。
- 表示装置を駆動するための半導体集積回路装置の製造方法であって、以下の工程を含む半導体集積回路装置の製造方法:
(x)ウエハのデバイス面上に第1および第2の短辺および、それよりも5倍以上長い第1および第2の長辺を有する複数の矩形半導体チップ領域を形成する工程;
(y)前記複数の矩形半導体チップ領域の内の少なくとも一つの矩形半導体チップ領域に対する電気的試験を実行する工程、
ここで、前記複数の矩形半導体チップ領域の各矩形半導体チップ領域は以下を含む:
(a)前記第1の長辺に近接して、且つ、それに沿って配置された表示装置駆動信号出力用の外側出力バンプ電極列;
(b)前記外側出力バンプ電極列に近接して、且つ、それに沿って、より内側に配置された表示装置駆動信号出力用の内側出力バンプ電極列、
ここで更に、
前記外側出力バンプ電極列に属する各外側出力バンプ電極および、前記内側出力バンプ電極列に属する各内側出力バンプ電極のそれぞれの主要部は金を主要な成分とする金系金属から構成されており、
前記各外側出力バンプ電極および前記各内側出力バンプ電極は、それぞれの対応するアルミニウムを主要な成分とするアルミニウム系金属ボンディング・パッド上に形成されており、
前記各外側出力バンプ電極の前記第1の長辺に沿った幅と比較して、前記各内側出力バンプ電極の前記第1の長辺に沿った幅は、広くされており、
前記工程(y)の前記電気的試験は、前記各外側出力バンプ電極には、プローブ針を接触させることなく、前記各内側出力バンプ電極に前記プローブ針を接触させることにより電気的テストを実行する。 - 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、前記各外側出力バンプ電極と、前記各内側出力バンプ電極とは、ほぼ同一の面積を有する。
- 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、
前記各外側出力バンプ電極および前記各内側出力バンプ電極のそれぞれの面積は、前記対応するボンディング・パッドの面積よりも大きい。 - 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、前記各外側出力バンプ電極および、前記各内側出力バンプ電極のそれぞれのピッチは、ほぼ同一、且つ、一定である。
- 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、前記各内側出力バンプ電極のピッチ方向の中心位置は、表示装置側の対応する配線のピッチ方向の中心位置から実質的にシフトしている。
- 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法は、更に以下を含む:
(d)前記矩形半導体チップの前記デバイス面上の前記第2の長辺に近接して、且つ、それに沿って配置されたI/Oまたは電源端子用バンプ電極列、
ここで、前記I/Oまたは電源端子用バンプ電極列に属する各I/Oまたは電源端子用バンプ電極の面積は、前記各内側出力バンプ電極の面積よりも大きい。 - 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、前記表示装置は、液晶表示装置である。
- 請求項9に記載の表示装置を駆動するための半導体集積回路装置の製造方法において、前記各内側出力バンプ電極の前記第1の長辺に沿った幅は、前記プローブ針の先端部の径よりも広い。
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2008
- 2008-11-12 JP JP2008289570A patent/JP5395407B2/ja not_active Expired - Fee Related
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2009
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2012
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US20130075897A1 (en) | 2013-03-28 |
JP2010118428A (ja) | 2010-05-27 |
US20100117081A1 (en) | 2010-05-13 |
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