JP4693428B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP4693428B2 JP4693428B2 JP2005020111A JP2005020111A JP4693428B2 JP 4693428 B2 JP4693428 B2 JP 4693428B2 JP 2005020111 A JP2005020111 A JP 2005020111A JP 2005020111 A JP2005020111 A JP 2005020111A JP 4693428 B2 JP4693428 B2 JP 4693428B2
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- 239000004065 semiconductor Substances 0.000 title claims description 85
- 229910052751 metal Inorganic materials 0.000 claims description 86
- 239000002184 metal Substances 0.000 claims description 86
- 239000000872 buffer Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 108010068991 arginyl-threonyl-prolyl-prolyl-prolyl-seryl-glycine Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Microcomputers (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、実施の形態1の半導体集積回路のレイアウトを示す図である。図1を参照して、半導体集積回路1は、中央処理装置(図中、CPUと示す)2、中央処理装置2で行なわれる所定の処理に関する情報を不揮発的に記憶する不揮発性メモリ4、およびその情報を一時的に記憶する揮発性メモリ6を含む。不揮発性メモリ4は、たとえばフラッシュメモリである。揮発性メモリ6は、たとえばSRAM(Static Random Access Memory)である。
図4は、実施の形態2の半導体集積回路のレイアウトを示す図である。図4を参照して、半導体集積回路21は複数の領域SP5,SP6を含む点において図1の半導体集積回路1と異なる。実施の形態2においてバッファ(または保護回路)は領域SP5,SP6にブロック化されて配置される。図4では領域SP5,SP6に配置されたブロックをそれぞれブロックBC1,BC2として示す。
図5は、実施の形態3の半導体集積回路のレイアウトを示す図である。図5を参照して、半導体集積回路31は金属配線L1〜L9と同一の配線層に各々形成され、所定の電位が与えられる金属配線であるダミー配線DL1〜DL8をさらに含む点において図1の半導体集積回路1と異なる。半導体集積回路31の他の構成は半導体集積回路1の対応する部分の構成と同様であるので以後の説明は繰返さない。なお、半導体集積回路31においてバッファまたは保護回路は領域SP1に設けられるブロックBC3として示される。
図7は、実施の形態4の半導体集積回路のレイアウトを示す図である。図7を参照して、半導体集積回路41のレイアウトは図5の半導体集積回路31のレイアウトと同様であるので以後の説明は繰返さない。金属配線L1〜L9およびダミー配線DL1〜DL8の側面には誘電体により構成される側壁が設けられる点で実施の形態4は実施の形態3と相違する。
図10は、実施の形態5の半導体集積回路のレイアウトを示す図である。図10を参照して、半導体集積回路51は金属配線L3,L4,L5,L6に代えてジグザグ状に形成された部分を有する金属配線L3B,L4B,L5B,L6Bを含む点において図1の半導体集積回路1と異なる。なお半導体集積回路51の他の部分の構成については半導体集積回路1の対応する部分の構成と同様であるので以後の説明は繰返さない。
Claims (6)
- 中央処理装置と、
前記中央処理装置で行なわれる処理に関する情報を不揮発的に記憶する不揮発性メモリと、
前記情報を一時的に記憶する揮発性メモリと、
半導体基板の主表面において、前記中央処理装置、前記不揮発性メモリおよび前記揮発性メモリのうち少なくとも2つにより挟まれる領域に集合的に配置される、複数のバッファまたは複数の保護回路と、
前記複数のバッファまたは前記複数の保護回路にそれぞれ対応して設けられる、複数のパッドと、
前記複数のバッファまたは複数の保護回路の各々と、前記複数のパッドのうちの対応するパッドとを直接接続する、複数の金属配線とを備え、
前記複数の金属配線の各々は、多層配線のうちの同一の配線層に設けられ、
前記不揮発性メモリは、金属により構成される複数の第1のビット線を有し、
前記揮発性メモリは、金属により構成される複数の第2のビット線を有し、
前記複数の金属配線は、前記複数の第1のビット線のいずれか、または、前記複数の第2のビット線のいずれかに平行する部分を有する金属配線を含み、
金属により構成され、前記複数の金属配線の各々と同じ配線層に、前記平行する部分を側面から挟むように設けられる第1、第2のダミー配線と、
絶縁体により構成され、前記複数の金属配線の各々の側面および前記第1、第2のダミー配線の各々の側面に設けられる複数の側壁と、
前記複数の金属配線、前記第1、第2のダミー配線、および前記複数の側壁を覆う絶縁膜とをさらに備え、
前記第1、第2のダミー配線には、所定の電位が与えられ、
前記複数の側壁の各々の誘電率は、前記絶縁膜の誘電率よりも高い、半導体集積回路。 - 前記複数の金属配線は、前記中央処理装置に含まれる金属配線が設けられる配線層、前記不揮発性メモリに含まれる金属配線が設けられる配線層、および前記揮発性メモリに含まれる金属配線が設けられる配線層のいずれの配線層よりも前記主表面に対して上側にある、請求項1に記載の半導体集積回路。
- 前記複数のバッファまたは複数の保護回路は、前記主表面において単数の領域に集合して配置される、請求項2に記載の半導体集積回路。
- 前記複数のバッファまたは前記複数の保護回路は、前記主表面において複数の領域に分散して配置される、請求項2に記載の半導体集積回路。
- 前記所定の電位は、電源電位または接地電位である、請求項1に記載の半導体集積回路。
- 前記複数の金属配線は、前記複数の金属配線の各々が形成される配線層において、前記複数の第1のビット線のいずれか、または、前記複数の第2のビット線のいずれかに平行な第1の方向と、前記第1の方向と異なる第2の方向とに交互に方向を変えて複数回折れ曲がるように形成される金属配線を含む、請求項2に記載の半導体集積回路。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005020111A JP4693428B2 (ja) | 2005-01-27 | 2005-01-27 | 半導体集積回路 |
US11/328,194 US7358548B2 (en) | 2005-01-27 | 2006-01-10 | Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner |
TW095100837A TW200644161A (en) | 2005-01-27 | 2006-01-10 | Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner |
KR1020060008212A KR20060086880A (ko) | 2005-01-27 | 2006-01-26 | 반도체 집적 회로 |
CNB2006100024302A CN100536133C (zh) | 2005-01-27 | 2006-01-27 | 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路 |
US12/071,624 US20080149966A1 (en) | 2005-01-27 | 2008-02-25 | Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005020111A JP4693428B2 (ja) | 2005-01-27 | 2005-01-27 | 半導体集積回路 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006210607A JP2006210607A (ja) | 2006-08-10 |
JP2006210607A5 JP2006210607A5 (ja) | 2008-02-14 |
JP4693428B2 true JP4693428B2 (ja) | 2011-06-01 |
Family
ID=36695849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005020111A Expired - Fee Related JP4693428B2 (ja) | 2005-01-27 | 2005-01-27 | 半導体集積回路 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7358548B2 (ja) |
JP (1) | JP4693428B2 (ja) |
KR (1) | KR20060086880A (ja) |
CN (1) | CN100536133C (ja) |
TW (1) | TW200644161A (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4693428B2 (ja) * | 2005-01-27 | 2011-06-01 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
TWI381385B (zh) * | 2007-05-04 | 2013-01-01 | Macronix Int Co Ltd | 具有嵌入式多類型記憶體的記憶體結構 |
KR100798896B1 (ko) * | 2007-06-07 | 2008-01-29 | 주식회사 실리콘웍스 | 반도체 칩의 패드 배치 구조 |
US8138787B2 (en) * | 2008-07-13 | 2012-03-20 | Altera Corporation | Apparatus and method for input/output module that optimizes frequency performance in a circuit |
JP5419431B2 (ja) | 2008-11-28 | 2014-02-19 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP5503208B2 (ja) * | 2009-07-24 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11367478B2 (en) | 2020-01-14 | 2022-06-21 | Changxin Memory Technologies, Inc. | Integrated circuit structure and memory |
WO2021143050A1 (zh) * | 2020-01-14 | 2021-07-22 | 长鑫存储技术有限公司 | 集成电路结构和存储器 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH09232437A (ja) * | 1996-02-27 | 1997-09-05 | Hitachi Ltd | 半導体集積回路装置およびそれを用いたコンピュータシステム |
JP2000133777A (ja) * | 1998-10-26 | 2000-05-12 | Nec Corp | 半導体集積回路 |
JP2002050742A (ja) * | 2000-07-31 | 2002-02-15 | Nec Corp | 半導体装置およびその製造方法 |
JP2002170929A (ja) * | 2000-11-29 | 2002-06-14 | Fujitsu Ltd | 半導体装置 |
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US4454591A (en) * | 1980-05-29 | 1984-06-12 | Texas Instruments Incorporated | Interface system for bus line control |
US5300796A (en) * | 1988-06-29 | 1994-04-05 | Hitachi, Ltd. | Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells |
JPH08125130A (ja) | 1994-10-26 | 1996-05-17 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JP3380465B2 (ja) * | 1998-06-29 | 2003-02-24 | 松下電器産業株式会社 | 半導体装置 |
US6502231B1 (en) * | 2001-05-31 | 2002-12-31 | Applied Micro Circuits Corporation | Integrated circuit template cell system and method |
JP2003158195A (ja) * | 2001-11-20 | 2003-05-30 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
DE10220923B4 (de) * | 2002-05-10 | 2006-10-26 | Infineon Technologies Ag | Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers |
US6735108B2 (en) * | 2002-07-08 | 2004-05-11 | Micron Technology, Inc. | ROM embedded DRAM with anti-fuse programming |
US7003750B2 (en) * | 2002-08-01 | 2006-02-21 | Sun Microsystems, Inc. | Topology based wire shielding generation |
JP4190865B2 (ja) * | 2002-11-11 | 2008-12-03 | Necエレクトロニクス株式会社 | 半導体メモリ |
JP4624660B2 (ja) * | 2003-10-09 | 2011-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7006370B1 (en) * | 2003-11-18 | 2006-02-28 | Lsi Logic Corporation | Memory cell architecture |
JP4693428B2 (ja) * | 2005-01-27 | 2011-06-01 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
-
2005
- 2005-01-27 JP JP2005020111A patent/JP4693428B2/ja not_active Expired - Fee Related
-
2006
- 2006-01-10 TW TW095100837A patent/TW200644161A/zh unknown
- 2006-01-10 US US11/328,194 patent/US7358548B2/en not_active Expired - Fee Related
- 2006-01-26 KR KR1020060008212A patent/KR20060086880A/ko not_active Application Discontinuation
- 2006-01-27 CN CNB2006100024302A patent/CN100536133C/zh not_active Expired - Fee Related
-
2008
- 2008-02-25 US US12/071,624 patent/US20080149966A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09232437A (ja) * | 1996-02-27 | 1997-09-05 | Hitachi Ltd | 半導体集積回路装置およびそれを用いたコンピュータシステム |
JP2000133777A (ja) * | 1998-10-26 | 2000-05-12 | Nec Corp | 半導体集積回路 |
JP2002050742A (ja) * | 2000-07-31 | 2002-02-15 | Nec Corp | 半導体装置およびその製造方法 |
JP2002170929A (ja) * | 2000-11-29 | 2002-06-14 | Fujitsu Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20080149966A1 (en) | 2008-06-26 |
US20060163615A1 (en) | 2006-07-27 |
US7358548B2 (en) | 2008-04-15 |
KR20060086880A (ko) | 2006-08-01 |
TW200644161A (en) | 2006-12-16 |
CN1819196A (zh) | 2006-08-16 |
CN100536133C (zh) | 2009-09-02 |
JP2006210607A (ja) | 2006-08-10 |
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