WO2021143050A1 - 集成电路结构和存储器 - Google Patents

集成电路结构和存储器 Download PDF

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Publication number
WO2021143050A1
WO2021143050A1 PCT/CN2020/098521 CN2020098521W WO2021143050A1 WO 2021143050 A1 WO2021143050 A1 WO 2021143050A1 CN 2020098521 W CN2020098521 W CN 2020098521W WO 2021143050 A1 WO2021143050 A1 WO 2021143050A1
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input
pad
output circuit
area
sub
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PCT/CN2020/098521
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English (en)
French (fr)
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张良
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长鑫存储技术有限公司
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Priority claimed from CN202010036694.XA external-priority patent/CN113129942A/zh
Priority claimed from CN202020082043.XU external-priority patent/CN210805230U/zh
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20914624.0A priority Critical patent/EP3923285B1/en
Priority to US17/197,051 priority patent/US11367478B2/en
Publication of WO2021143050A1 publication Critical patent/WO2021143050A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular to an integrated circuit structure and memory.
  • DDR4SDRAM Double Data Rate Fourth Synchronous Access Memory, the fourth generation of double data rate synchronous dynamic random access memory
  • DDR4 SDRAM has a lower power supply voltage and a higher transmission rate.
  • the bank group on it has the characteristics of independently starting operations such as reading and writing.
  • DDR4SDRAM not only has fast and power-saving features, it can also enhance signal integrity and improve the reliability of data transmission and storage.
  • the low-power memory chip LPDDR4 Take the low-power memory chip LPDDR4 as an example.
  • the data strobe signal (DQS) and the data signal (DQ) are transmitted to LPDDR4 at approximately the same speed through a transmission path of approximately the same length.
  • the DQS input circuit module transmits the received DQS signal as a strobe sample to the DQ input circuit module to collect data. Since it takes a period of time for the DQS signal to be transmitted to the DQ input circuit module, this causes the DQS signal to be out of sync with the DQ signal.
  • the DQS signal can be sent in advance.
  • the JEDEC standard defines the parameter tDQS2DQ to characterize the time for sending in advance.
  • tDQS2DQ tends to have a large value and is susceptible to temperature and voltage interference on the transmission path, which affects the performance of the memory.
  • the purpose of the present disclosure is to provide an integrated circuit structure and memory, thereby at least to some extent overcome the problem of large tDQS2DQ value and susceptibility to temperature and voltage interference on the transmission path due to limitations and defects of related technologies.
  • an integrated circuit structure including:
  • the pad area includes a plurality of signal pads arranged along the target direction;
  • the circuit area is set on one side of the pad area and includes a plurality of input/output circuit modules arranged along the target direction and respectively connected to each of the signal pads, each of the input/output circuit modules Is configured to implement a sampling operation of an input signal and write a sampling result into a storage array, and read out the data stored in the storage array;
  • the size of the circuit area along the target direction is smaller than the size of the pad area along the target direction.
  • the multiple signal pads include:
  • a first differential data strobe pad, a second differential data strobe pad, a data mask pad and a plurality of data input/output pads are provided.
  • the pad area further includes:
  • the pad area includes:
  • the first pad sub-region and the second pad sub-region, the first pad sub-region and the second pad sub-region contain the same number of data input/output pads, and the number is the total number of data input/output pads. Half of the quantity
  • the first differential data strobe pad, the second differential data strobe pad and the data mask pad are arranged between the first pad sub-region and the second pad sub-region.
  • the multiple input/output circuit modules include:
  • Data strobe input/output circuit module Data mask input/output circuit module and multiple data input/output circuit modules.
  • the circuit area includes:
  • the first circuit sub-area and the second circuit sub-area, the first circuit sub-area and the second circuit sub-area contain the same number of data input/output circuit modules, and the number is the total number of data input/output circuit modules. Half of the quantity
  • the data strobe input/output circuit module and the data mask input/output circuit module are arranged between the first circuit sub-region and the second circuit sub-region.
  • the data strobe input/output circuit module is respectively connected to the first differential data strobe pad and the second differential data strobe pad.
  • the distance between adjacent input/output circuit modules is less than a distance threshold
  • the distance threshold is determined based on the size of the pad area along the target direction and the size of each input/output circuit module along the target direction.
  • the aspect ratio of the area occupied by each of the input/output circuit modules along the target direction is less than a ratio threshold.
  • a memory including the integrated circuit structure as described in any one of the above.
  • the DQS signal is reduced.
  • the length of the path transmitted to the DQ input circuit module reduces tDQS2DQ; on the other hand, a short path can reduce temperature and voltage interference, greatly improve temperature and voltage performance, and reduce current consumption, which helps ensure The integrity of the signal, thereby improving the performance of the memory.
  • Figure 1 shows a schematic diagram of the integrated circuit structure of some technologies
  • FIG. 2 shows a schematic diagram of an integrated circuit structure according to an exemplary embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of an integrated circuit structure according to another exemplary embodiment of the present disclosure.
  • the DQ input circuit module can obtain the signal transmitted by the DQ port, and this signal is often not a signal that can be directly processed by the digital circuit due to parasitic effects and various interferences. .
  • the DQ input circuit module needs to sample the acquired DQ signal with the aid of the DQS signal, and the DQ input circuit module writes the sampled result into the storage array.
  • the semiconductor memory chip can send the DQS signal one tDQS2DQ in advance to the LPDDR4, so that the DQS signal and the DQ signal can reach the DQ input circuit module synchronously, so as to improve the accuracy of sampling the DQ signal by the DQ input circuit module.
  • tDQS2DQ is easily affected by factors such as LPDDR4 internal operating voltage or operating temperature.
  • tDQS2DQ needs to be adjusted by continuously detecting changes in internal operating voltage, operating temperature and other parameters. The detection process consumes time and energy. This results in slower writing speed, which affects the performance of the memory.
  • Figure 1 shows a schematic diagram of an integrated circuit structure of some technologies.
  • the DQ input/output circuit module and the signal pad are manufactured and configured together, the path for the acquired DQS signal to reach the DQ input/output circuit module at the two ends is long, which is occupied by the signal pad.
  • the length of the area is approximate.
  • DQ includes 8 bits in total from DQ0 to DQ7
  • the sum of the paths of the DQS signal to the DQ0 and DQ7 input/output circuit modules is about 1140 ⁇ m.
  • the sum of the paths is recorded as the path corresponding to tDQS2DQ.
  • the path corresponding to tDQS2DQ is shortened, the influence of tDQS2DQ on operating voltage and operating temperature will also be reduced.
  • the shortening of the path can also reduce current consumption and help ensure signal integrity. As a result, the write performance of the memory can be improved.
  • the integrated circuit structure may include a pad area 21 and a circuit area 22.
  • the pad area 21 includes a plurality of signal pads arranged along a target direction, where the signal pad refers to a pad corresponding to each data signal port, and may include but is not limited to a plurality of data input/output pads, first The differential data strobe pad, the second differential data strobe pad and the data mask pad.
  • multiple data input/output pads include DQ0 pads, DQ1 pads, DQ2 pads, DQ3 pads, and DQ4 soldering pads. Pad, DQ5 pad, DQ6 pad and DQ7 pad. However, it should be understood that, depending on the memory type, the multiple data input/output pads may also include a total of 16 pads from DQ0 to DQ15, etc., which is not limited in the present disclosure.
  • the data input/output pad performs writing and reading operations in one.
  • the data input/output pad receives the data signal from the pin through the lead and sends the data signal to the corresponding circuit module; in the process of performing the read operation, the data input/output The output pad receives the data signal from the corresponding circuit module and sends the signal through the pin.
  • a memory above DDR4 may include a first differential data strobe pad (denoted as DQS_t pad) and a second differential data strobe pad (denoted as DQS_c pad).
  • the signal received by the first differential data strobe pad and the signal received by the second differential data strobe pad have the same amplitude and opposite phase.
  • the time point at which the two differential signals cross can be, for example, the time point of sampling, and the data signal is sampled accordingly.
  • DM pad For the data mask pad (DM pad), a mask signal for performing a partial write function can be input. When the received mask signal is low, the bit corresponding to the input data will be discarded.
  • the pad area 21 may also include a plurality of power supply pads (VDDQ pads) and a plurality of ground pads (VSSQ pads) for providing power and ground terminals.
  • VDDQ pads power supply pads
  • VSSQ pads ground pads
  • the pad area 21 may include a first pad sub-region 211 and a second pad sub-region 212.
  • the number of data input/output pads included in the first pad sub-region 211 is the same as the number of data input/output pads included in the second pad sub-region 212, and the number is half of the total number of data input/output pads.
  • the first pad subregion 211 includes DQ0 pads, DQ1 pads, DQ2 pads, and DQ3 pads
  • the second pad subregion 212 includes DQ4 pads, DQ5 pads, DQ6 pads, and DQ7 pads.
  • the first differential data strobe pad, the second differential data strobe pad, and the data mask pad may be arranged between the first pad sub-region 211 and the second pad sub-region 212 so as to differentiate
  • the data strobe signal makes it easier to match the paths of each DQ input circuit module, avoiding the problem of excessive distance difference.
  • any one of the first differential data strobe pad, the second differential data strobe pad, and the data mask pad may be configured in the pad area 21.
  • One side, and its position relative to each data input/output pad is not restricted.
  • the circuit area 22 it is provided on one side of the pad area 21, that is, the circuit area 22 and the pad area 21 are two areas without overlapping areas.
  • the circuit area 22 includes a plurality of input/output circuit modules arranged along a target direction, and each input/output circuit module is connected to a corresponding signal pad through a metal wire.
  • each input/output circuit module performs a write operation, it is configured to sample the input signal and write the sampled result into the storage array; when each input/output circuit module performs a read operation, it is configured to read Export the data stored in the storage array.
  • the multiple input/output circuit modules may include multiple data input/output circuit modules, data strobe input/output circuit modules, and data mask input/output circuit modules.
  • the multiple data input/output circuit modules may include DQ0 input/output circuit modules, DQ1 input/output circuit modules, and DQ2 input/output circuit modules.
  • Each DQ input/output circuit module may be configured to receive the data signal sent by the corresponding DQ input/output pad, and sample the data signal in response to the data strobe signal to write the sampling result into the storage array.
  • the data strobe input/output circuit module may be configured to send a data strobe signal to each DQ input/output circuit module.
  • the data mask input/output circuit module may be configured to obtain mask information and perform corresponding partial write operations.
  • the circuit area 22 includes a first circuit sub-area 221 and a second circuit sub-area 222.
  • the number of data input/output circuit modules included in the first circuit subarea 221 is the same as the number of data input/output circuit modules included in the second circuit subarea 222, and the number is half of the total number of data input/output circuit modules.
  • the first circuit sub-region 221 includes DQ0 input/output circuit modules, DQ1 input/output circuit modules, DQ2 input/output circuit modules, and DQ3 input/output circuit modules
  • the second circuit sub-region 222 includes DQ4 input/output circuit modules.
  • DQ5 input/output circuit module, DQ6 input/output circuit module and DQ7 input/output circuit module includes DQ5 input/output circuit module.
  • the data strobe input/output circuit module and the data mask input/output circuit module are arranged between the first circuit sub-region 221 and the second circuit sub-region 222.
  • the data strobe input/output circuit module may be connected to the first differential data strobe pad and the second differential data strobe pad through metal wires.
  • the size of the circuit region 22 in the target direction is smaller than the size of the pad region 21 in the target direction.
  • the size of the circuit area 22 in the target direction refers to the length of the circuit area 22 in the direction in which the multiple input/output circuit modules are arranged, that is, the path length corresponding to tDQS2DQ.
  • a short path can reduce temperature and voltage interference, greatly improve temperature and voltage performance, and can also reduce current consumption, help ensure signal integrity, and thereby improve memory performance.
  • the distance between adjacent input/output circuit modules is smaller than the distance threshold.
  • the distance threshold can be determined according to the size of the pad area 21 along the target direction and the size of each input/output circuit module along the target direction, so that the size of the circuit area 22 along the target direction is smaller than that of the pad area 21 along the target direction. size of. It should be noted that the distance between adjacent input/output circuit modules may be the same or different.
  • the size of the circuit area along the target direction can be set smaller.
  • the pad area 31 is the same as the pad area 21 in FIG. 2, and will not be described again.
  • the distance between adjacent input/output circuit modules can be as small as possible, that is, the above-mentioned distance threshold can be configured to be as small as possible.
  • it is configured as an adjacent structure, which further shortens the path length corresponding to tDQS2DQ, while saving more space in the manufacturing process.
  • the path corresponding to tDQS2DQ is about 700 ⁇ m. Compared with the 1140 ⁇ m in some technologies in FIG. 1, the path length is greatly reduced.
  • the aspect ratio of the area occupied by each input/output circuit module along the target direction is smaller than the ratio threshold.
  • the length of each input/output circuit module along the target direction can be configured to be shorter.
  • each input/output circuit module can be appropriately increased along the direction perpendicular to the target direction. On the length.
  • the present disclosure does not limit the specific value of the ratio threshold.
  • the metal line from the pad to the input/output circuit module can be configured to be very narrow, thus, a large current drive is not required, and input capacitance can be reduced.
  • the present disclosure also provides a memory, which includes any of the above-mentioned integrated circuit structures.
  • DDR4 SDRAM such as LPDDR4, or DDR5 memory.

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Abstract

本公开提供了一种集成电路结构和存储器，涉及半导体存储器技术领域。该集成电路结构包括：焊盘区域，包括沿目标方向配置的多个信号焊盘；电路区域，设于所述焊盘区域的一侧，包括沿所述目标方向配置的且分别与各所述信号焊盘对应连接的多个输入/输出电路模块，各所述输入/输出电路模块被配置为实现输入信号的采样操作并将采样结果写入存储阵列，以及读出所述存储阵列存储的数据；其中，所述电路区域沿所述目标方向的尺寸小于所述焊盘区域沿所述目标方向的尺寸。本公开可以提高存储器写操作的性能。 (图2)

Description

集成电路结构和存储器
相关申请的交叉引用
本申请要求于2020年01月14日提交的申请号为202010036694.X、名称为“集成电路结构和存储器”的中国专利申请以及申请号为202020082043.X、名称为“集成电路结构和存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种集成电路结构和存储器。
背景技术
随着存储器技术的发展，DDR4SDRAM(Double Data Rate Fourth Synchronous Dynamic Random Access Memory，第四代双倍数据率同步动态随机存取存储器)应运而生，DDR4SDRAM具有较低的供电电压、较高的传输速率，其上的存储单元组(Bank Group)具有独立启动操作读、写等动作的特性。另外，相比于例如DDR3/DDR2的存储器，DDR4SDRAM在具有快速、省电特性的同时，还可以增强信号的完整性，提高了数据传输及存储的可靠性。
以低功耗内存芯片LPDDR4为例，在写操作的过程中，数据选通信号(DQS)与数据信号(DQ)通过近似相同长度的传输路径以近似相同的速度传送至LPDDR4中，在LPDDR4中，DQS输入电路模块将接收到的作为选通采样的DQS信号传送至DQ输入电路模块，以采集数据。由于DQS信号需要一段时间才能传送至DQ输入电路模块，这就导致DQS信号与DQ信号不同步。
为了补偿DQS信号与DQ信号的时间差，可以提前发送DQS信号。为此，JEDEC标准定义了参数tDQS2DQ，以表征提前发送的时间。
然而，tDQS2DQ往往数值较大，且易受传输路径上温度和电压的干扰，导致存储器的性能受到了影响。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种集成电路结构和存储器，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的tDQS2DQ数值较大且易受传输路径上温度和电压干扰的问题。
根据本公开的第一方面，提供一种集成电路结构，包括：
焊盘区域，包括沿目标方向配置的多个信号焊盘；
电路区域，设于所述焊盘区域的一侧，包括沿所述目标方向配置的且分别与各所述信号焊盘对应连接的多个输入/输出电路模块，各所述输入/输出电路模块被配置为实现输入信号的采样操作并将采样结果写入存储阵列，以及读出所述存储阵列存储的数据；
其中，所述电路区域沿所述目标方向的尺寸小于所述焊盘区域沿所述目标方向的尺寸。
可选地，所述多个信号焊盘包括：
第一差分数据选通焊盘、第二差分数据选通焊盘、数据掩膜焊盘和多个数据输入/输出焊盘。
可选地，所述焊盘区域还包括：
多个电源焊盘和多个接地焊盘。
可选地，所述焊盘区域包括：
第一焊盘子区域和第二焊盘子区域，所述第一焊盘子区域与所述第二焊盘子区域包含的数据输入/输出焊盘的数量相同，且数量均为数据输入/输出焊盘总数量的一半；
其中，所述第一差分数据选通焊盘、所述第二差分数据选通焊盘和数据掩膜焊盘配置在所述第一焊盘子区域与所述第二焊盘子区域之间。
可选地，所述多个输入/输出电路模块包括：
数据选通输入/输出电路模块、数据掩膜输入/输出电路模块和多个数据输入/输出电路模块。
可选地，所述电路区域包括：
第一电路子区域和第二电路子区域，所述第一电路子区域与所述第二电路子区域包含的数据输入/输出电路模块的数量相同，且数量均为数据输入/输出电路模块总数量的一半；
其中，所述数据选通输入/输出电路模块和所述数据掩膜输入/输出电路模块配置在所述第一电路子区域与所述第二电路子区域之间。
可选地，数据选通输入/输出电路模块分别与所述第一差分数据选通焊盘和所述第二差分数据选通焊盘连接。
可选地，相邻的所述输入/输出电路模块之间的距离小于距离阈值；
其中，所述距离阈值基于所述焊盘区域沿所述目标方向的尺寸以及各所述输入/输出电路模块沿所述目标方向的尺寸而确定出。
可选地，各所述输入/输出电路模块所占区域沿所述目标方向的宽高比小于比例阈值。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的集成电路结构。
在本公开的一些实施例所提供的技术方案中，通过将电路区域沿目标方向的尺寸配置为小于焊盘区域沿目标方向的尺寸，相比于现有技术，一方面，减小了DQS信号传送至DQ输入电路模块的路径长度，进而减小了tDQS2DQ；另一方面，短的路径可以减轻温度和电压的干扰，极大提高温度和电压性能，也可以减少电流的消耗，有助于确保信号的完整性，进而提高存储器的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示出了一些技术的集成电路结构的示意图；
图2示出了根据本公开的示例性实施方式的集成电路结构的示意图；
图3示出了根据本公开的另一示例性实施方式的集成电路结构的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
在例如LPDDR4的存储器执行写入操作的过程中，DQ输入电路模块可以获取DQ端口传送的信号，而这种信号由于受到寄生效应及各种干扰的影响，往往不是数字电路能够直接进行处理的信号。在这种情况下，DQ输入电路模块需要借助于DQS信号对获取的DQ信号进行采样，DQ输入电路模块将采样得到的结果写入存储阵列。
由于DQS信号和DQ信号到达LPDDR4所用的时间几乎相同，在LPDDR4内部，DQS信号还需要一段时间才能传送至DQ输入电路模块，这就造成了DQS信号与DQ信号不同步，为了避免这种情况，半导体存储器的芯片可以将DQS信号提前一个tDQS2DQ发送至LPDDR4中，使得DQS信号与DQ信号能够同步到达DQ输入电路模块，以提高DQ输入电路模块对DQ信号进行采样的准确率。
然而，tDQS2DQ容易受到LPDDR4内部工作电压或工作温度等因素的影响，为了解决这个问题，需要通过不断地检测内部工作电压、工作温度等参数的变化来调整tDQS2DQ，而检测过程耗时耗能，最终导致写入速度变慢，影响存储器的工作性能。
图1示出了一些技术的集成电路结构的示意图。在这些技术中，由于DQ输入/输出电路模块与信号焊盘在制造成配置在一起，导致获取到的DQS信号到达最两端的DQ输入/输出电路模块的路径较长，与信号焊盘所占区域的长度近似。在DQ包括DQ0至DQ7共计8位的情况下，如果对应信号焊盘间距(pad pitch)为60μm，那么DQS信号到达DQ0和DQ7输入/输出电路模块的路径之和约为1140μm。在本公开的示例性实施方式中，将该路径之和记为tDQS2DQ对应的路径。
鉴于此，如果将tDQS2DQ对应的路径缩短，那么tDQS2DQ受工作电压、工作温度等的影响也将减小，另外，路径的缩短，还可以减少电流消耗，有助于确保信号的完整性。由此，可以提高存储器的写入性能。
下面将参考图2对本公开一个示例性实施方式的集成电路结构进行说明。
参考图2，集成电路结构可以包括焊盘区域21和电路区域22。
焊盘区域21包括沿目标方向配置的多个信号焊盘，其中，信号焊盘指的是与各数据信号端口对应的焊盘，可以包括但不限于多个数据输入/输出焊盘、第一差分数据选通焊盘、第二差分数据选通焊盘和数据掩膜焊盘。
针对多个数据输入/输出焊盘，以DQ包括DQ0至DQ7共计8位为例，多个数据输入/输出焊盘包括与DQ0焊盘、DQ1焊盘、DQ2焊盘、DQ3焊盘、DQ4焊盘、DQ5焊盘、DQ6焊盘和DQ7焊盘。然而，应当理解的是，存储器类型的不同，多个数据输入/输出焊盘还可以包括DQ0至DQ15共计16个焊盘等，本公开对此不做限制。
数据输入/输出焊盘执行写入与读出操作于一体。在执行写入操作的过程中，数据输入/输出焊盘通过引线从引脚(pin)接收数据信号，并将数据信号发送给对应的电路模块；在执行读出操作的过程中，数据输入/输出焊盘接收来自对应电路模块的数据信号，并将该信号通过引脚发送出。
针对差分数据选通焊盘，在DDR4以上的存储器中，可以包括第一差分数据选通焊盘(记为DQS_t焊盘)和第二差分数据选通焊盘(记为DQS_c焊盘)。第一差分数据选通焊盘接收到的信号与第二差分数据选通焊盘接收到的信号幅值相同、相位相反。在利用差分信号进行采样的过程中，两个差分信号交叉的时间点可以例如是采样的时间点，据此对数据信号进行采样。
针对数据掩膜焊盘(DM焊盘)，可以输入有用于执行部分写入功能的掩码信号。当接收到的掩码信号为低电平时，输入数据对应的位将被丢弃。
此外，焊盘区域21还可以包括多个电源焊盘(VDDQ焊盘)和多个接地焊盘(VSSQ焊盘)，用于提供电源和接地端。
根据本公开的一个实施例，焊盘区域21可以包括第一焊盘子区域211和第二焊盘子区域212。第一焊盘子区域211包含的数据输入/输出焊盘的数量与第二焊盘子区域212包含的数据输入/输出焊盘的数量相同，且数量均为数据输入/输出焊盘总数量的一半。例如，第一焊盘子区域211包括DQ0焊盘、DQ1焊盘、DQ2焊盘和DQ3焊盘，第二焊盘 子区域212包括DQ4焊盘、DQ5焊盘、DQ6焊盘和DQ7焊盘。
在这种情况下，第一差分数据选通焊盘、第二差分数据选通焊盘和数据掩膜焊盘可以配置在第一焊盘子区域211与第二焊盘子区域212之间，以便差分数据选通信号更容易对各DQ输入电路模块进行路径匹配，避免出现距离相差过大的问题。
应当理解的是，根据本公开的另一些实施例，第一差分数据选通焊盘、第二差分数据选通焊盘和数据掩膜焊盘中的任意一个均可以配置于焊盘区域21的一侧，并对其相对于各数据输入/输出焊盘的位置不做限制。
针对电路区域22，其设于焊盘区域21的一侧，也就是说，电路区域22与焊盘区域21是没有重叠区域的两个区域。与焊盘区域21中多个信号焊盘对应的，电路区域22包括沿目标方向配置的多个输入/输出电路模块，各输入/输出电路模块通过金属线与对应的信号焊盘连接。各输入/输出电路模块在执行写入操作时，被配置为对输入信号的采样操作，并将采样的结果写入存储阵列；各输入/输出电路模块在执行读出操作时，被配置为读出存储阵列存储的数据。
其中，多个输入/输出电路模块可以包括多个数据输入/输出电路模块、数据选通输入/输出电路模块和数据掩膜输入/输出电路模块。
针对多个数据输入/输出电路模块，与上述多个数据输入/输出焊盘对应的，多个数据输入/输出电路模块可以包括DQ0输入/输出电路模块、DQ1输入/输出电路模块、DQ2输入/输出电路模块、DQ3输入/输出电路模块、DQ4输入/输出电路模块、DQ5输入/输出电路模块、DQ6输入/输出电路模块和DQ7输入/输出电路模块。
各DQ输入/输出电路模块可以被配置为接收对应DQ输入/输出焊盘发送的数据信号，并响应数据选通信号对该数据信号进行采样，以将采样结果写入存储阵列。
数据选通输入/输出电路模块可以被配置为将数据选通信号发送给各DQ输入/输出电路模块。
数据掩膜输入/输出电路模块可以被配置为获取掩码信息，并执行对应的部分写操作。
根据本公开的一个实施例，电路区域22包括第一电路子区域221和第二电路子区域222。第一电路子区域221包含的数据输入/输出电路模块的数量与第二电路子区域222包含的数据输入/输出电路模块的数量相同，且数量均为数据输入/输出电路模块总数量的一半。例如，第一电路子区域221包括DQ0输入/输出电路模块、DQ1输入/输出电路模块、DQ2输入/输出电路模块和DQ3输入/输出电路模块，第二电路子区域222包括DQ4输入/输出电路模块、DQ5输入/输出电路模块、DQ6输入/输出电路模块和DQ7输入/输出电路模块。
在这种情况下，数据选通输入/输出电路模块和数据掩膜输入/输出电路模块配置在第一电路子区域221与第二电路子区域222之间。
另外，参考图2，数据选通输入/输出电路模块可以通过金属线与第一差分数据选通焊盘和第二差分数据选通焊盘连接。
在本公开的示例性实施方式中，电路区域22沿目标方向的尺寸小于焊盘区域21沿目标方向的尺寸。如上所述，电路区域22沿目标方向的尺寸指的是，电路区域22沿配置多个输入/输出电路模块的方向的长度，也就是说，tDQS2DQ对应的路径长度。
将电路区域22沿目标方向的尺寸配置为小于焊盘区域21沿目标方向的尺寸，一方面，减小了DQS信号传送至DQ输入/输出电路模块的路径长度，进而减小了tDQS2DQ；另一方面，短的路径可以减轻温度和电压的干扰，极大提高温度和电压性能，也可以减少电流的消耗，有助于确保信号的完整性，进而提高存储器的性能。
根据本公开的一些实施例，在电路区域22中，相邻的输入/输出电路模块之间的距离小于距离阈值。其中，该距离阈值可以根据焊盘区域21沿目标方向的尺寸以及各输入/输出电路模块沿目标方向的尺寸而确定出，以使电路区域22沿目标方向的尺寸小于焊盘区域21沿目标方向的尺寸。应当注意的是，各相邻的输入/输出电路模块之间的距离可以相同，也可以不同。
如图2所示，各相邻的输入/输出电路模块之间可以存在间隙，以避免各模块之间相互干扰。
此外，针对电路区域沿目标方向的尺寸，可以设置地更小。
参考图3，焊盘区域31与图2中焊盘区域21相同，不再赘述。针对电路区域32，各相邻的输入/输出电路模块之间的距离可以尽可能小，也就是说，上述距离阈值可以被配置为尽可能小。如图3所示配置为紧邻的结构，进一步缩短tDQS2DQ对应的路径长度的同时，又可以在制造过程中节省更多空间。
就图3所示的示例性结构而言，tDQS2DQ对应的路径约为700μm，相比于图1一些技术中的1140μm，路径长度大大减小。
根据本公开的一些实施例，在图2或图3所示的集成电路结构中，各输入/输出电路模块所占区域沿目标方向的宽高比小于比例阈值。具体的，可以将各输入/输出电路模块沿目标方向的长度配置为较短，为了不影响模块的功能，在这种情况下，可以适当增加各输入/输出电路模块沿与目标方向垂直的方向上的长度。本公开对该比例阈值的具体取值不做限制。
另外，参考图2或图3，本公开实施例中，从焊盘到输入/输出电路模块的金属线可以被配置为很窄，由此，不需要大的电流驱动，并可以减少输入电容。
本公开还提供了一种存储器，该存储器包括上面所述的任意一种集成电路结构。
应当理解的是，本公开对存储器的类型不做限制，可以是例如LPDDR4的DDR4SDRAM，也可以是DDR5存储器等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指 出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (10)

  1. 一种集成电路结构，包括：
    焊盘区域，包括沿目标方向配置的多个信号焊盘；
    电路区域，设于所述焊盘区域的一侧，包括沿所述目标方向配置的且分别与各所述信号焊盘对应连接的多个输入/输出电路模块，各所述输入/输出电路模块被配置为实现输入信号的采样操作并将采样结果写入存储阵列，以及读出所述存储阵列存储的数据；
    其中，所述电路区域沿所述目标方向的尺寸小于所述焊盘区域沿所述目标方向的尺寸。
  2. 根据权利要求1所述的集成电路结构，其中，所述多个信号焊盘包括：
    第一差分数据选通焊盘、第二差分数据选通焊盘、数据掩膜焊盘和多个数据输入/输出焊盘。
  3. 根据权利要求2所述的集成电路结构，其中，所述焊盘区域还包括：
    多个电源焊盘和多个接地焊盘。
  4. 根据权利要求2所述的集成电路结构，其中，所述焊盘区域包括：
    第一焊盘子区域和第二焊盘子区域，所述第一焊盘子区域与所述第二焊盘子区域包含的数据输入/输出焊盘的数量相同，且数量均为数据输入/输出焊盘总数量的一半；
    其中，所述第一差分数据选通焊盘、所述第二差分数据选通焊盘和数据掩膜焊盘配置在所述第一焊盘子区域与所述第二焊盘子区域之间。
  5. 根据权利要求4所述的集成电路结构，其中，所述多个输入/输出电路模块包括：
    数据选通输入/输出电路模块、数据掩膜输入/输出电路模块和多个数据输入/输出电路模块。
  6. 根据权利要求5所述的集成电路结构，其中，所述电路区域包括：
    第一电路子区域和第二电路子区域，所述第一电路子区域与所述第二电路子区域包含的数据输入/输出电路模块的数量相同，且数量均为数据输入/输出电路模块总数量的一半；
    其中，所述数据选通输入/输出电路模块和所述数据掩膜输入/输出电路模块配置在所述第一电路子区域与所述第二电路子区域之间。
  7. 根据权利要求5所述的集成电路结构，其中，数据选通输入/输出电路模块分别与所述第一差分数据选通焊盘和所述第二差分数据选通焊盘连接。
  8. 根据权利要求1至7中任一项所述的集成电路结构，其中，相邻的所述输入/输出电路模块之间的距离小于距离阈值；
    其中，所述距离阈值基于所述焊盘区域沿所述目标方向的尺寸以及各所述输入/输出电路模块沿所述目标方向的尺寸而确定出。
  9. 根据权利要求1至7中任一项所述的集成电路结构，其中，各所述输入/输出电路模块所占区域沿所述目标方向的宽高比小于比例阈值。
  10. 一种存储器，包括如权利要求1至9中任一项所述的集成电路结构。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097883A (en) * 1997-07-08 2000-08-01 International Business Machines Corporation Dual state memory card having combined and single circuit operation
US6351405B1 (en) * 1999-09-16 2002-02-26 Samsung Electronics Co., Ltd. Pad for integrated circuit device which allows for multiple probing and reliable bonding and integrated circuit device including the pad
KR20040107244A (ko) * 2003-06-13 2004-12-20 삼성전자주식회사 반도체메모리장치의 전원 및 접지 배선구조
CN1819196A (zh) * 2005-01-27 2006-08-16 株式会社瑞萨科技 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路
CN101620877A (zh) * 2008-06-30 2010-01-06 海力士半导体有限公司 半导体存储装置
CN109891586A (zh) * 2016-11-04 2019-06-14 美光科技公司 与外部端子接线
CN210805230U (zh) * 2020-01-14 2020-06-19 长鑫存储技术有限公司 集成电路结构和存储器
CN210805229U (zh) * 2020-01-14 2020-06-19 长鑫存储技术(上海)有限公司 集成电路结构和存储器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097883A (en) * 1997-07-08 2000-08-01 International Business Machines Corporation Dual state memory card having combined and single circuit operation
US6351405B1 (en) * 1999-09-16 2002-02-26 Samsung Electronics Co., Ltd. Pad for integrated circuit device which allows for multiple probing and reliable bonding and integrated circuit device including the pad
KR20040107244A (ko) * 2003-06-13 2004-12-20 삼성전자주식회사 반도체메모리장치의 전원 및 접지 배선구조
CN1819196A (zh) * 2005-01-27 2006-08-16 株式会社瑞萨科技 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路
CN101620877A (zh) * 2008-06-30 2010-01-06 海力士半导体有限公司 半导体存储装置
CN109891586A (zh) * 2016-11-04 2019-06-14 美光科技公司 与外部端子接线
CN210805230U (zh) * 2020-01-14 2020-06-19 长鑫存储技术有限公司 集成电路结构和存储器
CN210805229U (zh) * 2020-01-14 2020-06-19 长鑫存储技术(上海)有限公司 集成电路结构和存储器

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