JP4991134B2 - 半導体装置およびその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
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- 238000002955 isolation Methods 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 29
- 229910052814 silicon oxide Inorganic materials 0.000 description 29
- 238000000034 method Methods 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
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- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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- 229910021334 nickel silicide Inorganic materials 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、本実施の形態によるLCDドライバの回路構成を示す概略図である。LCDドライバは、単結晶シリコンからなる半導体チップ1Aの主面に形成された入出力端子(ボンディングパッド)50、内部回路51および静電保護(ESD)回路52などによって構成されている。
前記実施の形態1では、静電保護回路52の抵抗素子ERを素子分離溝2の上部に配置したのに対し、本実施の形態では、図12および図13に示すように、抵抗素子ERをアクティブ領域(n型埋込み層3)上に配置する。一方、内部回路51の抵抗素子IRは、前記実施の形態1と同じように、アクティブ領域(n型埋込み層3)上に配置する。
図14に示すように、本実施の形態では、静電保護回路52の抵抗素子ERおよび内部回路51の抵抗素子IRをそれぞれ素子分離溝2の上部に配置する。また、抵抗素子ER、IRのそれぞれの下部の素子分離溝2には、複数のダミーアクティブ領域21を島状、格子状、またはマトリクス状に形成する。これにより、酸化シリコン膜が埋め込まれた素子分離溝2の上部に抵抗素子ER、IRを配置する場合に比べて、基板1の表面をより平坦化することができる。
1A 半導体チップ
2 素子分離溝
3 n型埋込み層
4 p型埋込み層
5 n型ウエル
6 p型ウエル
7 ゲート絶縁膜
8 ゲート電極
9 キャップ絶縁膜
10 n型半導体領域
11、12 ゲート絶縁膜
13、14 ゲート電極
16 サイドウォールスペーサ
17 n型半導体領域
18 p型半導体領域
20 シリサイド層
21 ダミーアクティブ領域
50 入出力端子(ボンディングパッド)
51 内部回路
52 静電保護回路
D1、D2 保護ダイオード
ER 抵抗素子
IR 抵抗素子
QHN 高耐圧nチャネル型MISFET
QHP 高耐圧pチャネル型MISFET
QMP 中耐圧pチャネル型MISFET
QLP 低耐圧pチャネル型MISFET
Claims (10)
- 半導体基板の主面の第1領域に形成された第1ゲート絶縁膜を有し、第1の電源電圧で動作する第1MISFET、前記半導体基板の主面の第2領域に形成され、前記第1ゲート絶縁膜よりも膜厚が大きい第2ゲート絶縁膜を有すると共に、前記第1の電源電圧よりも高い第2の電源電圧で動作する第2MISFET、および前記半導体基板の主面の第3領域に形成されたシリコン膜からなる第1抵抗素子を含む内部回路と、
前記半導体基板の主面の第4領域に形成されたシリコン膜からなる第2抵抗素子を含む静電保護回路と、
を有する半導体装置であって、
前記第1および第2抵抗素子のそれぞれの下部には、前記第2ゲート絶縁膜と同層の第1絶縁膜が形成されており、
前記第1抵抗素子の下部の前記半導体基板には、アクティブ領域が形成されており、
前記第2抵抗素子のエッジ部の下部の前記半導体基板には、第2絶縁膜が埋め込まれた素子分離溝が形成されていることを特徴とする半導体装置。 - 前記素子分離溝は、前記第2抵抗素子の下部の全域にわたって形成されていることを特徴とする請求項1記載の半導体装置。
- 前記第2抵抗素子の下部の前記半導体基板には、複数のダミーアクティブ領域がマトリクス状に配置されていることを特徴とする請求項1記載の半導体装置。
- 前記第1抵抗素子を構成する前記シリコン膜と、前記第2抵抗素子を構成する前記シリコン膜とは、互いに同層のシリコン膜であることを特徴とする請求項1記載の半導体装置。
- 前記第1抵抗素子を構成する前記シリコン膜と、前記第2抵抗素子を構成する前記シリコン膜とは、互いに異なる層のシリコン膜であることを特徴とする請求項1記載の半導体装置。
- 半導体基板の主面の第1領域に形成された第1ゲート絶縁膜を有し、第1の電源電圧で動作する第1MISFET、前記半導体基板の主面の第2領域に形成され、前記第1ゲート絶縁膜よりも膜厚が大きい第2ゲート絶縁膜を有すると共に、前記第1の電源電圧よりも高い第2の電源電圧で動作する第2MISFET、および前記半導体基板の主面の第3領域に形成されたシリコン膜からなる第1抵抗素子を含む内部回路と、
前記半導体基板の主面の第4領域に形成されたシリコン膜からなる第2抵抗素子を含む静電保護回路と、
を有する半導体装置の製造方法であって、
(a)前記半導体基板の主面上に前記第2ゲート絶縁膜を形成する工程と、
(b)前記第2ゲート絶縁膜をパターニングすることによって、前記半導体基板の主面の前記第2、第3および第4領域に、それぞれ前記第2ゲート絶縁膜を残す工程と、
(c)前記工程(b)の後、前記第2領域の前記第2ゲート絶縁膜上に前記第2MISFETのゲート電極を形成し、前記第3領域の前記第2ゲート絶縁膜上に前記第1抵抗素子を形成し、前記第4領域の前記第2ゲート絶縁膜上に前記第2抵抗素子を形成する工程と、
を含み、
前記第1抵抗素子は、アクティブ領域の上部に形成され、前記第2抵抗素子は、前記第2抵抗素子のエッジ部の下部が、絶縁膜が埋め込まれた素子分離溝の上部に形成されることを特徴とする半導体装置の製造方法。 - 前記工程(c)に先だって、前記半導体基板の主面の前記第1領域に前記第1ゲート絶縁膜を形成する工程を含み、
前記工程(c)において、前記半導体基板上に形成した第3シリコン膜をパターニングすることによって、前記第1MISFETのゲート電極と、前記第1および第2抵抗素子の一方とを同時に形成し、前記半導体基板上に形成した第4シリコン膜をパターニングすることによって、前記第2MISFETのゲート電極と、前記第1および第2抵抗素子の他方とを同時に形成することを特徴とする請求項6記載の半導体装置の製造方法。 - 前記第2抵抗素子は、絶縁膜が埋め込まれた素子分離溝とアクティブ領域とが混在する領域の上部に形成されることを特徴とする請求項6記載の半導体装置の製造方法。
- 前記第2抵抗素子が形成される領域の前記アクティブ領域は、マトリクス状に配置された複数のダミーアクティブ領域からなることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記素子分離溝は、前記第2抵抗素子の下部の全域にわたって形成されていることを特徴とする請求項7記載の半導体装置の製造方法。
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JP2005268135A JP4991134B2 (ja) | 2005-09-15 | 2005-09-15 | 半導体装置およびその製造方法 |
TW095125378A TWI395330B (zh) | 2005-09-15 | 2006-07-12 | Semiconductor device and manufacturing method thereof |
TW101145177A TW201312756A (zh) | 2005-09-15 | 2006-07-12 | 半導體裝置及其製造方法 |
US11/500,381 US7393737B2 (en) | 2005-09-15 | 2006-08-08 | Semiconductor device and a method of manufacturing the same |
CN2006101150853A CN1933157B (zh) | 2005-09-15 | 2006-08-23 | 半导体器件及其制造方法 |
KR1020060089494A KR101264433B1 (ko) | 2005-09-15 | 2006-09-15 | 반도체장치 및 그 제조방법 |
US12/116,193 US7759763B2 (en) | 2005-09-15 | 2008-05-06 | Semiconductor device and a method of manufacturing the same |
US12/813,144 US8324706B2 (en) | 2005-09-15 | 2010-06-10 | Semiconductor device and a method of manufacturing the same |
KR1020120127218A KR101287274B1 (ko) | 2005-09-15 | 2012-11-12 | 반도체장치 및 그 제조방법 |
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JP4991134B2 (ja) * | 2005-09-15 | 2012-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2008140922A (ja) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | 半導体装置 |
JP2008251812A (ja) * | 2007-03-30 | 2008-10-16 | Toshiba Corp | 半導体装置およびその製造方法 |
CN101673311B (zh) * | 2008-09-11 | 2011-05-11 | 北京同方微电子有限公司 | 一种优化混合信号芯片面积的方法 |
JP5367390B2 (ja) * | 2009-01-28 | 2013-12-11 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP5503208B2 (ja) | 2009-07-24 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2011054901A (ja) * | 2009-09-04 | 2011-03-17 | Panasonic Corp | 半導体装置及びその製造方法 |
JP5375497B2 (ja) * | 2009-10-01 | 2013-12-25 | トヨタ自動車株式会社 | 半導体装置、及び、半導体装置の製造方法 |
JP5135374B2 (ja) * | 2010-03-24 | 2013-02-06 | 株式会社東芝 | キャパシタ、集積装置、高周波切替装置及び電子機器 |
JP2012227206A (ja) * | 2011-04-15 | 2012-11-15 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
KR102148236B1 (ko) * | 2013-12-02 | 2020-08-26 | 에스케이하이닉스 주식회사 | 반도체 장치 |
CN105633018A (zh) * | 2014-11-03 | 2016-06-01 | 无锡华润上华半导体有限公司 | 集成电路制造方法 |
WO2016125490A1 (ja) * | 2015-02-03 | 2016-08-11 | 富士電機株式会社 | 半導体装置及びその製造方法 |
CN106298913B (zh) * | 2015-05-18 | 2019-11-08 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
JP2017041597A (ja) * | 2015-08-21 | 2017-02-23 | シナプティクス・ジャパン合同会社 | 半導体装置および半導体装置製造方法 |
CN105185779B (zh) * | 2015-09-01 | 2017-11-10 | 成都方舟微电子有限公司 | 高阈值电压功率mos芯片、器件及提高阈值电压的方法 |
US10340357B2 (en) * | 2017-09-25 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dishing prevention dummy structures for semiconductor devices |
DE102018112866B4 (de) | 2018-05-29 | 2020-07-02 | Infineon Technologies Ag | Halbleitervorrichtung mit elektrischem Widerstand |
JP7045271B2 (ja) * | 2018-06-28 | 2022-03-31 | エイブリック株式会社 | 半導体装置及び半導体チップ |
JP2020088142A (ja) * | 2018-11-26 | 2020-06-04 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子および電子機器 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55156370A (en) * | 1979-05-25 | 1980-12-05 | Hitachi Ltd | Manufacture of semiconductor device |
JP3257317B2 (ja) * | 1995-01-13 | 2002-02-18 | 富士電機株式会社 | 半導体装置の製造方法 |
US5665633A (en) * | 1995-04-06 | 1997-09-09 | Motorola, Inc. | Process for forming a semiconductor device having field isolation |
JP3262752B2 (ja) * | 1997-03-28 | 2002-03-04 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
US6218704B1 (en) * | 1997-05-07 | 2001-04-17 | International Business Machines Corporation | ESD protection structure and method |
JPH11251533A (ja) * | 1998-02-27 | 1999-09-17 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
US6365185B1 (en) | 1998-03-26 | 2002-04-02 | University Of Cincinnati | Self-destructing, controlled release peroral drug delivery system |
JP3799166B2 (ja) * | 1998-08-04 | 2006-07-19 | 松下電器産業株式会社 | Mos型半導体装置の製造方法 |
JP3413569B2 (ja) * | 1998-09-16 | 2003-06-03 | 株式会社日立製作所 | 絶縁ゲート型半導体装置およびその製造方法 |
FR2786407B1 (fr) | 1998-11-27 | 2001-02-16 | Roquette Freres | Composition de polyols concentree |
DE19936000A1 (de) * | 1999-07-30 | 2001-02-08 | Osram Opto Semiconductors Gmbh | UV-Photodetektor mit verbesserter Empfindlichkeit |
US6683345B1 (en) * | 1999-12-20 | 2004-01-27 | International Business Machines, Corp. | Semiconductor device and method for making the device having an electrically modulated conduction channel |
US6531745B1 (en) * | 1999-12-30 | 2003-03-11 | Intel Corporation | Electro static discharge protection n-well ballast resistor device |
US6462380B1 (en) * | 2000-01-21 | 2002-10-08 | Texas Instruments Incorporated | ESD protection circuit for advanced technologies |
US6384452B1 (en) * | 2000-07-17 | 2002-05-07 | Agere Systems Guardian Corp | Electrostatic discharge protection device with monolithically formed resistor-capacitor portion |
US6850397B2 (en) * | 2000-11-06 | 2005-02-01 | Sarnoff Corporation | Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation |
JP2002158278A (ja) | 2000-11-20 | 2002-05-31 | Hitachi Ltd | 半導体装置およびその製造方法ならびに設計方法 |
JP2002189487A (ja) * | 2000-12-20 | 2002-07-05 | Mitsubishi Electric Corp | 音声認識装置および音声認識方法 |
JP4982921B2 (ja) | 2001-03-05 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7005708B2 (en) * | 2001-06-14 | 2006-02-28 | Sarnoff Corporation | Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling |
JP2003023114A (ja) * | 2001-07-05 | 2003-01-24 | Fujitsu Ltd | 半導体集積回路装置およびその製造方法 |
KR100399350B1 (ko) * | 2001-08-09 | 2003-09-26 | 삼성전자주식회사 | 부유 트랩형 소자를 가지는 비휘발성 반도체 메모리 장치및 그 제조방법 |
US6723304B2 (en) | 2001-11-13 | 2004-04-20 | Noville, Inc. | Oral care compositions comprising diglycerol |
JP2003152102A (ja) * | 2001-11-15 | 2003-05-23 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3828419B2 (ja) * | 2001-12-25 | 2006-10-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7109533B2 (en) * | 2002-03-25 | 2006-09-19 | Nec Electronics Corporation | Electrostatic discharge protection device |
US20040253307A1 (en) | 2003-02-04 | 2004-12-16 | Brian Hague | Sugar-free oral transmucosal solid dosage forms and uses thereof |
JP2004363234A (ja) * | 2003-06-03 | 2004-12-24 | Renesas Technology Corp | 半導体装置の製造方法 |
US6853036B1 (en) * | 2003-08-06 | 2005-02-08 | Esd Pulse, Inc. | Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event |
JP2005183609A (ja) | 2003-12-18 | 2005-07-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US7285458B2 (en) * | 2004-02-11 | 2007-10-23 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an ESD protection circuit |
JP4854934B2 (ja) * | 2004-06-14 | 2012-01-18 | ルネサスエレクトロニクス株式会社 | 静電気放電保護素子 |
JP2006303110A (ja) * | 2005-04-19 | 2006-11-02 | Nec Electronics Corp | 半導体装置 |
JP5001522B2 (ja) * | 2005-04-20 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
JP4991134B2 (ja) * | 2005-09-15 | 2012-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7544545B2 (en) * | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
US8044457B2 (en) * | 2009-06-29 | 2011-10-25 | Analog Devices, Inc. | Transient over-voltage clamp |
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US8324706B2 (en) | 2012-12-04 |
KR20070031813A (ko) | 2007-03-20 |
CN1933157A (zh) | 2007-03-21 |
CN1933157B (zh) | 2010-07-14 |
US20070069326A1 (en) | 2007-03-29 |
JP2007081206A (ja) | 2007-03-29 |
TWI395330B (zh) | 2013-05-01 |
KR20120127706A (ko) | 2012-11-23 |
US7393737B2 (en) | 2008-07-01 |
KR101287274B1 (ko) | 2013-07-17 |
US20100244137A1 (en) | 2010-09-30 |
US7759763B2 (en) | 2010-07-20 |
TW201312756A (zh) | 2013-03-16 |
KR101264433B1 (ko) | 2013-05-14 |
US20080211029A1 (en) | 2008-09-04 |
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