JP7045271B2 - 半導体装置及び半導体チップ - Google Patents
半導体装置及び半導体チップ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 159
- 239000010408 film Substances 0.000 claims description 103
- 239000010409 thin film Substances 0.000 claims description 60
- 230000002093 peripheral effect Effects 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 56
- 238000000034 method Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000011345 viscous material Substances 0.000 description 1
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- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
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Description
以下に、第1の実施形態に係る半導体装置について説明する。
図1は、本発明の第1の実施形態を示す半導体装置100の模式平面図であり、一部の特徴的な部分を透視して示している。また、図2は、図1において半導体装置100をA-A’線に沿って切断した場合の模式断面図である。
図5は、第1の実施形態のブリーダー抵抗回路を搭載したボルテージディテクタ101aの模式回路ブロック図である。
以下に、第2の実施形態に係る半導体装置について説明する。
図7は、本発明の第2の実施形態を示す半導体装置200の模式断面図である。第2の実施形態の平面視における構成は図1と同様であり、図7の模式断面図は、図1のA-A’線に沿って切断した断面図に相当する。
以下に、第3の実施形態に係る半導体装置及び半導体集積回路装置について説明する。
図8(a)、(b)は、本発明の第3の実施形態を示す半導体装置300を搭載した半導体チップ301を、スクライブ領域302を挟んで半導体基板30上に搭載した場合の部分的な模式平面図であり、一部の特徴的な部分のみ示している。図8(a)、(b)の半導体基板30における位置は、それぞれ図10における領域440a、440bに相当する。また、図9は、図8(b)において半導体チップ301及びスクライブ領域302の1部をB-B’線に沿って切断した場合の模式断面図である。以下に第3の実施形態において、第1の実施形態に対して特徴的な部分を中心に説明する。
2 接地端子
3 出力端子
10、20、30、40 半導体基板
11、21、31 平坦領域
11a、31a 領域辺
11b、31b 領域面取り部
12、22、32 外周領域
13、23、33 薄膜抵抗素子
14 コンタクトホール
15a、15b、15c、15d 配線金属
16、26、36 ブリーダー抵抗回路
17、27、37 第1の絶縁膜
18、28、38 第2の絶縁膜
19、29、39 パッシベーション膜
27a 導電膜
27b 下地絶縁膜
91 基準電圧回路
92 電圧比較器
93 Pチャネル型トランジスタ
94 Nチャネル型トランジスタ
95 誤差増幅器
101、301、401 半導体チップ
301a チップ辺
301b チップ面取り部
102、302、402 スクライブ領域
400 高段差パターン
Claims (9)
- 半導体基板の表面に形成された第1の絶縁膜上の、平面視において領域辺と前記領域辺の間の領域面取り部とを有する外周形状の平坦領域と、
前記平坦領域を囲み、前記平坦領域と高さの異なる外周領域と、
前記平坦領域上に前記外周領域から所定の距離以上離れて形成された、相似形状もしくは同一形状を有する複数の半導体素子と、
前記複数の半導体素子上に形成された第2の絶縁膜と、
前記複数の半導体素子上の前記第2の絶縁膜に形成されたコンタクトホールと、
前記コンタクトホール上に形成され、前記複数の半導体素子を接続する配線金属と
を備えることを特徴とする半導体装置。 - 平面視における前記領域面取り部の形状が直線であり、前記領域辺と前記領域面取り部のなす内角が90度を越える角度であることを特徴とする請求項1に記載の半導体装置。
- 平面視における前記領域面取り部の形状が、前記外周領域に向かい凸形状をなす曲線であることを特徴とする請求項1に記載の半導体装置。
- 前記領域辺の形状が、前記外周領域に向かい凸形状をなす曲線であり、前記平坦領域の外周が円形または楕円形をなすことを特徴とする請求項3に記載の半導体装置。
- 前記平坦領域の下の前記半導体基板と前記第1の絶縁膜の間に、導電膜が形成されていることを特徴とする請求項2乃至4のいずれか一項に記載の半導体装置。
- 前記半導体素子が薄膜抵抗素子であり、前記半導体装置がブリーダー抵抗回路であることを特徴とする請求項2乃至4のいずれか一項に記載の半導体装置。
- 前記半導体基板に形成され、平面視においてスクライブ領域で区画されたチップ辺と前記チップ辺の間に設けられたチップ面取り部とを備え、
前記チップ辺が、対向する前記領域辺に対し、平行である方向に設けられていることを特徴とする請求項2に記載の半導体装置を備えた半導体チップ。 - 平面視における前記チップ面取り部の形状が直線であり、前記チップ辺と前記チップ面取り部のなす内角が90度を越える角度であることを特徴とする請求項7に記載の半導体チップ。
- 平面視における前記チップ面取り部の形状が前記スクライブ領域に向かい凸形状をなす曲線であることを特徴とする請求項7に記載の半導体チップ。
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JP2018123205A JP7045271B2 (ja) | 2018-06-28 | 2018-06-28 | 半導体装置及び半導体チップ |
US16/442,772 US11011480B2 (en) | 2018-06-28 | 2019-06-17 | Semiconductor device having a flat region with an outer peripheral shape including chamfer portions |
TW108120806A TWI794513B (zh) | 2018-06-28 | 2019-06-17 | 半導體裝置以及半導體晶片 |
KR1020190075051A KR20200001988A (ko) | 2018-06-28 | 2019-06-24 | 반도체 장치 및 반도체 칩 |
CN201910553907.3A CN110660789B (zh) | 2018-06-28 | 2019-06-25 | 半导体装置及半导体芯片 |
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JP (1) | JP7045271B2 (ja) |
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- 2019-06-24 KR KR1020190075051A patent/KR20200001988A/ko not_active Application Discontinuation
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JP2001044431A (ja) | 1999-05-27 | 2001-02-16 | Fuji Electric Co Ltd | 半導体装置 |
JP2008270720A (ja) | 2007-03-22 | 2008-11-06 | Fujitsu Microelectronics Ltd | 半導体装置及び半導体装置の製造方法 |
JP2010109233A (ja) | 2008-10-31 | 2010-05-13 | Renesas Technology Corp | 半導体装置 |
JP2010182954A (ja) | 2009-02-06 | 2010-08-19 | Seiko Instruments Inc | 半導体装置 |
JP2013512587A (ja) | 2009-12-01 | 2013-04-11 | クゥアルコム・インコーポレイテッド | 集積化されたパッシブ及びアクティブエレメントを伴ったインダクタに対する方法及び装置 |
WO2014199608A1 (ja) | 2013-06-14 | 2014-12-18 | 富士電機株式会社 | 半導体装置 |
JP2017092393A (ja) | 2015-11-16 | 2017-05-25 | 住友電工デバイス・イノベーション株式会社 | 電子装置 |
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TW202002239A (zh) | 2020-01-01 |
CN110660789B (zh) | 2023-09-12 |
US11011480B2 (en) | 2021-05-18 |
TWI794513B (zh) | 2023-03-01 |
JP2020004851A (ja) | 2020-01-09 |
CN110660789A (zh) | 2020-01-07 |
KR20200001988A (ko) | 2020-01-07 |
US20200006260A1 (en) | 2020-01-02 |
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