WO2023087154A1 - 一种芯片、芯片的制作方法及电子设备 - Google Patents

一种芯片、芯片的制作方法及电子设备 Download PDF

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Publication number
WO2023087154A1
WO2023087154A1 PCT/CN2021/131001 CN2021131001W WO2023087154A1 WO 2023087154 A1 WO2023087154 A1 WO 2023087154A1 CN 2021131001 W CN2021131001 W CN 2021131001W WO 2023087154 A1 WO2023087154 A1 WO 2023087154A1
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Prior art keywords
regions
strip
redundant
fin
region
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PCT/CN2021/131001
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English (en)
French (fr)
Inventor
杨磊
高健
吴艾瑞克
叶约翰
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华为技术有限公司
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Priority to CN202180099258.XA priority Critical patent/CN117480598A/zh
Priority to PCT/CN2021/131001 priority patent/WO2023087154A1/zh
Publication of WO2023087154A1 publication Critical patent/WO2023087154A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Definitions

  • the present application relates to the technical field of semiconductors, and in particular to a chip, a method for manufacturing the chip, and electronic equipment.
  • fin field effect transistor fin field effect transistor
  • FinFET fin field effect transistor
  • the fin field effect transistor includes a gate and a strip-shaped fin structure.
  • the gate surrounds the fin structure on three sides.
  • the gate can control the channel region through the top surface and two sides of the fin structure, thereby greatly improving the gate control capability and
  • the leakage current is significantly reduced, so that the fin field effect transistor has the advantages of strong gate control capability, small device size, and low power consumption.
  • the fins outside the active area need to be removed, so as to form the fin structure in the active area. Since the shape of the area other than the active area is generally more complicated, the process precision of removing the fin strips is low, which easily affects the shape of the fin structure in the active area. In addition, due to the removal of the fins in the area other than the active area, the process difference between the area outside the active area and the active area is relatively large, which makes the uniformity of the isolation dielectric layer formed subsequently poor, which affects the subsequent film The growth of the layer, and it is easy to cause uneven stress and lead to defects such as bending and dislocation of the fin structure. Therefore, the performance of the FinFET produced in the related art is poor.
  • Embodiments of the present application provide a chip, a method for manufacturing the chip, and an electronic device to solve the problem of poor performance of fin field effect transistors manufactured in the related art.
  • the embodiment of the present application provides a chip manufacturing method, the manufacturing method may include:
  • a substrate is provided; wherein, the surface of the substrate has: a plurality of active regions, a plurality of first strip-shaped regions extending along a first direction, a plurality of second strip-shaped regions extending along a second direction, and a plurality of redundant area.
  • the redundant area is located in an area other than the plurality of active areas, the plurality of first stripe areas, and the plurality of second stripe areas.
  • the first direction and the second direction cross each other, for example, the first direction and the second direction may be perpendicular to each other.
  • Each active area corresponds to at least one fin field effect transistor to be formed, and each active area is surrounded by an area formed by the first strip-shaped area and/or the second strip-shaped area, for example, when the active area is rectangular, The active area may be surrounded by two first stripe regions and two second stripe regions.
  • the active region can be set in a shape such as a rectangle or an "L" shape, which can be set according to the structure of the fin field effect transistor to be formed, and can be set according to the shape and shape of the active region on the substrate. Relative position to set the shape and position of the first bar area and the second bar area.
  • a plurality of fins are formed on the substrate.
  • the formed plurality of fins can approximately cover the surface of the substrate, that is, in each active region, each first stripe region, and each second stripe region. Fin rays are distributed in the region and each redundant region.
  • a plurality of fins extending along the first direction can be formed on the substrate, that is to say, the extending direction of each fin formed on the substrate is the same, and the extending direction of the fins is the same as that of the first strip. The area extends in the same direction.
  • the redundant fin structure wherein the fin structure is a part of the fin bars located in the active area, and the redundant fin structure is a part of the fin bars located in the redundant area.
  • the first strip-shaped regions extend along the first direction
  • the second strip-shaped regions extend along the second direction
  • each active area is surrounded by an area formed by the first strip-shaped area and/or the second strip-shaped area.
  • the redundant fin structure is separated from the fin structure in the active area by the first strip area and the second strip area, so the redundant fin structure will not affect the performance of the fin structure in the active area.
  • the uniformity of the subsequently formed isolation dielectric layer can be better, so that the quality of the subsequently formed film layers can be better, and the bending and dislocation of the fin structure caused by uneven stress can also be prevented. and other defects.
  • the shapes of the first strip-shaped area and the second strip-shaped area are relatively simple, the difficulty of the process of removing the fin strips is reduced, and the shape of the fin structure in the active area will not be affected. Therefore, the performance of the fin field effect transistor obtained by the manufacturing method of the chip provided in the embodiment of the present application is better.
  • each active region may include: at least two first edges extending along a first direction, and at least two second edges extending along a second direction.
  • Each first strip-shaped area is adjacent to a first edge of at least one active area
  • each second strip-shaped area is adjacent to a second edge of at least one active area. That is to say, the distance between the active area and the first strip-shaped area and the second strip-shaped area surrounding the active area is relatively close, so that after removing the fins in the first strip-shaped area and the second strip-shaped area,
  • the formed fin structure is basically located within the range of each active region, and the manufacturing precision of the fin structure is relatively high.
  • the active region and the first strip-shaped region and the second strip-shaped region surrounding the active region may be a certain gap between the active region and the first strip-shaped region and the second strip-shaped region surrounding the active region, which can avoid process error when removing the first strip-shaped region and the second strip-shaped region.
  • the shape of the fin structure in the active region is affected, thereby ensuring better performance of the fin structure formed in the active region.
  • the width of the first strip-shaped region in the second direction may be in the range of 0-2000 nm
  • the width of the second strip-shaped region in the first direction may be in the range of 0-2000 nm.
  • the removal of the fin rays in the plurality of first strip-shaped regions and the plurality of second strip-shaped regions may include:
  • a photolithography process and an etching process are used to remove the fin strips in the plurality of second strip-shaped regions.
  • the process accuracy can be improved by adjusting the conditions of the photolithography process such as the light source, exposure parameters, and etching process conditions and craft window.
  • fin rays in multiple first strip-shaped regions it is illustrated by removing fin rays in multiple first strip-shaped regions first, and then removing fin rays in multiple second strip-shaped regions.
  • multiple fin rays can also be removed first. the fin rays in a second strip-shaped region, and then remove the fin rays in a plurality of first strip-shaped regions, or, the fin rays in a plurality of first strip-shaped regions and a plurality of second strip-shaped regions can be Removal is not limited here.
  • forming a plurality of fins on the substrate may include:
  • a plurality of base shafts are formed on the substrate, and the extension direction of the base shafts is the same as the extension direction of the fins to be formed.
  • polysilicon material can be used to make the base shaft, and of course, other materials can also be used to make the base shaft, which is not limited here.
  • an entire basal axis film layer can be formed on the substrate, and then multiple basal axes located on the substrate can be obtained through an etching process.
  • the side wall layer is formed on the entire surface above the base axis.
  • the side wall layer can be made of silicon nitride material, and of course, other materials can also be used to make the side wall layer, which is not limited here.
  • the sidewall layer is etched to form a plurality of sidewalls on the sidewalls of the base shaft. In the actual process, the side wall layer can be etched on the entire surface. Due to the geometric effect of the side wall of the base shaft, the material at the side wall of the base shaft will not be etched away, thus forming a side wall at the side wall of the base shaft. wall.
  • the manufacturing process of the fin ray is illustrated by taking the above manufacturing process as an example. In the actual process, the fin ray may also be manufactured in other ways, which are not limited here.
  • the above may further include:
  • the fin structure in each active region is doped to form a source region, a drain region and a channel region in the fin structure; wherein the channel region may be located between the source region and the drain region.
  • the redundant fin structure in the redundant region can also be doped, so that there is no need to shield the redundant region, which simplifies the process difficulty.
  • An isolation dielectric layer is formed on the surface of the substrate, and the isolation dielectric layer is etched so that each fin structure protrudes from the isolation dielectric layer.
  • the isolation dielectric layer formed on the surface of the substrate can be arranged approximately on the entire surface, and after the isolation dielectric layer is etched, each redundant fin structure can also protrude from the isolation dielectric layer. Since there is a redundant fin structure in the redundant area except the active area, the first strip area and the second strip area, the uniformity of the formed isolation dielectric layer can be improved.
  • a gate dielectric layer is formed on the fin structure in each active region, and the gate dielectric layer can cover the channel region of the fin structure.
  • a gate is formed over the gate dielectric layer in each active region to obtain at least one FinFET. Since the uniformity of the isolation dielectric layer formed in the embodiment of the present application is better, the quality of the subsequently formed gate dielectric layer and gate is better, and the obtained fin field effect transistor has better performance.
  • a gate dielectric layer and a gate can also be formed on the redundant fin structure, so that the process difference between the active area and the redundant area is small.
  • a source electrically connected to the source region of the fin structure, and a drain electrically connected to the drain region of the fin structure may also be formed, thereby leading out the source region and the drain region of the fin structure. Since the redundant fin structure only serves to improve the uniformity of the subsequently formed isolation dielectric layer and does not need to be electrically connected to other components, the source region and the drain region in the redundant fin structure do not need to be drawn out.
  • the embodiment of the present application further provides a chip, which may include: a substrate, multiple fin structures and multiple redundant fin structures located on the substrate.
  • the surface of the substrate may have: a plurality of active regions, a plurality of first stripe regions extending along a first direction, a plurality of second stripe regions extending along a second direction, and a plurality of redundant regions, the redundant The regions may be located in regions other than the respective active regions, the plurality of first stripe regions, and the plurality of second stripe regions.
  • the first direction and the second direction cross each other, for example, the first direction and the second direction may be perpendicular to each other.
  • At least one fin structure is arranged in each active region above the substrate, and at least one redundant fin structure is arranged in each redundant region above the substrate. Each active area and the redundant area are separated by the first strip area and/or the second strip area.
  • each active region corresponds to at least one FinFET, that is, the chip includes at least one FinFET.
  • Each active area and the redundant area are separated by the first strip area and/or the second strip area, therefore, the fin structure in each active area is separated from the redundant fin structure in the redundant area, thus , the redundant fin structure does not affect the performance of the fin structure.
  • At least one redundant region has a shape of a polygon including at least five sides, that is, the polygon may include 5, 6 or more sides, and may be configured according to the substrate.
  • the position and shape of each active area that the bottom surface has is set.
  • the redundant area includes at least one sub-area surrounded by at least three sides of the polygon, and the sub-area is embedded in a gap between two adjacent active areas.
  • the sub-area may be: a closed area surrounded by at least three sides of the polygon and a certain line segment (or a polyline or a curve, etc.) located in the redundant area.
  • the space between two adjacent active regions can be fully utilized, and more redundant fin structures can be arranged near the active regions, thereby making the area of the redundant region larger and greatly improving the subsequent formation of fin structures.
  • the uniformity of the isolation dielectric layer further improves the quality of the subsequently formed film layer and makes the performance of the fin field effect transistor better.
  • At least one redundant region among the plurality of redundant regions on the surface of the substrate at least half surrounds one active region, and the redundant region may half surround one, two or more active regions. area; or, the redundant area may also completely surround at least one active area, which is not limited here. It can be understood that the redundant area at least half surrounds an active area means that the redundant area surrounds at least two sides of the active area.
  • At least one redundant area among the plurality of redundant areas on the surface of the substrate may be rectangular.
  • At least one active area among the plurality of active areas on the surface of the substrate is rectangular, and the active area and the redundant area are separated by two first strip-shaped areas and two second strip-shaped areas.
  • the active area can also be in other shapes.
  • the active area can be in an "L" shape, and the first strip-shaped area and the second strip-shaped area surrounding the active area can be set according to the shape of the active area. quantity and location.
  • the above-mentioned chip may further include: an isolation dielectric layer located on the substrate, and the fin structure protrudes from a side of the isolation dielectric layer facing away from the substrate.
  • the chip may further include: a gate dielectric layer and a gate located in the active region above the substrate. The gate is located on the side of the fin structure away from the substrate, and the gate dielectric layer is located between the fin structure and the gate.
  • the fin structure includes a source region, a drain region and a channel region, the channel region is located between the source region and the drain region, the gate covers the position of the channel region of the fin structure, and, on the top surface and two sides of the fin structure Both are surrounded by a gate, so the gate can control the channel region through the top surface and two sides of the fin structure, so that the fin field effect transistor has the advantages of strong gate control capability, small device size, and low power consumption.
  • the embodiment of the present application further provides an electronic device, and the electronic device may be a smart phone, a smart TV, a notebook computer, and the like.
  • the electronic device may include: any chip mentioned above, and a printed circuit board. Since the performance of the fin field effect transistor in the above chip is better, the performance of the electronic equipment including the above chip is also better.
  • FIG. 1 is a schematic structural view of a fin field effect transistor
  • Fig. 2 is the flow chart of the manufacturing method of the chip that the embodiment of the present application provides;
  • Fig. 3, Fig. 4, Fig. 5a, Fig. 5b and Fig. 6 are structural schematic diagrams corresponding to each step in the manufacturing method of the chip in the embodiment of the present application;
  • Fig. 7 to Fig. 12 are the manufacturing process flowcharts of the fin rays in the embodiment of the present application.
  • Figure 13a is a schematic structural view of a plurality of fins formed on a substrate
  • Figure 13b is a schematic cross-sectional view at the dotted line WW' in Figure 13a;
  • Fig. 14a is a structural schematic diagram during the process of removing fin rays in a plurality of first strip-shaped regions
  • Figure 14b is a schematic cross-sectional view at the dotted line PP' in Figure 14a;
  • Fig. 15a is a schematic structural view after removing fins in a plurality of first strip-shaped regions
  • Figure 15b is a schematic cross-sectional view at the dotted line PP' in Figure 15a;
  • Fig. 16a is a structural schematic diagram during the process of removing fin rays in a plurality of second strip-shaped regions
  • Figure 16b is a schematic cross-sectional view at the dotted line QQ' in Figure 16a;
  • Fig. 17a is a schematic structural view after removing fins in a plurality of second strip-shaped regions
  • Figure 17b is a schematic cross-sectional view at the dotted line QQ' in Figure 17a;
  • 18 to 20 are structural schematic diagrams corresponding to each step in the chip manufacturing method in the embodiment of the present application.
  • Embodiments of the present application provide a chip, a method for manufacturing the chip, and an electronic device.
  • the chip may be a central processing unit chip, an artificial intelligence chip, etc.
  • the chip may also be other types of chips, which are not limited here.
  • the chips provided in the embodiments of the present application may be applied to various types of electronic devices, for example, the electronic devices may be smart phones, smart TVs, notebook computers, and the like.
  • FIG. 1 is a schematic structural diagram of a fin field effect transistor.
  • the fin field effect transistor may include: a substrate 10 located on the substrate At least one fin structure 111 above 10, an isolation dielectric layer 12 located above the substrate 10, a gate 13 located on the side of the fin structure 111 away from the substrate 10, and a gate located between the fin structure 111 and the gate 13 polar dielectric layer 14.
  • the fin structures 111 are strip structures extending along the first direction F1, and each fin structure 111 is arranged along the second direction F2.
  • the first direction F1 and the second direction F2 cross each other, and the third direction F3 may be a direction perpendicular to the surface of the substrate 10 .
  • the fin field effect transistor includes three fin structures 111 as an example.
  • the fin field effect transistor may also include one, two, four or more fin structures 111, where The number of fin structures 111 is not limited.
  • the fin structure 111 protrudes from the side of the isolation dielectric layer 12 away from the substrate 10 .
  • the fin structure 111 includes a source region, a drain region and a channel region
  • the gate 13 covers the position of the channel region of the fin structure 11, and the top surface and both sides of the fin structure 111 are surrounded by the gate 13, thus , the gate 13 can control the channel region through the top surface and two side surfaces of the fin structure 111, so that the fin field effect transistor has the advantages of strong gate control capability, small device size, and low power consumption.
  • Fig. 2 is a flow chart of the chip manufacturing method provided in the embodiment of the present application
  • Fig. 3, Fig. 4, Fig. 5a, Fig. 5b and Fig. 6 are structural schematic diagrams corresponding to each step in the chip manufacturing method in the embodiment of the present application.
  • the chip manufacturing method provided by the embodiment of the present application may include:
  • the surface of the substrate 10 has: a plurality of active regions (for example, the surface of the substrate 10 in FIG. 3 has active regions A1-A7), a plurality of first strip-shaped regions T1 extending along the first direction F1 , a plurality of second stripe regions T2 extending along the second direction F2, and a plurality of redundant regions (for example, the surface of the substrate 10 in FIG. 3 has redundant regions C1-C3).
  • the redundant regions C1 - C3 are located in regions other than the plurality of active regions, the plurality of first stripe regions T1 , and the plurality of second stripe regions T2 .
  • the first direction F1 and the second direction F2 cross each other, for example, the first direction F1 and the second direction F2 may be perpendicular to each other.
  • Each active area corresponds to at least one fin field effect transistor to be formed, and each active area is surrounded by the area formed by the first strip-shaped area T1 and/or the second strip-shaped area T2, for example, in FIG. 3, the active area
  • the areas A1 , A2 , A3 , A4 , A6 and A7 are surrounded by an area formed by two first strip-shaped areas T1 and two second strip-shaped areas T2 .
  • At least two adjacent active regions may share the first strip-shaped region T1 or the second strip-shaped region T2.
  • the active area A2 and the active area A3 share the same second strip-shaped area T2
  • the active area A1 and the active area A4 share the same second strip-shaped area T2
  • the active area A5 and the active area A5 share the same second strip-shaped area T2.
  • the source regions A6 share the same second stripe region T2.
  • at least two active regions whose edges are substantially aligned may share the first strip-shaped region T1 or the second strip-shaped region T2. For example, in FIG.
  • active region A1, active region A5, and active region A6 share the same A first strip-shaped region T1
  • the active region A3 and the active region A7 may share the same first strip-shaped region T.
  • the active regions A1, A2, A3, A4, A6 and A7 are rectangles, and the active region A5 is an "L" shape as an example.
  • the active regions can also be For other shapes, it can be set according to the structure of the fin field effect transistor to be formed, and, according to the shape and relative position of the first active region on the substrate 10, a first strip-shaped region T1 and a second strip-shaped region T1 can be set. The shape and position of the shaped area T2.
  • each Fins 11 are distributed in the first strip region T1 , in each of the second strip regions T2 , and in the redundant regions C1 - C3 .
  • the fin structure 111 is a partial fin ray located in the active area
  • the redundant fin structure 112 is a partial fin ray located in the redundant area.
  • each active area includes at least one strip-shaped fin structure 111 , and there are multiple redundant fin structures 112 in the redundant areas C1 - C3 outside each active area. Moreover, since the fins in the first and second strips around the active region are removed, the formed fin structure 111 is separated from the redundant fin structure 112 , thus, the formed redundant fin structure 112 The performance of the fin structure 111 will not be affected.
  • At least one redundant region is in the shape of a polygon including at least five sides, and the edges of the redundant region are embedded in the gap between two adjacent active regions, for example,
  • the redundant area C1 is a polygon including 16 sides, and the edges of the redundant area C1 are embedded in the gap between the active area A4 and the active area A5, so that the area of the redundant area is relatively large and the active area can be made
  • There are more redundant fin structures in the vicinity which can greatly improve the uniformity of the isolation dielectric layer formed subsequently, so that the performance of the formed fin field effect transistor is better.
  • the first strip-shaped regions extend along the first direction
  • the second strip-shaped regions extend along the second direction
  • each active area is surrounded by an area formed by the first strip-shaped area and/or the second strip-shaped area.
  • the redundant fin structure is separated from the fin structure in the active area by the first strip area and the second strip area, so the redundant fin structure will not affect the performance of the fin structure in the active area.
  • the uniformity of the subsequently formed isolation dielectric layer can be better, so that the quality of the subsequently formed film layers can be better, and the bending and dislocation of the fin structure caused by uneven stress can also be prevented. and other defects.
  • the shapes of the first strip-shaped area and the second strip-shaped area are relatively simple, the difficulty of the process of removing the fin strips is reduced, and the shape of the fin structure in the active area will not be affected. Therefore, the performance of the fin field effect transistor obtained by the manufacturing method of the chip provided in the embodiment of the present application is better.
  • the above step S202 may include: referring to FIG. 4 , forming a plurality of fins 11 extending along the first direction F1 on the substrate 10 . That is to say, the extending direction of each fin 11 formed on the substrate 10 is consistent, and the extending direction of the fin 11 is consistent with the extending direction of the first strip region T1 .
  • it is easier to remove the fins 11 in the first strip region T1 and the second strip region T2 and the process precision of removing the fins 11 is higher. Therefore, removing the first strip region T1 and the second strip region T2
  • the fin 11 in the second strip region T2 will not affect the shape of the fin structure in the active region, so that the fin field effect transistor formed in the active region has better performance.
  • each active area may include: at least two first edges a extending along the first direction F1, and F2 extends at least two second edges b.
  • Each first strip-shaped region T1 is adjacent to a first edge a of at least one active region
  • each second strip-shaped region T2 is adjacent to a second edge b of at least one active region. That is to say, the distance between the active region and the first strip-shaped region T1 and the second strip-shaped region T2 surrounding the active region is relatively close, so that the After the fin ray, the formed fin structure is basically located within the range of each active region, and the manufacturing precision of the fin structure is relatively high.
  • the active region and the first strip-shaped region T1 and the second strip-shaped region T2 surrounding the active region may be a certain gap between the active region and the first strip-shaped region T1 and the second strip-shaped region T2 surrounding the active region, which can avoid process error when removing the first strip-shaped region T1 and the second strip-shaped region T1.
  • the shape of the fin structure in the active area is affected during the process of forming the fins in the strip-shaped area T2, thereby ensuring better performance of the fin structure formed in the active area.
  • the width d1 of the first strip-shaped region T1 in the second direction F2 may be in the range of 0-2000 nm, and the width d2 of the second strip-shaped region T2 in the first direction F1 may be In the range of 0-2000nm.
  • the width of the first strip area and the second strip area By reasonably setting the widths of the first strip area and the second strip area, the size of the active area, the redundant area other than the first strip area and the second strip area can be controlled, and the first strip area can be made
  • the width of the region T1 and the second strip-shaped region T2 is relatively narrow, so that the area of the fin strips removed in step S203 is small, and then the area of the formed redundant fin structure can be made larger, so that the area outside each active region
  • the process difference with the active region is small, the effect of optimizing the process can be achieved, and the performance of the formed fin field effect transistor is guaranteed to be better.
  • Fig. 7 to Fig. 12 are the flow charts of the manufacturing process of fin rays in the embodiment of the present application.
  • the above step S202 may include:
  • a plurality of base shafts 15 are formed on the substrate 10, and the extension direction of the base shafts 15 is the same as the extension direction of the fins to be formed, that is, the direction perpendicular to the paper surface in FIG. 7 can be the above-mentioned first direction , the horizontal direction in the figure may be the above-mentioned second direction F2, the vertical direction in the figure may be the third direction F3, and the third direction F3 may be a direction perpendicular to the surface of the substrate 10.
  • polysilicon material can be used to make the base shaft 15 , of course, other materials can also be used to make the base shaft 15 , which is not limited here.
  • an entire basal axis film layer can be formed on the substrate 10 , and then a plurality of basal axes 15 located on the substrate 10 can be obtained through an etching process.
  • the side wall layer 16 is formed on the entire surface of the base shaft 15.
  • the side wall layer 16 can be made of silicon nitride material, and of course, other materials can also be used to make the side wall layer 16.
  • the sidewall layer 16 is etched, referring to FIG. 9 , to form a plurality of sidewalls 161 located on the sidewall of the base shaft 15 .
  • the entire surface of the side wall layer can be etched. Due to the geometric effect of the side wall of the base shaft 15, the material at the side wall of the base shaft 15 will not be etched away, so that the side wall of the base shaft 15 side walls 161 are formed.
  • a plurality of base axes are removed by an etching process to obtain the structure shown in FIG. 10 .
  • the substrate 10 is etched to obtain the pattern of a plurality of fin bars 11 .
  • multiple sidewalls are removed to obtain multiple fins 11 .
  • the manufacturing process shown in Figure 7 to Figure 12 is taken as an example to illustrate the manufacturing process of fin rays. In the actual process, other methods can also be used to manufacture fin rays, which are not limited here. .
  • Figure 13a is a schematic structural view of a plurality of fins formed on the substrate
  • Figure 13b is a schematic cross-sectional view at the dotted line WW' in Figure 13a, as shown in Figure 13a and Figure 13b
  • the substrate 10 A plurality of fins 11 extending along the first direction F1 are formed on it.
  • it may further include: forming a buffer layer 17 on the fin 11 , and forming a protection layer 18 on the buffer layer 17 .
  • Fig. 14a is a structural schematic diagram during the process of removing fin rays in multiple first strip-shaped regions
  • Fig. 14b is a schematic cross-sectional view at the dotted line PP' in Fig. 14a
  • Fig. 15a is a schematic diagram of removing fin rays in multiple first strip-shaped regions
  • Figure 15b is a schematic cross-sectional view at the dotted line PP' in Figure 15a
  • Fig. 16a is a structural schematic view during the process of removing fin rays in multiple second strip-shaped regions
  • Fig. 16b is a schematic cross-sectional view at the dotted line QQ' in Fig. 16a.
  • FIG. 17a is a schematic structural view after removing the fins in multiple second strip-shaped regions
  • FIG. 17b is a schematic cross-sectional view at the dotted line QQ' in FIG. 17a.
  • a photolithography process and an etching process may be used to remove the fin bars 11 in the plurality of first bar-shaped regions T1.
  • a photoresist layer (not shown) can be formed on the entire surface of the protective layer 18, and the photoresist layer in the plurality of first strip-shaped regions T1 is removed by exposure and development processes, so that the light
  • the resist layer protects regions other than the plurality of first strip regions T1, and then, an etching process is used to remove the fin bars 11 in the plurality of first strip regions T1, and then the remaining photoresist layer is removed.
  • the structures shown in FIG. 15a and FIG. 15b are obtained.
  • a photolithography process and an etching process may be used to remove the fin bars 11 in the plurality of second bar-shaped regions T2.
  • a photoresist layer (not shown) can be formed on the entire surface of the protective layer 18, and the photoresist layer in the plurality of second strip-shaped regions T2 is removed by exposure and development processes, so that the light
  • the resist layer protects the regions except the plurality of second strip regions T2, and then, the fin bars 11 in the plurality of second strip regions T2 are removed by an etching process, and then the remaining photoresist layer is removed.
  • the structure shown in Figure 17a and Figure 17b is obtained, as shown in Figure 17a and Figure 17b, the plurality of first strip-shaped regions T1 and the plurality of second strip-shaped regions T1 are removed.
  • fin structures 111 are formed in the active regions A1-A7, and redundant fin structures 112 are formed in the redundant regions C1-C3.
  • the process accuracy can be improved by adjusting the conditions of the photolithography process such as the light source, exposure parameters, and etching process conditions and craft window.
  • fin rays in multiple first strip-shaped regions it is illustrated by removing fin rays in multiple first strip-shaped regions first, and then removing fin rays in multiple second strip-shaped regions.
  • multiple fin rays can also be removed first. the fin rays in a second strip-shaped region, and then remove the fin rays in a plurality of first strip-shaped regions, or, the fin rays in a plurality of first strip-shaped regions and a plurality of second strip-shaped regions can be Removal is not limited here.
  • step S203 is schematic structural diagrams corresponding to each step in the chip manufacturing method in the embodiment of the present application.
  • it may further include:
  • the redundant fin structure in the redundant region can also be doped, so that there is no need to shield the redundant region, which simplifies the process difficulty.
  • an isolation dielectric layer 12 is formed on the surface of the substrate 10 , and the isolation dielectric layer 12 is etched so that each fin structure 11 protrudes from the isolation dielectric layer 12 .
  • the isolation dielectric layer 12 formed on the surface of the substrate 10 can be arranged on the entire surface. After the isolation dielectric layer 12 is etched, each redundant fin structure can also protrude from the isolation dielectric layer 12 . Since there is a redundant fin structure in the redundant area except the active area, the first strip area and the second strip area, the uniformity of the formed isolation dielectric layer 12 can be better.
  • a gate dielectric layer 14 is formed on the fin structure 11 in each active region, and the gate dielectric layer 14 may cover the channel region of the fin structure 11 .
  • a gate 13 is formed on the gate dielectric layer 14 in each active region to obtain at least one FinFET as shown in FIG. 1 . Since the uniformity of the isolation dielectric layer 12 formed in the embodiment of the present application is better, the quality of the subsequently formed gate dielectric layer 14 and gate 13 is better, and the obtained fin field effect transistor has better performance.
  • the gate dielectric layer 14 and the gate 13 can also be formed on the redundant fin structure, so that the process difference between the active area and the redundant area is small.
  • a source electrically connected to the source region of the fin structure, and a drain electrically connected to the drain region of the fin structure may also be formed, thereby leading out the source region and the drain region of the fin structure. Since the redundant fin structure only serves to improve the uniformity of the subsequently formed isolation dielectric layer and does not need to be electrically connected to other components, the source region and the drain region in the redundant fin structure do not need to be drawn out.
  • the embodiment of the present application also provides a chip, which may be various types of chips such as a central processing unit chip and an artificial intelligence chip.
  • the chip can be manufactured by any of the above-mentioned manufacturing methods.
  • the chip may include: a substrate 10 , a plurality of fin structures 111 and a plurality of redundant fin structures 112 located on the substrate 10 .
  • the surface of the substrate 10 may have: a plurality of active regions (for example, the surface of the substrate 10 in FIG. A plurality of second strip-shaped regions T2 extending in the direction F2, and a plurality of redundant regions (for example, the surface of the substrate 10 in FIG. region, the plurality of first strip-shaped regions T1 and the plurality of second strip-shaped regions T2.
  • the first direction F1 and the second direction F2 cross each other, for example, the first direction F1 and the second direction F2 may be perpendicular to each other.
  • Each active area on the substrate 10 is provided with at least one fin structure 111, and each redundant area on the substrate 10 is provided with at least one redundant fin structure 112, and each active area and redundant The regions are separated by the first stripe region T1 and/or the second stripe region T2.
  • each active region corresponds to at least one FinFET, that is, the chip includes at least one FinFET.
  • Each active area and the redundant area are separated by the first strip-shaped area T1 and/or the second strip-shaped area T2, thus, the fin structure 111 in each active area and the redundant fin structure 112 in the redundant area Separately arranged, thus, the redundant fin structure will not affect the performance of the fin structure.
  • At least one redundant region has a shape of a polygon including at least five sides, that is, the polygon may include 5, 6 or more sides, and may be configured according to the substrate.
  • the position and shape of each active area that the bottom surface has is set.
  • the redundant area includes at least one sub-area surrounded by at least three sides of the polygon, and the sub-area is embedded in a gap between two adjacent active areas.
  • the sub-area may be: a closed area surrounded by at least three sides of the polygon and a certain line segment (or a polyline or a curve, etc.) located in the redundant area.
  • FIG. 5b is a partially enlarged schematic diagram of FIG. 5a.
  • the redundant area C1 in FIG. 5a is a polygon including 16 sides.
  • the redundant area C1 may include a sub-area C11 and a sub-area C12.
  • the sub-area C11 may be a closed area enclosed by the sides x1, x2 and x3 of the redundant area C1 and the line segment y1 in the redundant area C1, and the sub-area C11 is embedded in the gap between the active areas A4 and A5.
  • the sub-region C12 may be a closed region surrounded by the sides x4, x5, x6 and x7 of the redundant region C1 and the line segment y2 located in the redundant region C1, and the sub-region C12 is embedded in the gap between the active regions A2, A1 and A4 middle.
  • the space between two adjacent active regions can be fully utilized, and more redundant fin structures can be arranged near the active regions, thereby making the area of the redundant region larger and greatly improving the subsequent formation of fin structures.
  • the uniformity of the isolation dielectric layer further improves the quality of the subsequently formed film layer and makes the performance of the fin field effect transistor better.
  • At least one redundant region among the plurality of redundant regions on the surface of the substrate at least half surrounds an active region.
  • the redundant region C1 half surrounds the active regions A4, A5 and A7
  • the redundant area may also half surround one, two or more active areas, or the redundant area may fully surround at least one active area, which is not limited here. It can be understood that the redundant area at least half surrounds an active area means that the redundant area surrounds at least two sides of the active area.
  • At least one of the redundant regions on the surface of the substrate may be rectangular, for example, the redundant regions C2 and C3 in FIG. 5a are rectangular.
  • At least one active region among the plurality of active regions on the surface of the substrate 10 is a rectangle (for example, the active region A1 in FIG. 5a is a rectangle), and the active region and the redundant The remainder area is separated by two first stripe regions T1 and two second stripe regions T2.
  • the active area can also be in other shapes.
  • the chip may further include: an isolation dielectric layer 12 on the substrate 10 , and the fin structure 111 protrudes from the side of the isolation dielectric layer 12 away from the substrate 10 .
  • the chip may further include: a gate dielectric layer 14 and a gate 13 located in the active region above the substrate 10, the gate 13 is located on the side of the fin structure 111 away from the substrate 10, and the gate dielectric layer 14 Located between the fin structure 111 and the gate 13 .
  • the fin structure 111 includes a source region, a drain region and a channel region, the channel region is located between the source region and the drain region, the gate 13 covers the position of the channel region of the fin structure 11, and, on the top surface of the fin structure 111 The gate 13 is surrounded by the gate 13 and the two sides, and thus the gate 13 can control the channel region through the top surface and two sides of the fin structure 111, so that the fin field effect transistor has strong gate control ability, small device volume, high performance Advantages of low consumption.
  • an embodiment of the present application also provides an electronic device, which may be a smart phone, a smart TV, a notebook computer, and the like.
  • the electronic device may include: any chip mentioned above, and a printed circuit board. Since the performance of the fin field effect transistor in the above chip is better, the performance of the electronic equipment including the above chip is also better.

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Abstract

本申请提供一种芯片、芯片的制作方法及电子设备，该芯片的制作方法包括：提供一衬底；其中，该衬底的表面具有：多个有源区域，沿第一方向延伸的多个第一条形区域，沿第二方向延伸的多个第二条形区域，以及多个冗余区域；每一个有源区域对应至少一个将要形成的鳍式场效应晶体管，每一个有源区域被第一条形区域和/或第二条形区域构成的区域围绕；在衬底上形成多个鳍条；去除多个第一条形区域和多个第二条形区域内的鳍条，以在每一个有源区域内形成鳍式场效应晶体管的鳍结构，以及每一个冗余区域内形成冗余鳍结构。通过形成冗余鳍结构可以使后续形成的隔离介质层的均匀性较好，使得到的鳍式场效应晶体管的性能较好。

Description

一种芯片、芯片的制作方法及电子设备 技术领域
本申请涉及半导体技术领域，特别涉及一种芯片、芯片的制作方法及电子设备。
背景技术
随着电子技术的不断发展，鳍式场效应晶体管(fin field effect transistor，FinFET)作为一种新兴的场效应晶体管，已经被广泛应用于各类芯片中。鳍式场效应晶体管包括栅极和条形的鳍结构，栅极三面围绕鳍结构，栅极可以通过鳍结构的顶面和两个侧面控制沟道区，从而，能够大幅提升栅控能力，并明显降低漏电流，使得鳍式场效应晶体管具有栅控能力强、器件体积小、功耗低等优点。
在相关技术中，鳍式场效应晶体管的制作过程中，在衬底上形成多个鳍条后，需要去除有源区域以外的鳍条，以在有源区域内形成鳍结构。由于有源区域以外的区域的形状一般比较复杂，因而，去除鳍条的工艺精度较低，容易影响有源区域中的鳍结构的形状。此外，由于有源区域以外的区域中的鳍条被去除，导致有源区域以外的区域与有源区域的工艺差异较大，使得后续形成的隔离介质层的均匀性较差，进而影响后续膜层的生长，并且，容易引起应力不均而导致鳍结构出现弯曲及错位等缺陷。因此，相关技术中制作得到的鳍式场效应晶体管的性能较差。
发明内容
本申请实施例提供了一种芯片、芯片的制作方法及电子设备，用以解决相关技术中制作的鳍式场效应晶体管的性能较差的问题。
第一方面，本申请实施例提供了一种芯片的制作方法，该制作方法可以包括：
提供一衬底；其中，该衬底的表面具有：多个有源区域，沿第一方向延伸的多个第一条形区域，沿第二方向延伸的多个第二条形区域，以及多个冗余区域。冗余区域位于除多个有源区域、多个第一条形区域、多个第二条形区域外的区域内。第一方向与第二方向相互交叉，例如第一方向与第二方向可以相互垂直。每一个有源区域对应至少一个将要形成的鳍式场效应晶体管，每一个有源区域被第一条形区域和/或第二条形区域构成的区域围绕，例如，有源区域为矩形时，有源区域可以被两个第一条形区域和两个第二条形区域围绕。在实际应用中，可以将有源区域设置为矩形、“L”形等形状，可以根据将要形成的鳍式场效应晶体管的结构进行设置，并且，可以根据衬底上个有源区域的形状和相对位置，来设置个第一条形区域和第二条形区域的形状和位置。
然后，在衬底上形成多个鳍条，可选地，形成的多个鳍条可以近似铺满衬底的表面，即在各有源区域、各第一条形区域、各第二条形区域，以及各冗余区域内均分布有鳍条。在具体实施时，可以在衬底上形成沿第一方向延伸的多个鳍条，也就是说，衬底上形成的各鳍条的延伸方向一致，且鳍条的延伸方向与第一条形区域的延伸方向一致。
之后，去除多个第一条形区域和多个第二条形区域内的鳍条，以在每一个有源区域内形成鳍式场效应晶体管的鳍结构，以及在每一个冗余区域内形成冗余鳍结构，其中，鳍结构为位于有源区域内的部分鳍条，冗余鳍结构为位于冗余区域内的部分鳍条。
本申请实施例提供的芯片的制作方法，通过设置多个第一条形区域和多个第二条形区域，第一条形区域沿第一方向延伸，第二条形区域沿第二方向延伸，且每一个有源区域被第一条形区域和/或第二条形区域构成的区域围绕。这样，去除多个第一条形区域和多个第二条形区域内的鳍条后，可以在每一个有源区域内形成鳍式场效应晶体管的鳍结构，并且，可以在除有源区域、第一条形区域和第二条形区域以外的冗余区域内形成冗余鳍结构。冗余鳍结构通过第一条形区域和第二条形区域与有源区域内的鳍结构分隔，因而冗余鳍结构不会影响有源区域内鳍结构的性能。而且，通过设置冗余鳍结构可以使后续形成的隔离介质层的均匀性较好，从而，可以使后续形成的膜层的质量较好，也可以防止由于应力不均导致的鳍结构弯曲及错位等缺陷。此外，第一条形区域和第二条形区域的形状较简单，去除鳍条的工艺的难度降低，不会影响有源区域中鳍结构的形状。因此，本申请实施例提供的芯片的制作方法得到的鳍式场效应晶体管的性能较好。
在本申请实施例中，每一个有源区域可以包括：沿第一方向延伸的至少两个第一边缘，以及沿第二方向延伸的至少两个第二边缘。每一个第一条形区域与至少一个有源区域的第一边缘相邻，每一个第二条形区域与至少一个有源区域的第二边缘相邻。也就是说，有源区域与围绕该有源区域的第一条形区域和第二条形区域的距离较近，这样，去除第一条形区域和第二条形区域内的鳍条后，形成的鳍结构基本位于各有源区域的范围内，鳍结构的制作精度较高。并且，有源区域与围绕该有源区域的第一条形区域和第二条形区域之间可以具有一定的间隙，可以避免由于工艺误差，在去除第一条形区域和第二条形区域内的鳍条的过程中，影响有源区域内的鳍结构的形状，从而，可以保证形成于有源区域内的鳍结构的性能较好。
在一种可能的实现方式中，第一条形区域在第二方向上的宽度可以在0～2000nm的范围内，第二条形区域在第一方向上的宽度在0～2000nm的范围内。这样，通过合理设置第一条形区域和第二条形区域的宽度，可以控制有源区域、第一条形区域和第二条形区域以外的冗余区域的大小，可以使第一条形区域和第二条形区域的宽度较窄，使得去除的鳍条的面积较小，进而，可以使形成的冗余鳍结构的面积较大，使各有源区域外的区域与有源区域的工艺差异较小，能够达到优化工艺的效果，保证形成的鳍式场效应晶体管的性能较好。
在一种可能的实现方式中，上述去除多个第一条形区域和多个第二条形区域内的鳍条，可以包括：
采用光刻工艺和刻蚀工艺，去除多个第一条形区域内的鳍条；
采用光刻工艺和刻蚀工艺，去除多个第二条形区域内的鳍条。
在实际工艺过程中，在去除第一条形区域或第二条形区域中的鳍条的过程中，可以通过调节光源、曝光参数等光刻工艺的条件以及刻蚀工艺条件，来提高工艺精度和工艺窗口。
本申请实施例中，以先去除多个第一条形区域中的鳍条，再去除多个第二条形区域中的鳍条为例进行示意，在实际工艺过程中，也可以先去除多个第二条形区域中的鳍条，再去除多个第一条形区域中的鳍条，或者，也可以将多个第一条形区域和多个第二条形区域中的鳍条一起去除，此处不做限定。
在一种可能的实现方式中，上述在衬底上形成多个鳍条，可以包括：
在衬底上形成多个基轴，基轴的延伸方向与将要形成的鳍条的延伸方向相同。可选地，可以采用多晶硅材料制作基轴，当然，也可以采用其他材料制作基轴，此处不做限定。在 实际工艺过程中，可以在衬底之上形成整面的基轴膜层，然后通过刻蚀工艺得到位于衬底之上的多个基轴。
在基轴之上整面形成侧墙层，在具体实施时，可以采用氮化硅材料制作侧墙层，当然，也可以采用其他材料制作侧墙层，此处不做限定。之后，对侧墙层进行刻蚀，以形成位于基轴的侧壁处的多个侧墙。在实际工艺过程中，可以对侧墙层进行整面刻蚀，由于基轴侧壁的几何效应，基轴侧壁处的材料不会被刻蚀掉，从而在基轴的侧壁处形成侧墙。
采用刻蚀工艺去除多个基轴；
以多个侧墙为遮挡，对衬底进行刻蚀，以得到多个鳍条的图形；
去除多个侧墙，得到多个鳍条。
本申请实施例中，以上述制作流程为例，对鳍条的制作过程进行举例说明，在实际工艺过程中，也可以采用其他方式制作鳍条，此处不做限定。
在本申请的一些实施例中，上述在形成鳍式场效应晶体管的鳍结构之后，还可以包括：
对每一个有源区域内的鳍结构进行掺杂处理，以在鳍结构中形成源区、漏区和沟道区；其中，沟道区可以位于源区和漏区之间。在对有源区域内的鳍结构进行掺杂的工艺过程中，也可以对冗余区域中的冗余鳍结构进行掺杂，从而无需对冗余区域进行遮挡，简化工艺难度。
在衬底的表面形成隔离介质层，并刻蚀隔离介质层，以使每一个鳍结构凸出于隔离介质层。本申请实施例中，在衬底表面形成的隔离介质层可以近似整面设置，对隔离介质层进行刻蚀后，还可以使每一个冗余鳍结构凸出于隔离介质层。由于在除有源区域、第一条形区域和第二条形区域以外的冗余区域内具有冗余鳍结构，可以使形成的隔离介质层的均匀性较好。
在每一个有源区域内的鳍结构之上形成栅极介质层，栅极介质层可以覆盖鳍结构的沟道区。
在每一个有源区域内的栅极介质层之上形成栅极，以得到至少一个鳍式场效应晶体管。由于本申请实施例中形成的隔离介质层的均匀性较好，因而，后续形成的栅极介质层和栅极的质量较好，得到的鳍式场效应晶体管的性能较好。
在实际工艺过程中，也可以在冗余鳍结构之上形成栅极介质层和栅极，从而使有源区域与冗余区域内的工艺差异较小。此外，在掺杂工艺之后，还可以形成与鳍结构的源区电连接的源极，以及形成与鳍结构的漏区电连接的漏极，从而将鳍结构的源区和漏区引出。由于冗余鳍结构仅起到使后续形成的隔离介质层的均匀性较好的作用，无需与其他部件电连接，因而，冗余鳍结构中的源区和漏区无需引出。
第二方面，本申请实施例还提供了一种芯片，该芯片可以包括：衬底，位于衬底之上的多个鳍结构和多个冗余鳍结构。衬底的表面可以具有：多个有源区域，沿第一方向延伸的多个第一条形区域，沿第二方向延伸的多个第二条形区域，以及多个冗余区域，冗余区域可以位于除各有源区域、多个第一条形区域和多个第二条形区域以外的区域内。其中，第一方向与第二方向相互交叉，例如第一方向与第二方向可以相互垂直。衬底之上的每一个有源区域内设有至少一个鳍结构，衬底之上的每一个冗余区域内设有至少一个冗余鳍结构。每一个有源区域与冗余区域被第一条形区域和/或第二条形区域间隔。
本申请实施例中，每一个有源区域对应至少一个鳍式场效应晶体管，也就是说，上述芯片包括至少一个鳍式场效应晶体管。每一个有源区域与冗余区域被第一条形区域和/或第 二条形区域间隔，因而，每一个有源区域中的鳍结构与冗余区域中的冗余鳍结构分隔设置，因而，冗余鳍结构不会影响鳍结构的性能。
并且，衬底的表面具有的各冗余区域中，至少一个冗余区域的形状为包括至少五个边的多边形，即，该多边形可以包括5个、6个或更多个边，可以根据衬底表面具有的各有源区域的位置和形状进行设置。且该冗余区域包括至少一个子区域，该子区域由该多边形中的至少三个边围绕，该子区域嵌入到相邻两个有源区域之间的间隙中。在一种可能的实现方式中，该子区域可以为：由该多边形中的至少三个边与位于该冗余区域内的某一条线段(也可以为折线或曲线等)围成的封闭区域。
这样，可以充分利用相邻两个有源区域之间的空间，可以在有源区域的附近设置较多的冗余鳍结构，进而可以使冗余区域的面积较大，可以大幅提高后续形成的隔离介质层的均匀性，进而使后续形成的膜层的质量较好，使得该鳍式场效应晶体管的性能较好。
在一种可能的实现方式中，衬底表面的多个冗余区域中的至少一个冗余区域，至少半包围一个有源区域，冗余区域可以半包围一个、两个或更多个有源区域；或者，冗余区域也可以全包围至少一个有源区域，此处不做限定。可以理解的是，冗余区域至少半包围一个有源区域指的是，冗余区域围绕有源区域的至少两个边。
可选地，衬底表面的多个冗余区域中的至少一个冗余区域可以为矩形。
在具体实施时，衬底表面的多个有源区域中的至少一个有源区域为矩形，该有源区域与冗余区域被两个第一条形区域和两个第二条形区域间隔。当然，有源区域也可以为其他形状，例如有源区域可以为“L”形，可以根据有源区域的形状，来设置围绕该有源区域的第一条形区域和第二条形区域的数量和位置。
在一种可能的实现方式中，上述芯片还可以包括：位于衬底之上的隔离介质层，鳍结构凸出于隔离介质层背离衬底的一侧。此外，该芯片还可以包括：位于衬底之上的有源区域内的栅极介质层和栅极。栅极位于鳍结构背离衬底的一侧，栅极介质层位于鳍结构与栅极之间。鳍结构包括源区、漏区和沟道区，沟道区位于源区和漏区之间，栅极覆盖鳍结构的沟道区的位置处，并且，在鳍结构的顶面和两个侧面均围绕有栅极，因而，栅极可以通过鳍结构的顶面和两个侧面控制沟道区，使得鳍式场效应晶体管具有栅控能力强、器件体积小、功耗低等优点。
第三方面，本申请实施例还提供了一种电子设备，该电子设备可以为智能手机、智能电视、笔记本电脑等设备。该电子设备可以包括：上述任一芯片，以及印刷电路板。由于上述芯片中的鳍式场效应晶体管的性能较好，因而，包括上述芯片的电子设备的性能也较好。
附图说明
图1为鳍式场效应晶体管的结构示意图；
图2为本申请实施例提供的芯片的制作方法的流程图；
图3、图4、图5a、图5b和图6为本申请实施例中芯片的制作方法中各步骤对应的结构示意图；
图7至图12为本申请实施例中鳍条的制作工艺流程图；
图13a为在衬底上形成的多个鳍条的结构示意图；
图13b为图13a中虚线WW＇处的截面示意图；
图14a为去除多个第一条形区域内的鳍条过程中的结构示意图；
图14b为图14a中虚线PP＇处的截面示意图；
图15a为去除多个第一条形区域内的鳍条后的结构示意图；
图15b为图15a中虚线PP＇处的截面示意图；
图16a为去除多个第二条形区域内的鳍条过程中的结构示意图；
图16b为图16a中虚线QQ＇处的截面示意图；
图17a为去除多个第二条形区域内的鳍条后的结构示意图；
图17b为图17a中虚线QQ＇处的截面示意图；
图18至图20为本申请实施例中芯片的制作方法中各步骤对应的结构示意图。
附图标记：
10-衬底；11-鳍条；111-鳍结构；112-冗余鳍结构；12-隔离介质层；13-栅极；14-栅极介质层；15-基轴；16-侧墙层；161-侧墙；17-缓冲层；18-保护层；A1～A7-有源区域；T1-第一条形区域；T2-第二条形区域；C1、C2、C3-冗余区域；a-第一边缘；b-第二边缘。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
应注意的是，本申请的附图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
本申请实施例提供了一种芯片、芯片的制作方法及电子设备。该芯片可以为中央处理器芯片、人工智能芯片等，当然，该芯片也可以为其他类型的芯片，此处不做限定。本申请实施例提供的芯片可以应用于各种类型的电子设备中，例如，该电子设备可以为智能手机、智能电视、笔记本电脑等。
本申请实施例提供的芯片可以包括至少一个鳍式场效应晶体管，图1为鳍式场效应晶体管的结构示意图，如图1所示，鳍式场效应晶体管可以包括：衬底10，位于衬底10之上的至少一个鳍结构111，位于衬底10之上的隔离介质层12，位于鳍结构111背离衬底10一侧的栅极13，以及位于鳍结构111与栅极13之间的栅极介质层14。其中，鳍结构111为沿第一方向F1延伸的条状结构，并且，各鳍结构111沿第二方向F2排列。第一方向F1与第二方向F2相互交叉，第三方向F3可以为垂直于衬底10表面的方向。图1中以该鳍式场效应晶体管包括三个鳍结构111为例，在具体实施时，该鳍式场效应晶体管也可以包括一个、两个、四个或更多个鳍结构111，此处不对鳍结构111的数量进行限定。鳍结构111凸出于隔离介质层12背离衬底10的一侧。鳍结构111包括源区、漏区和沟道区，栅极13覆盖鳍结构11的沟道区的位置处，并且，在鳍结构111的顶面和两个侧面均围绕有栅极13，因而，栅极13可以通过鳍结构111的顶面和两个侧面控制沟道区，使得鳍式场效应晶体管具有栅控能力强、器件体积小、功耗低等优点。
下面结合附图，对本申请实施例提供的芯片、芯片的制作方法及电子设备进行详细说明。
图2为本申请实施例提供的芯片的制作方法的流程图，图3、图4、图5a、图5b和图 6为本申请实施例中芯片的制作方法中各步骤对应的结构示意图。如图2所示，本申请实施例提供的芯片的制作方法，可以包括：
S201、参照图3，提供一衬底10。其中，该衬底10的表面具有：多个有源区域(例如图3中的衬底10的表面具有有源区域A1～A7)，沿第一方向F1延伸的多个第一条形区域T1，沿第二方向F2延伸的多个第二条形区域T2，以及多个冗余区域(例如图3中衬底10的表面具有冗余区域C1～C3)。冗余区域C1～C3位于除多个有源区域、多个第一条形区域T1、多个第二条形区域T2外的区域内。第一方向F1与第二方向F2相互交叉，例如第一方向F1与第二方向F2可以相互垂直。每一个有源区域对应至少一个将要形成的鳍式场效应晶体管，每一个有源区域被第一条形区域T1和/或第二条形区域T2构成的区域围绕，例如图3中，有源区域A1、A2、A3、A4、A6及A7被两个第一条形区域T1和两个第二条形区域T2构成的区域围绕。
在具体实施时，相邻的至少两个有源区域可以共用第一条形区域T1或第二条形区域T2。例如在图3中，有源区域A2和有源区域A3共用同一个第二条形区域T2，有源区域A1和有源区域A4共用同一个第二条形区域T2，有源区域A5和有源区域A6共用同一个第二条形区域T2。或者，边缘基本对齐的至少两个有源区域可以共用第一条形区域T1或第二条形区域T2，例如在图3中，有源区域A1、有源区域A5和有源区域A6共用同一个第一条形区域T1，有源区域A3和有源区域A7可以共用同一个第一条形区域T。应该说明的是，图3中以有源区域A1、A2、A3、A4、A6及A7为矩形，有源区域A5为“L”形为例进行示意，在实际应用中，有源区域也可以为其他形状，可以根据将要形成的鳍式场效应晶体管的结构进行设置，并且，可以根据衬底10上个有源区域的形状和相对位置，来设置个第一条形区域T1和第二条形区域T2的形状和位置。
S202、参照图4，在衬底10上形成多个鳍条11，可选地，形成的多个鳍条11可以近似铺满衬底10的表面，即在有源区域A1～A7中、各第一条形区域T1中、各第二条形区域T2中，以及冗余区域C1～C3中均分布有鳍条11。
S203、参照图5a，去除多个第一条形区域T1和多个第二条形区域T2内的鳍条，以在每一个有源区域内形成鳍式场效应晶体管的鳍结构111，以及在每一个冗余区域内形成冗余鳍结构112。其中，鳍结构111为位于有源区域内的部分鳍条，冗余鳍结构112为位于冗余区域内的部分鳍条。
为了更清楚的示意步骤S203中形成的鳍结构和冗余鳍结构，图6中省去了图5a中各第一条形区域和第二条形区域的标记。从图6中可以明显看出，每一个有源区域包括至少一个条形的鳍结构111，在各有源区域以外的冗余区域C1～C3中具有多个冗余鳍结构112。并且，由于去除了有源区域周围的第一条形区域和第二条形区域内的鳍条，使形成的鳍结构111与冗余鳍结构112分隔设置，因而，形成的冗余鳍结构112不会影响鳍结构111的性能。而且，形成的各冗余区域中，至少一个冗余区域的形状为包括至少五个边的多边形，且该冗余区域的边缘嵌入到相邻两个有源区域之间的间隙中，例如，冗余区域C1为包括16个边的多边形，且冗余区域C1的边缘嵌入到有源区域A4和有源区域A5之间的间隙中，使得冗余区域的面积较大，可以使有源区域的附近具有较多的冗余鳍结构，能够大幅提高后续形成的隔离介质层的均匀性，使得形成的鳍式场效应晶体管的性能较好。
本申请实施例提供的芯片的制作方法，通过设置多个第一条形区域和多个第二条形区域，第一条形区域沿第一方向延伸，第二条形区域沿第二方向延伸，且每一个有源区域被 第一条形区域和/或第二条形区域构成的区域围绕。这样，去除多个第一条形区域和多个第二条形区域内的鳍条后，可以在每一个有源区域内形成鳍式场效应晶体管的鳍结构，并且，可以在除有源区域、第一条形区域和第二条形区域以外的冗余区域内形成冗余鳍结构。冗余鳍结构通过第一条形区域和第二条形区域与有源区域内的鳍结构分隔，因而冗余鳍结构不会影响有源区域内鳍结构的性能。而且，通过设置冗余鳍结构可以使后续形成的隔离介质层的均匀性较好，从而，可以使后续形成的膜层的质量较好，也可以防止由于应力不均导致的鳍结构弯曲及错位等缺陷。此外，第一条形区域和第二条形区域的形状较简单，去除鳍条的工艺的难度降低，不会影响有源区域中鳍结构的形状。因此，本申请实施例提供的芯片的制作方法得到的鳍式场效应晶体管的性能较好。
在具体实施时，上述步骤S202，可以包括：参照图4，在衬底10上形成沿第一方向F1延伸的多个鳍条11。也就是说，衬底10上形成的各鳍条11的延伸方向一致，且鳍条11的延伸方向与第一条形区域T1的延伸方向一致。这样，在后续步骤S203中，更容易去除第一条形区域T1和第二条形区域T2内的鳍条11，去除鳍条11的工艺精度更高，因而，去除第一条形区域T1和第二条形区域T2的鳍条11的过程中，不会影响有源区域中的鳍结构的形状，使得有源区域中形成的鳍式场效应晶体管的性能更好。
在本申请实施例中，如图3所示，每一个有源区域(例如可以参照有源区域A7)可以包括：沿第一方向F1延伸的至少两个第一边缘a，以及沿第二方向F2延伸的至少两个第二边缘b。每一个第一条形区域T1与至少一个有源区域的第一边缘a相邻，每一个第二条形区域T2与至少一个有源区域的第二边缘b相邻。也就是说，有源区域与围绕该有源区域的第一条形区域T1和第二条形区域T2的距离较近，这样，去除第一条形区域T1和第二条形区域T2内的鳍条后，形成的鳍结构基本位于各有源区域的范围内，鳍结构的制作精度较高。并且，有源区域与围绕该有源区域的第一条形区域T1和第二条形区域T2之间可以具有一定的间隙，可以避免由于工艺误差，在去除第一条形区域T1和第二条形区域T2内的鳍条的过程中，影响有源区域内的鳍结构的形状，从而，可以保证形成于有源区域内的鳍结构的性能较好。
在实际应用中，继续参照图3，第一条形区域T1在第二方向F2上的宽度d1可以在0～2000nm的范围内，第二条形区域T2在第一方向F1上的宽度d2可以在0～2000nm的范围内。这样，通过合理设置第一条形区域和第二条形区域的宽度，可以控制有源区域、第一条形区域和第二条形区域以外的冗余区域的大小，可以使第一条形区域T1和第二条形区域T2的宽度较窄，使得步骤S203中去除的鳍条的面积较小，进而，可以使形成的冗余鳍结构的面积较大，使各有源区域外的区域与有源区域的工艺差异较小，能够达到优化工艺的效果，保证形成的鳍式场效应晶体管的性能较好。
图7至图12为本申请实施例中鳍条的制作工艺流程图，结合图7至图12，上述步骤S202，可以包括：
参照图7，在衬底10上形成多个基轴15，基轴15的延伸方向与将要形成的鳍条的延伸方向相同，也就是图7中垂直于纸面的方向可以为上述第一方向，图中水平方向可以为上述第二方向F2，图中竖直方向为第三方向F3，第三方向F3可以为垂直于衬底10表面的方向。可选地，可以采用多晶硅材料制作基轴15，当然，也可以采用其他材料制作基轴15，此处不做限定。在实际工艺过程中，可以在衬底10之上形成整面的基轴膜层，然后通过刻蚀工艺得到位于衬底10之上的多个基轴15。
参照图8，在基轴15之上整面形成侧墙层16，在具体实施时，可以采用氮化硅材料制作侧墙层16，当然，也可以采用其他材料制作侧墙层16，此处不做限定。之后，对侧墙层16进行刻蚀，参照图9，形成位于基轴15的侧壁处的多个侧墙161。在实际工艺过程中，可以对侧墙层进行整面刻蚀，由于基轴15侧壁的几何效应，基轴15侧壁处的材料不会被刻蚀掉，从而在基轴15的侧壁处形成侧墙161。
采用刻蚀工艺去除多个基轴，得到图10所示的结构。
参照图11，以多个侧墙161为遮挡，对衬底10进行刻蚀，以得到多个鳍条11的图形。
参照图12，去除多个侧墙，得到多个鳍条11。
本申请实施例中，以图7至图12所示的制作流程为例，对鳍条的制作过程进行举例说明，在实际工艺过程中，也可以采用其他方式制作鳍条，此处不做限定。
图13a为在衬底上形成的多个鳍条的结构示意图，图13b为图13a中虚线WW＇处的截面示意图，如图13a和图13b所示，在上述步骤S202中，在衬底10上形成了多个沿第一方向F1延伸的鳍条11。在上述步骤S202之后，上述步骤S203之前，还可以包括：在鳍条11之上形成缓冲层17，以及在缓冲层17之上形成保护层18。通过在鳍条11之上形成缓冲层17和保护层18，可以对鳍条11起到保护作用，防止后续工艺过程损伤鳍条11。
图14a为去除多个第一条形区域内的鳍条过程中的结构示意图，图14b为图14a中虚线PP＇处的截面示意图，图15a为去除多个第一条形区域内的鳍条后的结构示意图，图15b为图15a中虚线PP＇处的截面示意图。图16a为去除多个第二条形区域内的鳍条过程中的结构示意图，图16b为图16a中虚线QQ＇处的截面示意图。图17a为去除多个第二条形区域内的鳍条后的结构示意图，图17b为图17a中虚线QQ＇处的截面示意图。以下结合附图，对上述步骤S203中，去除多个第一条形区域和多个第二条形区域内的鳍条的过程进行详细说明。
参照图14a和图14b，可以采用光刻工艺和刻蚀工艺，去除多个第一条形区域T1内的鳍条11。可选地，可以在保护层18之上整面形成光刻胶层(图中未示出)，采用曝光、显影工艺去除多个第一条形区域T1中的光刻胶层，以使光刻胶层保护除多个第一条形区域T1以外的区域，然后，采用刻蚀工艺去除多个第一条形区域T1内的鳍条11，之后去除剩余的光刻胶层。去除多个第一条形区域T1内的鳍条11后，得到图15a和图15b所示的结构。
参照图16a和图16b，可以采用光刻工艺和刻蚀工艺，去除多个第二条形区域T2内的鳍条11。可选地，可以在保护层18之上整面形成光刻胶层(图中未示出)，采用曝光、显影工艺去除多个第二条形区域T2中的光刻胶层，以使光刻胶层保护除多个第二条形区域T2以外的区域，然后，采用刻蚀工艺去除多个第二条形区域T2内的鳍条11，之后去除剩余的光刻胶层。去除多个第二条形区域T2内的鳍条11后，得到图17a和图17b所示的结构，如图17a和图17b所示，去除多个第一条形区域T1和多个第二条形区域T2内的鳍条11后，在有源区域A1～A7内形成了鳍结构111，以及在冗余区域C1～C3内形成了冗余鳍结构112。
在实际工艺过程中，在去除第一条形区域或第二条形区域中的鳍条的过程中，可以通过调节光源、曝光参数等光刻工艺的条件以及刻蚀工艺条件，来提高工艺精度和工艺窗口。
本申请实施例中，以先去除多个第一条形区域中的鳍条，再去除多个第二条形区域中的鳍条为例进行示意，在实际工艺过程中，也可以先去除多个第二条形区域中的鳍条，再 去除多个第一条形区域中的鳍条，或者，也可以将多个第一条形区域和多个第二条形区域中的鳍条一起去除，此处不做限定。
图18至图20为本申请实施例中芯片的制作方法中各步骤对应的结构示意图，在本申请的一些实施例中，在上述步骤S203之后，还可以包括：
对每一个有源区域内的鳍结构进行掺杂处理，以在鳍结构中形成源区、漏区和沟道区，其中，沟道区可以位于源区和漏区之间；在实际应用中，在对有源区域内的鳍结构进行掺杂处理之前，还可以去除鳍结构上的缓冲层和保护层。在对有源区域内的鳍结构进行掺杂的工艺过程中，也可以对冗余区域中的冗余鳍结构进行掺杂，从而无需对冗余区域进行遮挡，简化工艺难度。
如图18所示，在衬底10的表面形成隔离介质层12，并刻蚀隔离介质层12，以使每一个鳍结构11凸出于隔离介质层12。本申请实施例中，在衬底10表面形成的隔离介质层12可以近似整面设置，对隔离介质层12进行刻蚀后，还可以使每一个冗余鳍结构凸出于隔离介质层12。由于在除有源区域、第一条形区域和第二条形区域以外的冗余区域内具有冗余鳍结构，可以使形成的隔离介质层12的均匀性较好。
如图19所示，在每一个有源区域内的鳍结构11之上形成栅极介质层14，栅极介质层14可以覆盖鳍结构11的沟道区。
如图20所示，在每一个有源区域内的栅极介质层14之上形成栅极13，以得到至少一个图1所示的鳍式场效应晶体管。由于本申请实施例中形成的隔离介质层12的均匀性较好，因而，后续形成的栅极介质层14和栅极13的质量较好，得到的鳍式场效应晶体管的性能较好。
在实际工艺过程中，也可以在冗余鳍结构之上形成栅极介质层14和栅极13，从而使有源区域与冗余区域内的工艺差异较小。此外，在掺杂工艺之后，还可以形成与鳍结构的源区电连接的源极，以及形成与鳍结构的漏区电连接的漏极，从而将鳍结构的源区和漏区引出。由于冗余鳍结构仅起到使后续形成的隔离介质层的均匀性较好的作用，无需与其他部件电连接，因而，冗余鳍结构中的源区和漏区无需引出。
基于同一技术构思，本申请实施例还提供了一种芯片，该芯片可以为中央处理器芯片、人工智能芯片等各种类型的芯片。该芯片可以采用上述任一制作方法制作而成。
如图5a所示，该芯片可以包括：衬底10，位于衬底10之上的多个鳍结构111和多个冗余鳍结构112。衬底10的表面可以具有：多个有源区域(例如图5a中衬底10的表面具有源区域A1～A7)，沿第一方向F1延伸的多个第一条形区域T1，沿第二方向F2延伸的多个第二条形区域T2，以及多个冗余区域(例如图5a中衬底10的表面具有冗余区域C1～C3)，冗余区域C1～C3可以位于除各有源区域、多个第一条形区域T1和多个第二条形区域T2以外的区域内。其中，第一方向F1与第二方向F2相互交叉，例如，第一方向F1与第二方向F2可以相互垂直。衬底10之上的每一个有源区域内设有至少一个鳍结构111，衬底10之上的每一个冗余区域内设有至少一个冗余鳍结构112，每一个有源区域与冗余区域被第一条形区域T1和/或第二条形区域T2间隔。
本申请实施例中，每一个有源区域对应至少一个鳍式场效应晶体管，也就是说，上述芯片包括至少一个鳍式场效应晶体管。每一个有源区域与冗余区域被第一条形区域T1和/或第二条形区域T2间隔，因而，每一个有源区域中的鳍结构111与冗余区域中的冗余鳍结构112分隔设置，因而，冗余鳍结构不会影响鳍结构的性能。
并且，衬底的表面具有的各冗余区域中，至少一个冗余区域的形状为包括至少五个边的多边形，即，该多边形可以包括5个、6个或更多个边，可以根据衬底表面具有的各有源区域的位置和形状进行设置。且该冗余区域包括至少一个子区域，该子区域由该多边形中的至少三个边围绕，该子区域嵌入到相邻两个有源区域之间的间隙中。在一种可能的实现方式中，该子区域可以为：由该多边形中的至少三个边与位于该冗余区域内的某一条线段(也可以为折线或曲线等)围成的封闭区域。
图5b为图5a的局部放大示意图，为了清楚的示意冗余区域中的子区域，图5b中省去了鳍结构、冗余鳍结构、第一条形区域和第二条形区域的图形。结合图5a和图5b，举例来说，图5a中的冗余区域C1为包括16个边的多边形。其中，冗余区域C1可以包括子区域C11和子区域C12。子区域C11可以为：冗余区域C1的边x1、x2和x3与位于冗余区域C1内的线段y1围城的封闭区域，子区域C11嵌入到有源区域A4与A5之间的间隙中。子区域C12可以为冗余区域C1的边x4、x5、x6和x7与位于冗余区域C1内的线段y2围城的封闭区域，子区域C12嵌入到有源区域A2、A1与A4之间的间隙中。
这样，可以充分利用相邻两个有源区域之间的空间，可以在有源区域的附近设置较多的冗余鳍结构，进而可以使冗余区域的面积较大，可以大幅提高后续形成的隔离介质层的均匀性，进而使后续形成的膜层的质量较好，使得该鳍式场效应晶体管的性能较好。
继续参照图5a，衬底表面的多个冗余区域中的至少一个冗余区域，至少半包围一个有源区域，例如图5a中，冗余区域C1半包围有源区域A4、A5及A7，当然，冗余区域也可以半包围一个、两个或更多个有源区域，或者，冗余区域也可以全包围至少一个有源区域，此处不做限定。可以理解的是，冗余区域至少半包围一个有源区域指的是，冗余区域围绕有源区域的至少两个边。
可选地，衬底表面的多个冗余区域中的至少一个冗余区域可以为矩形，例如图5a中冗余区域C2和C3为矩形。
在具体实施时，如图5a所示，衬底10表面的多个有源区域中的至少一个有源区域为矩形(例如图5a中的有源区域A1为矩形)，该有源区域与冗余区域被两个第一条形区域T1和两个第二条形区域T2间隔。当然，有源区域也可以为其他形状，例如图5a中有源区域A5为“L”形，可以根据有源区域的形状，来设置围绕该有源区域的第一条形区域和第二条形区域的数量和位置。
在本申请实施例中，如图1所示，该芯片还可以包括：位于衬底10之上的隔离介质层12，鳍结构111凸出于隔离介质层12背离衬底10的一侧。此外，该芯片还可以包括：位于衬底10之上的有源区域内的栅极介质层14和栅极13，栅极13位于鳍结构111背离衬底10的一侧，栅极介质层14位于鳍结构111与栅极13之间。鳍结构111包括源区、漏区和沟道区，沟道区位于源区和漏区之间，栅极13覆盖鳍结构11的沟道区的位置处，并且，在鳍结构111的顶面和两个侧面均围绕有栅极13，因而，栅极13可以通过鳍结构111的顶面和两个侧面控制沟道区，使得鳍式场效应晶体管具有栅控能力强、器件体积小、功耗低等优点。
基于同一技术构思，本申请实施例还提供了一种电子设备，该电子设备可以为智能手机、智能电视、笔记本电脑等设备。该电子设备可以包括：上述任一芯片，以及印刷电路板。由于上述芯片中的鳍式场效应晶体管的性能较好，因而，包括上述芯片的电子设备的性能也较好。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种芯片，其特征在于，包括：衬底，位于所述衬底之上的多个鳍结构和多个冗余鳍结构；
    所述衬底的表面具有：多个有源区域，沿第一方向延伸的多个第一条形区域，沿第二方向延伸的多个第二条形区域，以及多个冗余区域；其中，所述第一方向与所述第二方向相互交叉；
    所述衬底之上的每一个所述有源区域内设有至少一个所述鳍结构；
    所述衬底之上的每一个所述冗余区域内设有至少一个所述冗余鳍结构；
    每一个所述有源区域与所述冗余区域被所述第一条形区域和/或所述第二条形区域间隔；
    所述多个冗余区域中的至少一个所述冗余区域的形状为包括至少五个边的多边形，且该冗余区域包括至少一个子区域，所述子区域由所述至少五个边中的至少三个边围绕，所述子区域嵌入到相邻两个所述有源区域之间的间隙中。
  2. 如权利要求1所述的芯片，其特征在于，所述多个冗余区域中的至少一个所述冗余区域，至少半包围一个所述有源区域。
  3. 如权利要求1所述的芯片，其特征在于，所述多个冗余区域中的至少一个所述冗余区域为矩形。
  4. 如权利要求1～3任一项所述的芯片，其特征在于，所述多个有源区域中的至少一个所述有源区域为矩形，该有源区域与所述冗余区域被两个所述第一条形区域和两个所述第二条形区域间隔。
  5. 如权利要求1～4任一项所述的芯片，其特征在于，还包括：位于所述衬底之上的隔离介质层；
    所述鳍结构凸出于所述隔离介质层背离所述衬底的一侧。
  6. 如权利要求5所述的芯片，其特征在于，还包括：位于所述衬底之上的所述有源区域内的栅极介质层和栅极；
    所述栅极位于所述鳍结构背离所述衬底的一侧，所述栅极介质层位于所述鳍结构与所述栅极之间；
    所述鳍结构包括源区、漏区及沟道区，所述沟道区位于所述源区和所述漏区之间，所述栅极覆盖所述鳍结构的所述沟道区的位置处。
  7. 一种电子设备，其特征在于，包括：如权利要求1～6任一项所述的芯片，以及印刷电路板。
  8. 一种芯片的制作方法，其特征在于，包括：
    提供一衬底；其中，所述衬底的表面具有：多个有源区域，沿第一方向延伸的多个第一条形区域，沿第二方向延伸的多个第二条形区域，以及多个冗余区域；所述第一方向与所述第二方向相互交叉；每一个所述有源区域对应至少一个将要形成的所述鳍式场效应晶体管，每一个所述有源区域被所述第一条形区域和/或所述第二条形区域构成的区域围绕；
    在所述衬底上形成多个鳍条；
    去除所述多个第一条形区域和所述多个第二条形区域内的所述鳍条，以在每一个所述有源区域内形成所述鳍式场效应晶体管的鳍结构，以及在每一个所述冗余区域内形成冗余 鳍结构；其中，所述鳍结构为位于所述有源区域内的部分所述鳍条，所述冗余鳍结构为位于所述冗余区域内的部分所述鳍条。
  9. 如权利要求8所述的制作方法，其特征在于，所述在所述衬底上形成多个鳍条，包括：
    在所述衬底上形成沿所述第一方向延伸的多个所述鳍条。
  10. 如权利要求8所述的制作方法，其特征在于，每一个所述有源区域包括：沿所述第一方向延伸的至少两个第一边缘，以及沿所述第二方向延伸的至少两个第二边缘；
    每一个所述第一条形区域与至少一个所述有源区域的所述第一边缘相邻，每一个所述第二条形区域与至少一个所述有源区域的所述第二边缘相邻。
  11. 如权利要求10所述的制作方法，其特征在于，所述第一条形区域在所述第二方向上的宽度在0～2000nm的范围内，所述第二条形区域在所述第一方向上的宽度在0～2000nm的范围内。
  12. 如权利要求10所述的制作方法，其特征在于，所述去除所述多个第一条形区域和所述多个第二条形区域内的所述鳍条，包括：
    采用光刻工艺和刻蚀工艺，去除所述多个第一条形区域内的所述鳍条；
    采用光刻工艺和刻蚀工艺，去除所述多个第二条形区域内的所述鳍条。
  13. 如权利要求8～12任一项所述的制作方法，其特征在于，所述在所述衬底上形成多个鳍条，包括：
    在所述衬底上形成多个基轴，所述基轴的延伸方向与将要形成的所述鳍条的延伸方向相同；
    在所述基轴之上整面形成侧墙层，并对所述侧墙层进行刻蚀，以形成位于所述基轴的侧壁处的多个侧墙；
    采用刻蚀工艺去除所述多个基轴；
    以所述多个侧墙为遮挡，对所述衬底进行刻蚀，以得到所述多个鳍条的图形；
    去除所述多个侧墙，得到所述多个鳍条。
  14. 如权利要求8～13任一项所述的制作方法，其特征在于，在形成所述鳍式场效应晶体管的鳍结构之后，还包括：
    对每一个所述有源区域内的所述鳍结构进行掺杂处理，以在所述鳍结构中形成源区、漏区和沟道区；
    在所述衬底的表面形成隔离介质层，并刻蚀所述隔离介质层，以使每一个所述鳍结构凸出于所述隔离介质层；
    在每一个所述有源区域内的所述鳍结构之上形成栅极介质层；
    在每一个所述有源区域内的所述栅极介质层之上形成栅极，以得到至少一个鳍式场效应晶体管。
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CN107393921A (zh) * 2016-05-17 2017-11-24 三星电子株式会社 半导体器件及其制造方法
CN108878364A (zh) * 2017-05-12 2018-11-23 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20190189609A1 (en) * 2017-11-24 2019-06-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having fin structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393921A (zh) * 2016-05-17 2017-11-24 三星电子株式会社 半导体器件及其制造方法
CN108878364A (zh) * 2017-05-12 2018-11-23 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20190189609A1 (en) * 2017-11-24 2019-06-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having fin structure

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