CN106298916B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106298916B
CN106298916B CN201510273696.XA CN201510273696A CN106298916B CN 106298916 B CN106298916 B CN 106298916B CN 201510273696 A CN201510273696 A CN 201510273696A CN 106298916 B CN106298916 B CN 106298916B
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fin
pattern
dummy gate
forming
gate structure
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CN106298916A (zh
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孙千媖
刘恩铨
陈明新
童宇诚
杨智伟
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。其中，该半导体元件包含多个鳍状结构，设置于一基底上，其中，该鳍状结构的至少一具有一尖端；以及一虚置栅极结构，设置于该基底上，其中，该虚置栅极结构包含一延伸部位，该延伸部位覆盖该尖端。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其形成方法，尤其是涉及一种包含虚置栅极结构的半导体元件及其形成方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明的一目的在于提供一种半导体元件的形成方法，其中该半导体元件具有可完全覆盖鳍状结构边缘的虚置栅极结构，有利于形成具有更佳可靠度的半导体元件。
为达上述目的，本发明的一实施例提供一种半导体元件，其包含多个鳍状结构，设置于一基底上，其中，该鳍状结构的至少一具有一尖端；以及一虚置栅极结构，设置于该基底上，其中，该虚置栅极结构包含一延伸部位，该延伸部位覆盖该尖端。
为达上述目的，本发明的一实施例提供一种形成半导体元件的方法，其包含以下步骤。首先，在一基底上形成多个环绕多个鳍状结构的浅沟隔离，其中该鳍状结构的至少一具有一尖端。后续，在该基底上形成一虚置栅极结构，其中，该虚置栅极结构包含一延伸部位，该延伸部位覆盖该尖端。
本发明的半导体元件及其形成方法，主要是在栅极结构的至少一侧形成有一延伸部，并使该延伸部可延伸至完全覆盖或有效覆盖在鳍状结构的两侧，特别是指可覆盖到该鳍状结构因受到光学接近效应影响而产生形变的侧边。由此，本发明可形成具有更佳可靠度的半导体元件。
附图说明
图1至图6为本发明第一实施例中形成半导体元件的方法的步骤剖面示意图；
图7为本发明一实施例中形成半导体元件的栅极结构的步骤剖面示意图；
图8至图11为本发明第二实施例中形成半导体元件的方法的步骤剖面示意图。
主要元件符号说明
100 基底
101 鳍状结构
101a 尖端
102 斜边
103、104 侧边
105 衬垫层
106 浅沟隔离
110 框状的鳍状结构
130、150、170 栅极结构
135 延伸部
151、171 栅极介电层
152、172 栅极
153、173 间隙壁
155 延伸部
200 光致抗蚀剂层
210 开口图案
230 图案
300、301 图案化牺牲层
302 凹口
310 间隙壁
311 特定部
401 鳍状图案
402 开口图案
403、405、407 栅极图案
406、408 延伸图案
θ1 锐角
θ2 钝角
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图6，所绘示者为本发明第一实施例中形成半导体元件的方法的步骤示意图。首先，如图1所示，提供一基底100。基底100例如是一硅基底、一含硅基底或一硅覆绝缘(silicon-on-insulator,SOI)基底等半导体基底。在一实施例中，基底100上还可先形成有一掩模层(未绘示)，该掩模层可具有单层或多层结构，例如包含由一氧化硅(siliconoxide)层(未绘示)以及一氮化硅(silicon nitride)层(未绘示)所组成的复合结构。
接着，在基底100形成至少一鳍状结构101。在块状硅(bulk silicon)基底的实施态样中，鳍状结构101的形成方式优选是利用一侧壁图案转移(sidewall image transfer,SIT)技术，包含通过一光刻暨蚀刻制作工艺在基底100上先形成多个图案化牺牲层(未绘示)，再依序进行沉积及蚀刻制作工艺，以于各该图案化牺牲层的侧壁形成一间隙壁(未绘示)，后续，去除该多个图案化牺牲层，保留多个具有封闭式的矩形框架的该间隙壁。之后，通过该多个间隙壁的覆盖再进行至少一蚀刻制作工艺，使得各该间隙壁的图案直接或逐步被转移至下方的基底100，形成多个浅沟槽(shallow trench，未绘示)，同时定义出多个被该浅沟槽环绕的框状的鳍状结构110，如图1所示。此外，在形成有该掩模层的实施例中，也可先将该多个间隙壁的图案被转移至单层或多层结构的该掩模层，再进行一蚀刻制作工艺，将该掩模层的图案转移至下方的基底100中。
之后，可进行一鳍状结构切割制作工艺(fin cut)移除初始结构中不必要的鳍片，例如是虚拟鳍片(dummy fin)及/或框状的鳍状结构110两端相连接的部分。具体来说，该鳍状结构切割制作工艺如图2所示是先于基底100上形成一图案化掩模，例如是具有至少一开口图案210的光致抗蚀剂层200，光致抗蚀剂层200大体上部分覆盖框状的鳍状结构110，并使得框状的鳍状结构110的一部分自开口图案210中被暴露出。需特别说明的是，在形成光致抗蚀剂层200时，是使用黄光制作工艺来定义其上的开口图案210，例如是利用曝光的方式将一光掩模(未绘示)上的蚀刻图案转移至光致抗蚀剂层200上。一般来说，该光掩模上用来界定开口的蚀刻图案，通常是由直线与直角组合所形成的几何图案，例如是呈正方形或是长方形的图案。然而，在对高密度排列的蚀刻图案进行曝光制作工艺以形成光致抗蚀剂层200时，容易产生光学接近效应(optical proximity effect)，使得形成于光致抗蚀剂层200上的开口图案210的直角处因为过度曝光(overexpose)或是曝光不足(underexpose)，造成分辨率减损(resolution loss)，使得光致抗蚀剂层200上实际形成的图案与该光掩模的原始设计图案不一致或是发生转角圆形化效应(corner rounding effect)。最后，如图2所示形成略呈圆形或椭圆形的开口图案210，其中矩形虚线框230则表示该光掩模上用来界定开口的图案230。
在此情况下，当后续以光致抗蚀剂层200为掩模进行一蚀刻制作工艺时，其下方的框状的鳍状结构110会受到该开口图案210的影响，使得其被蚀刻的一端形成一尖端101a，如图3所示。也就是说，在利用该鳍状结构切割制作工艺形成所需的鳍状结构布局时，例如是图3所示的条状排列的鳍状结构101，鳍状结构101的至少一端会受到光致抗蚀剂层200开口图案210形变的影响而形成一斜边102，使得鳍状结构101的一端具有逐渐缩减的宽度，进而形成尖端101a。在本实施例中，斜边102可以是如图3所示的一平面，并且可分别与鳍状结构101的两平行侧边103、104共同夹设有一锐角θ1及一钝角θ2，但不以此为限。本领域者应可轻易了解，本发明的鳍状结构101也可能因该开口图案的转角圆形化效应而形成一弧面(未绘示)或不规则面，而非原先预期的全部为矩形截角。
然后，依序形成覆盖基底100及鳍状结构101表面的一衬垫层(liner)105，以及至少填入该浅沟槽内的一绝缘层，然后再对此绝缘层进行化学机械研磨与回蚀刻等制作工艺，使其形成作为环绕各鳍状结构101的一浅沟隔离(STI)106。其中，衬垫层105及浅沟隔离106的具体形成方式及详细材质应为本领域者所熟知，于此不再赘述。
后续，请参照图4至图6所示，其中图5为图4的部分放大示意图；图6则是沿图4中A-A’剖线所绘示的剖面示意图。在基底100上形成横跨鳍状结构101的栅极结构130、150、170。在本实施例中，形成栅极结构130、150、170的制作工艺例如包含依序在鳍状结构101形成一栅极介电材料层(未绘示)，例如是包含氧化硅等绝缘材质，以及一栅极层(未绘示)，再图案化该栅极层及该栅极介电材料层，而在鳍状结构101上形成栅极结构130、150、170，如图4及图6所示。具体来说，各栅极结构150、170可包含栅极介电层151、171及栅极152、172，并且后续可继续形成环绕各栅极结构150、170的间隙壁153、173，例如是包含是氮化硅、氮氧化硅(silicon oxynitride)或氮碳化硅(silicon carbonitride)等材质，但并不限于此。
需特别说明的是，栅极结构130、150的一部分刚好横跨在鳍状结构101的一端，因而可形成部分位在浅沟隔离106上的栅极结构150，如图6所示。也就是说，栅极结构130、150的一部分是直接覆盖在浅沟隔离106上，而可构成一过路栅极(passing gate)，成为另一鳍式场效晶体管(fin field-effect transistor,FinFET)的栅极，或仅为另一不具有实际通路的一虚置栅极结构。在本实施例中，该过路栅极或虚置栅极结构的形成方式是与一般栅极结构的制作工艺整合，因此，该虚置栅极结构的栅极也可以同为一多晶硅栅极，但其材质非限于此，可视实际所需而定或另以其他方式形成。
此外，另需特别注意的是，栅极结构130、150覆盖在鳍状结构101尖端101a的部位分别具有一延伸部135、155。延伸部135、155是自栅极结构130、150的至少一侧边朝向鳍状结构101的延伸方向延伸出，由此，使得鳍状结构101受到光致抗蚀剂层200开口图案210形变的影响而产生的尖端101a可以完全被覆盖住，如图4及图5所示。在一实施例中，延伸部135、155优选在完全覆盖尖端101a后，更进一步延伸至覆盖到尖端101a以外的部分鳍状结构101，亦即延伸至覆盖到鳍状结构101的两平行侧边103、104的部分，如图5所示。由此，可避免尖端101a无法被该虚置栅极结构完全覆盖或有效覆盖，而导致元件缺失的情况。然而，本领域通常知识者也应了解，栅极结构130、150、170的形成方式并不限于前述的制作工艺，也可能包含其他步骤。举例来说，在另一实施例中也可利用侧壁图案转移技术来形成多个横跨鳍状结构101的栅极结构(未绘示)，例如是形成间距不同的图案化牺牲层301，如图7左所示；或是于图案化牺牲层300形成一内缩的凹口302，如图7右所示，使得后续于各图案化牺牲层300、301的侧壁形成的间隙壁310可部分融合成一较宽的特定部311。由此，利用间隙壁310作为蚀刻掩模进行蚀刻制作工艺即可于基底100形成如图6所示具有延伸部135、155的栅极结构130、150，但不以此为限。
由此即完成本发明第一实施例的半导体元件。后续，则可再搭配一轻掺杂漏极(light-doped drain,LDD)制作工艺、源极/漏极制作工艺、选择性外延成长(selectiveepitaxial growth，SEG)制作工艺、金属硅化物制作工艺、接触洞停止蚀刻层(contactetch stop layer,CESL)制作工艺或是金属栅极置换(replacement metal gate,RMG)等制作工艺，上述相关步骤与现有制作晶体管的步骤类似，在此不多加赘述。
此外，本领域者应可轻易了解，本发明的半导体元件也可能以其他方式形成，并不限于前述的制作步骤。因此，下文将进一步针对本发明半导体元件及其形成方法的其他实施例或变化型进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参照图8至图11，所绘示者为本发明第二实施例中形成半导体元件的方法的步骤示意图。本实施例的半导体元件的形成方法大体上和前述第一实施例相同，其差异处在于本实施例是直接利用绘图数据系统(graphic data system,GDS)定义可用以形成鳍状结构及栅极结构的掩模图案。具体来说，本实施例例如是图8所示首先提供一第一布局图案，其包含有多个平行排列的鳍状图案401，并将鳍状图案401输入至一电脑系统(未绘示)中。鳍状图案401是指后续欲形成于一半导体光致抗蚀剂层上(未绘示)的理想鳍状图案，其反映了后续半导体结构的布局图案(layout)。
然而，为避免光学接近效应的影响，造成转移后的鳍状图案401发生偏移的现象，本实施例进一步提供如图9所示的开口图案402。开口图案402是指后续欲形成于一光致抗蚀剂层上(未绘示)的蚀刻开口，其优选是位在鳍状图案401两侧且部分重叠于鳍状图案401。由此，即可在后续鳍状结构切割制作工艺中，利用该光致抗蚀剂层作为蚀刻掩模来移除不必要的鳍状结构(未绘示)，形成所需的结构布局。然而在实际制作工艺中，该光致抗蚀剂层上实际形成的图案可能发生转角圆形化效应，而与原始设计的开口图案402不一致，因而使被切割后的该鳍状结构形成如前述图3所示的尖端101a。
之后，则如图10及图11所示，提供一第三布局图案，其包含有多个横跨鳍状图案401的栅极图案403、405、407，并输入至该电脑系统中。其中，栅极图案403、405、407是相互平行且至少部分重叠于鳍状图案401。值得注意的是，本发明除了会利用一般光学接近修正方法(optical proximity correction method,OPC method)来修正各布局图案，以及调整两两布局图案的对应重叠的位置修正之外，本实施例更会在形成栅极图案403、405、407时，进一步进行一判读步骤，以判定出可完全横跨鳍状图案401的部分或是后续欲构成实际半导体元件布局的部分。并且，接着进行一修正步骤，以在栅极图案403、405、407中被判定为未完全横跨鳍状图案401的部分，例如是鳍状图案401的两侧或者是栅极图案405、407与前述开口图案402重叠的部分，形成如图11所示的延伸图案406、408。由此，确保后续能形成有效覆盖鳍状结构的尖端101a的栅极结构。
最后，再分别输出如图11所示包含有栅极图案403、405、407的第三布局图案，形成对应的光掩模(未绘示)，其中虚线代表相对应的开口图案402及鳍状图案401。后续，则可将该光掩模应用于各种多重曝光技术，例如两次光刻一次蚀刻制作工艺(2P1E)或是两次光刻两次蚀刻制作工艺(2P2E)。举例来说，利用图8中具有鳍状图案401的第一光掩模先对一光致抗蚀剂层(未绘示)进行一光刻暨蚀刻制作工艺，接着利用图9中具有边缘图案402的第二光掩模对该光致抗蚀剂层进行另一次的光刻暨蚀刻制作工艺，最后再利用图11中具有栅极图案403、405、407的第三光掩模对该光致抗蚀剂层再进行第三次的光刻暨蚀刻制作工艺，即可得到如前述第一实施例的图6所示的电路布局。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1. 一种半导体元件，其特征在于，包含：
多个鳍状结构，设置于一基底上，其中，该鳍状结构的至少一端具有一尖端；以及
虚置栅极结构，设置于该基底上，其中，该虚置栅极结构包含一延伸部，该延伸部覆盖该尖端，该延伸部的长度小于该虚置栅极结构的整体长度，且该延伸部的宽度大于该虚置栅极结构其他部分的宽度。
2.依据权利要求1所述的半导体元件，其特征在于，该尖端具有渐缩的宽度。
3.依据权利要求1所述的半导体元件，其特征在于，该尖端具有一斜边，该斜边与两平行侧边间分别具有一锐角及一钝角。
4.依据权利要求1所述的半导体元件，其特征在于，还包含：
多个浅沟隔离，设置在该基底并环绕该鳍状结构。
5.依据权利要求4所述的半导体元件，其特征在于，该虚置栅极结构设置在该浅沟隔离上。
6.依据权利要求4所述的半导体元件，其特征在于，该虚置栅极结构部分覆盖该浅沟隔离。
7.依据权利要求1所述的半导体元件，其特征在于，还包含：
间隙壁，设置在该虚置栅极结构的侧壁上。
8. 一种形成半导体元件的方法，其特征在于，包含以下步骤：
在一基底上形成多个环绕多个鳍状结构的浅沟隔离，其中该鳍状结构的至少一端具有一尖端；以及
在该基底上形成一虚置栅极结构，其中，该虚置栅极结构包含一延伸部，该延伸部覆盖该尖端，该延伸部的长度小于该虚置栅极结构的整体长度，且该延伸部的宽度大于该虚置栅极结构其他部分的宽度。
9.依据权利要求8所述的形成半导体元件的方法，其特征在于，该尖端具有渐缩的宽度。
10.依据权利要求8所述的形成半导体元件的方法，其特征在于，该尖端具有一斜边，该斜边与两平行侧边间分别具有一锐角及一钝角。
11.依据权利要求8所述的形成半导体元件的方法，其特征在于，该虚置栅极结构覆盖一部分的该浅沟隔离。
12.依据权利要求8所述的形成半导体元件的方法，其特征在于，该浅沟隔离的形成包含：
在该基底上形成多个浅沟槽，以定义该鳍状结构；以及
形成一绝缘层，该绝缘层至少填入该浅沟槽以形成该浅沟隔离。
13.依据权利要求8所述的形成半导体元件的方法，其特征在于，还包含：
通过一侧壁转移制作工艺在该基底上形成多个鳍状框结构；以及
进行一鳍状框结构切割制作工艺以形成该鳍状结构。
14.依据权利要求8所述的形成半导体元件的方法，其特征在于，还包含：
通过一绘图数据系统在该基底上形成一第一光掩模及一第二光掩模；以及
分别利用该第一光掩模及该一第二光掩模，形成该鳍状结构及该虚置栅极结构。
15.依据权利要求14所述的形成半导体元件的方法，其特征在于，该绘图数据系统步骤包含：
通过该绘图数据系统定义多个鳍状图案；
通过该绘图数据系统定义多个栅极图案；以及
利用该鳍状图案及该栅极图案形成该第一光掩模及该第二光掩模。
16.依据权利要求15所述的形成半导体元件的方法，其特征在于，该绘图数据系统步骤还包含：
判读步骤，以判定出该栅极图案可完全横跨该鳍状图案的部分。
17.依据权利要求16所述的形成半导体元件的方法，其特征在于，该绘图数据系统步骤还包含：
修正步骤，当该栅极图案被判定未完全横跨该鳍状图案时，进一步于该栅极图案的两侧形成一延伸图案。
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