CN110010684B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN110010684B
CN110010684B CN201810010463.4A CN201810010463A CN110010684B CN 110010684 B CN110010684 B CN 110010684B CN 201810010463 A CN201810010463 A CN 201810010463A CN 110010684 B CN110010684 B CN 110010684B
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CN110010684A (zh
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陈俊仁
吴典逸
林钰书
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United Microelectronics Corp
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Priority to CN202210974332.4A priority patent/CN115332346A/zh
Priority to US15/885,834 priority patent/US10510609B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法包括，首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域上以及一第二鳍状结构于第二区域上，形成一浅沟隔离环绕第一鳍状结构以及第二鳍状结构，形成一掩模层于第一鳍状结构上，再进行一第一退火制作工艺使第一鳍状结构的曲率半径不同于第二鳍状结构的曲率半径。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用退火制作工艺使鳍状结构具有不同曲率半径的方法。
背景技术
随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effecttransistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的形成仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
为解决上述问题，本发明公开一种制作半导体元件的方法。首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域上以及一第二鳍状结构于第二区域上，形成一浅沟隔离环绕第一鳍状结构以及第二鳍状结构，形成一掩模层于第一鳍状结构上，再进行一第一退火制作工艺使第一鳍状结构的曲率半径不同于第二鳍状结构的曲率半径。
本发明还公开一种半导体元件，其主要包含：一基底，该基底具有一第一区域以及一第二区域；以及一第一鳍状结构设于第一区域上以及一第二鳍状结构设于第二区域上，其中第一鳍状结构以及第二鳍状结构包含不同曲率半径。
附图说明
图1至图7为本发明制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 第一区域 18 第二区域
20 绝缘层 22 浅沟隔离
24 掩模层 26 第一曲面
28 第一退火制作工艺 30 第二退火制作工艺
32 第二曲面 34 第三曲面
36 栅极介电层 38 栅极材料层
R1 第一曲率半径 R2 第二曲率半径
R3 第三曲率半径
具体实施方式
请参照图1至图7，图1至图7为本发明制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon-on-insulator,SOI)基板。在本实施例中，基底12上较佳定义有第一区域16以及第二区域18，其中第一区域16以及第二区域18较佳于后续制作工艺中用来制备具有不同电场的元件，然后于形成多个鳍状结构14于基底12上。在本实施例中，分别设于第一区域16以及第二区域18上的鳍状结构14虽以四根为例，但所设置的鳍状结构数量均可依据产品需求任意调整，并不局限于此。
依据本发明的优选实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)等技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
然后形成一浅沟隔离(shallow trench isolation,STI)环绕鳍状结构14。在本实施例中，形成浅沟隔离的方式可先利用一可流动式化学气相沉积(flowable chemicalvapor deposition,FCVD)制作工艺形成一由氧化硅所构成的绝缘层20于基底12上并完全覆盖鳍状结构14。接着进行平坦化步骤，例如利用化学机械研磨(chemical mechanicalpolishing,CMP)制作工艺去除部分绝缘层20，使剩余的绝缘层20切齐鳍状结构14表面。
随后如图2所示，再利用蚀刻制作工艺去除部分绝缘层20，使剩余的绝缘层20略低于第一区域16以及第二区域18的鳍状结构14上表面以形成浅沟隔离22。
接着如图3所示，先全面性形成一掩模层24于第一区域16以及第二区域18的鳍状结构14上，然后进行一光刻及蚀刻制作工艺或图案转移制作工艺去除第二区域18的掩模层24。举例来说，可先形成一图案化掩模(图未示)，例如一图案化光致抗蚀剂覆盖第一区域16的掩模层24，然后以图案化光致抗蚀剂为掩模利用蚀刻去除第二区域18未被图案化光致抗蚀剂所覆盖的掩模层24，由此形成一图案化的掩模层24并同时暴露出第二区域18的鳍状结构14，之后再去除图案化光致抗蚀剂。在本实施例中，掩模层24较佳包含氮化硅，且用来去除部分掩模层24的蚀刻制作工艺可使用例如磷酸等蚀刻剂，但不局限于此。另外需注意的是，本实施例利用前述蚀刻去除第二区域18的掩模层24时较佳在不损害任何鳍状结构14下拔除掩模层24，因此在此阶段第二区域18的鳍状结构14上表面在拔除掩模层24之后仍为平坦表面。
然后如图4所示，进行一第一退火制作工艺28使未被掩模层24所覆盖的鳍状结构14顶部产生硅迁移(silicon migration)现象，由此改变鳍状结构14的顶部轮廓并同时调整鳍状结构的电场表面。更具体而言，由于第一区域16的鳍状结构14在进行退火制作工艺之前已被掩模层24所覆盖，因此本实施例在进行第一退火制作工艺28时较佳将第二区域18鳍状结构14顶部的平坦表面转换为一无任何平坦表面的第一曲面26，但第一区域16的鳍状结构14则无任何改变。换句话说，第二区域18的鳍状结构14顶部由于没有任何掩模层24的遮蔽或保护在经由第一退火制作工艺28产生硅迁移之后较佳由平坦表面改变为具有曲面的顶部，第一区域16的鳍状结构14顶部则在第一退火制作工艺28后未受到任何影响或产生硅迁移现象因此仍呈现平坦表面。在本实施例中，第一退火制作工艺28的温度较佳介于摄氏700度至摄氏850度且其压力较佳介于5托至300托，但均不限于此。
接着如图5所示，进行一蚀刻制作工艺，或更具体而言在不额外形成图案化掩模的情况下直接利用蚀刻去除第一区域16的掩模层24并暴露出下面的鳍状结构14。在本实施例中，用来去除掩模层24的蚀刻制作工艺可使用例如磷酸等蚀刻剂，但不局限于此。
值得注意的是，第一区域16的各鳍状结构14顶部以及第二区域18的各鳍状结构14顶部在此阶段均具有一曲率半径(radius of curvature,Rc)，其中本实施例所定义的曲率半径较佳为各鳍状结构14顶部或顶表面的任何一点至一曲率中心(center of curvature,Cc)的距离。以图5的结构为例，由于第一区域16的各鳍状结构14顶表面为平坦表面，因此第一区域16中各鳍状结构14的曲率半径较佳为无限大。第二区域16的各鳍状结构14经由前述第一退火制作工艺28加热后由平坦表面转换为第一曲面26，因此各鳍状结构14由顶表面至一曲率中心(Cc)的距离可取得一第一曲率半径R1。在此阶段，由于第一区域16各鳍状结构14的曲率半径为无限大，因此第二区域18中各鳍状结构14的第一曲率半径R1较佳小于第一区域16的各鳍状结构14曲率半径。
随后如图6所示，可选择性进行另一第二退火制作工艺30，在不额外形成掩模的情况下再次利用高温改变鳍状结构14的顶部轮廓并调整鳍状结构的电场表现。更具体而言，由于第一区域16的鳍状结构14在此阶段已无掩模层24覆盖，因此本实施例进行第二退火制作工艺30时较佳同时改变第一区域16以及第二区域18的鳍状结构14顶部轮廓，例如将第一区域16各鳍状结构14顶部的平坦表面转换为第二曲面32，同时将第二区域18各鳍状结构14的第一曲面26转换为第三曲面34，其中第二曲面32以及第三曲面34均各为完全曲面且不包含任何平坦表面。
从曲率半径的变化来看，第一区域16的各鳍状结构14顶表面较佳经由前述第二退火制作工艺30后由平坦表面转换为第二曲面32，因此各鳍状结构14由顶表面或第二曲面32任何一点至一曲率中心(Cc)的距离可取得一第二曲率半径R2。第二区域18的各鳍状结构14顶表面或第一曲面26经由前述第二退火制作工艺30后则由原本的第一曲率半径R1转换为第三曲面34的第三曲率半径R3。从细部来看，第三曲面34的第三曲率半径R3较佳小于第二曲率半径R2以及第一曲率半径R1，第二曲率半径R2与第一曲率半径R1则无太大分别，例如第二曲率半径R2可略小于或略大于第一曲率半径R1，这些变化型均属本发明所涵盖的范围。另外需注意的是，本实施例由图5至图6所绘示的第一曲率半径R1、第二曲率半径R2以及第三曲率半径R3均只概略表示曲率半径之间的大小关系，并非实际曲率半径的实际长度。另外如同前述第一退火制作工艺28，第二退火制作工艺30的温度同样可介于摄氏700度至摄氏850度且其压力较佳介于5托至300托，但均不限于此。
如图7所示，之后可依据制作工艺需求进行后续晶体管制作工艺，例如可依续形成一栅极介电层36以及一由多晶硅所构成的栅极材料层38于第一区域16以及第二区域18的鳍状结构14上，然后可依据制作工艺需求对栅极材料层38进行光刻及蚀刻制作工艺形成栅极结构，再形成间隙壁、源极/漏极区域等晶体管元件于栅极结构两侧。需注意的是，本实施例虽于进行完第二次退火制作工艺30之后才形成栅极介电层36以及栅极材料层38于鳍状结构14上，但不局限于此，本发明又可选择于图5去除掩模层24之后便直接形成栅极介电层36以及栅极材料层38于鳍状结构14上进行后续晶体管制作工艺，此实施例也属本发明所涵盖的范围。
综上所述，本发明主要先形成多个鳍状结构于基底上的第一区域以及第二区域，然后形成浅沟隔离环绕鳍状结构，再形成一掩模层并覆盖第一区域的鳍状结构上。接着进行一退火制作工艺利用高温使未被掩模层所覆盖的鳍状结构顶部产生硅迁移，由此改变鳍状结构的顶部轮廓使第一区域及第二区域的鳍状结构顶表面具有不同曲率半径，同时调整鳍状结构的电场表面，使各区域的鳍状结构适用于不同产品。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (13)

1.一种制作半导体元件的方法，其特征在于，包含：
提供一基底，该基底具有一第一区域以及一第二区域；
形成一第一鳍状结构于该第一区域上以及一第二鳍状结构于该第二区域上；
形成一浅沟隔离环绕该第一鳍状结构以及该第二鳍状结构；
形成一掩模层于该第一鳍状结构上；以及
进行一第一退火制作工艺使该第一鳍状结构的曲率半径不同于该第二鳍状结构的曲率半径。
2.如权利要求1所述的方法，另包含：
形成一绝缘层于该第一鳍状结构以及该第二鳍状结构上；以及
去除部分该绝缘层以形成该浅沟隔离。
3.如权利要求1所述的方法，其中该掩模层包含氮化硅。
4.如权利要求1所述的方法，其中各该第一鳍状结构以及该第二鳍状结构上表面包含一平坦表面。
5.如权利要求4所述的方法，另包含进行该第一退火制作工艺将该第二鳍状结构上表面转换为一第一曲面。
6.如权利要求5所述的方法，另包含于进行该第一退火制作工艺之后去除该掩模层。
7.如权利要求6所述的方法，另包含于去除该掩模层之后进行一第二退火制作工艺将该第一鳍状结构上表面转换为一第二曲面并将该第一曲面转换为一第三曲面。
8.如权利要求7所述的方法，其中该第三曲面的曲率半径小于第二曲面的曲率半径。
9.一种半导体元件，其特征在于，包含：
基底，该基底具有第一区域以及第二区域；以及
第一鳍状结构设于该第一区域上以及第二鳍状结构设于该第二区域上，其中该第一鳍状结构以及该第二鳍状结构包含不同曲率半径；以及
浅沟隔离，环绕该第一鳍状结构以及该第二鳍状结构，其中该第一鳍状结构的曲率中心低于该浅沟隔离的上表面，该第二鳍状结构的曲率中心高于该浅沟隔离的该上表面。
10.如权利要求9所述的半导体元件，另包含浅沟隔离，环绕该第一鳍状结构以及该第二鳍状结构。
11.如权利要求9所述的半导体元件，其中该第一鳍状结构上表面包含一平坦表面且该第二鳍状结构上表面包含第一曲面。
12.如权利要求9所述的半导体元件，其中该第一鳍状结构上表面包含第一曲面且该第二鳍状结构上表面包含第二曲面。
13.如权利要求12所述的半导体元件，其中该第二曲面的曲率半径小于该第一曲面的曲率半径。
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