CN106340455B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106340455B
CN106340455B CN201510388897.4A CN201510388897A CN106340455B CN 106340455 B CN106340455 B CN 106340455B CN 201510388897 A CN201510388897 A CN 201510388897A CN 106340455 B CN106340455 B CN 106340455B
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trench
fin
dummy gate
layer
fin structure
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CN106340455A (zh
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曾奕铭
梁文安
黄振铭
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/844,004 priority patent/US9653402B2/en
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Priority to US15/473,614 priority patent/US10032675B2/en
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Abstract

本发明公开一种半导体元件及其制作方法，该半导体元件包含一鳍状结构，设置于一基底上，其中，该鳍状结构具有一沟槽，一第一衬垫层，设置在该沟槽内，一第一绝缘层，位于该第一衬垫层上，以及一虚置栅极结构，位于该第一绝缘层上并横跨该沟槽，其中该虚置栅极结构的一底面与该鳍状结构的一顶面切齐。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其形成方法，尤其是涉及一种包含虚置栅极结构的半导体元件及其形成方法。
背景技术
近年来，随着场效晶体管(field effect transistors，FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor，Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering，DIBL)效应，并可以抑制短通道效应(short channel effect，SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明提供一种半导体元件，包含一鳍状结构，设置于一基底上，其中，该鳍状结构具有一沟槽，一第一衬垫层，设置在该沟槽内，一第一绝缘层，位于该第一衬垫层上，以及一虚置栅极结构，位于该第一绝缘层上并横跨该沟槽，其中该虚置栅极结构的一底面与该鳍状结构的一顶面切齐。
本发明另提供一种半导体元件的形成方法，包含：首先，提供一鳍状结构，设置于一基底上，其中，该鳍状结构具有一沟槽，接着形成一第一衬垫层在该沟槽内，然后形成一第一绝缘层于该第一衬垫层上，以及形成一虚置栅极结构于该第一绝缘层上并横跨该沟槽，其中该虚置栅极结构的一底面与该鳍状结构的一顶面切齐。
本发明的半导体元件及其形成方法，主要是利用调整沟槽的形成时序搭配设置在沟槽内的侧壁层来缩小沟槽的临界尺寸，使单一个虚置栅极结构即可同时横跨在两相邻的鳍状结构经蚀刻后的边缘与其间的沟槽之上，而提高集成度。由此，本发明可避免该沟槽的开口在形成浅沟隔离或介质层的制作工艺，例如是流动式化学气相沉积制作工艺或热氧化制作工艺，与制作工艺中提供的氧过度反应而发生该沟槽的开口扩增的情况。
附图说明
图1至图6为本发明第一实施例中形成半导体元件的方法的步骤示意图；
图7至图8为本发明的第二优选实施例的半导体元件结构示意图；
图9为本发明的第三优选实施例的半导体元件结构示意图。
主要元件符号说明
100 基底
101 鳍状结构
102 沟槽
103 沟槽
104 绝缘层
104’ 绝缘层
105 衬垫层
106 沟槽
110 图案化掩模
111 氧化硅层
112 氮化硅层
113 氧化硅层
130、150 虚置栅极结构
170 栅极结构
131、151、171 栅极介电层
132、152 栅极
133、153、173 间隙壁
172 虚置栅极
174 金属层
180 外延层
182 接触蚀刻停止层
184 介电层
186 介电层
190 接触结构
P1 平坦化步骤
S1 顶面
S2 顶面
S3 顶面
B1 底面
t1 厚度
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
请参照图1至图6，所绘示者为本发明第一实施例中形成半导体元件的方法的步骤示意图，其中，图4为半导体元件形成阶段的上视图。首先，如图1所示，提供一基底100。基底100例如是一硅基底、一含硅基底或一硅覆绝缘(silicon-on-insulator，SOI)基底等半导体基底。基底100形成有至少一鳍状结构101，在硅制作工艺(bulk silicon)的实施态样中，鳍状结构101的形成方式优选是利用一侧壁图案转移(sidewall image transfer，SIT)技术，包含通过一光刻暨蚀刻制作工艺在基底100上形成多个图案化牺牲层(未绘示)，依序进行沉积及蚀刻制作工艺，以于各该图案化牺牲层的侧壁形成一间隙壁(未绘示)，后续，去除该图案化牺牲层，并通过该间隙壁的覆盖再进行一蚀刻制作工艺，使得该间隙壁的图案被转移至单层或多层结构的一图案化掩模110，例如包含由一氧化硅(silicon oxide)层111、一氮化硅(silicon nitride)层112以及一氧化硅层113所组成的复合结构。之后，再经过一蚀刻制作工艺，将图案化掩模110的图案转移至下方的基底100中，形成多个沟槽102，同时定义出各鳍状结构101。此外，在另一实施态样中，也可再伴随一鳍状结构切割制作工艺(fin cut)形成所需的鳍状结构101，例如是彼此平行条状的鳍状结构101。
在另一实施态样中，鳍状结构101的形成方式也可选择先形成一图案化硬掩模层(未绘示)于基底100上，再利用一外延制作工艺于暴露于该图案化掩模层外的基底100上长出例如包含硅或硅锗等的半导体层(未绘示)，以作为相对应的鳍状结构。或者，在其他例如包含硅覆绝缘基底的实施态样(未绘示)中，则可利用图案化掩模110来蚀刻基底100的一半导体层(未绘示)，并停止于该半导体层下方的一底氧化层(未绘示)以形成该多个鳍状结构。
接着，如图2所示，再次通过图案化掩模110进行另一鳍状结构切割制作工艺，以蚀刻移除一部分的鳍状结构101，并在基底100上另形成一沟槽103。需注意的是，沟槽103优选具有小于沟槽102的一深度d1。举例来说，沟槽103的深度d1例如约是500埃至900埃(angstroms)，而沟槽102的深度d2则约是900埃至1200埃，但不以此为限。换句话说，在一实施态样中，形成沟槽103的制作工艺可与普遍应用的鳍状结构切割制作工艺整合，以在移除不必要的部分鳍状结构形成所需布局时，同时形成沟槽103。或者，在另一实施态样中，沟槽103也可与沟槽102一并通过一双重曝光(double patterning)或多重曝光(multiplepatterning)制作工艺，并且以显影-显影-蚀刻(photolithography-photolithography-etch，2P1E)或是显影-蚀刻-显影-蚀刻(photolithography-etch-photolithography-etch，2P2E)的操作方式进行，但不以此为限。
然后，全面性地于基底100上形成一绝缘材料层(未绘示)，优选是利用一流动式化学气相沉积(flowable chemical vapor deposition，FCVD)制作工艺，之后再搭配化学机械研磨(chemical mechanical polishing，CMP)与回蚀刻制作工艺，而在沟槽102及沟槽103内形成一绝缘层104，例如是一氧化硅。由此，使得鳍状结构101的一顶面S1与绝缘层104的一顶面S2切齐，而使得绝缘层104填满沟槽102内的形成浅沟隔离(STI)。需注意的是，在一实施态样中，在进行化学机械研磨与回蚀刻制作工艺时，可因应后续形成三栅极晶体管元件或双栅极鳍状晶体管元件等结构特性的不同，而选择性去除部分图案化掩模110(例如是氮化硅层112以及氧化硅层113)，但不以此为限。在其他实施态样中，也可选择完全保留或完全移除图案化掩模110。另外，位于鳍状结构101表面的图案化掩模110厚度t1，将可能影响位于沟槽102内的绝缘层104的厚度，因此在本发明的优选实施例中，调整图案化掩模110的厚度t1，以使得鳍状结构101的顶面S1与绝缘层104的顶面S2切齐。此外，在另一实施态样中，可进一步在形成绝缘层104之前，先全面地形成一介质层，作为衬垫层(liner)105，覆盖基底100及鳍状结构101。其中，衬垫层105例如是单层或多层结构，优选是包含氧化硅或适用的高介电常数材料等介电材质。衬垫层105的形成方式例如包含利用一临场蒸气产生技术(in situ steam generation，ISSG)，以在鳍状结构101与沟槽102的表面形成均匀分布的一衬垫层105，如图2所示，但不以此为限。在其他实施态样中，衬垫层105也可选择利用一原子层沉积(atomic layer deposition，ALD)制作工艺形成，或者是选择包含其他介电材质。
接着，再如图3及图4所示，在完全移除图案化掩模110(氧化硅层111)后，形成横跨鳍状结构101的至少一虚置栅极结构130、150。在本实施例中，形成虚置栅极结构130、150的制作工艺可与普遍应用的栅极制作工艺整合。例如可进行一栅极制作工艺，依序在鳍状结构101形成一栅极介电材料层(未绘示)，例如是包含氧化硅等绝缘材质，以及一栅极层(未绘示)，再图案化该栅极层及该栅极介电材料层，而在鳍状结构101上形成如图3所示的多个栅极结构170，包含栅极介电层171及虚置栅极172，以及虚置栅极结构130、150，分别包含栅极介电层131、151及栅极132、152。因此，在一实施态样中，虚置栅极结构130、150的栅极132、152例如为多晶硅栅极，但其材质非限于此，可视实际所需而定。后续，可继续形成环绕虚置栅极结构130、150及栅极结构170的间隙壁133、153、173，其中，间隙壁133、153、173例如是包含是氮化硅、氮氧化硅(silicon oxynitride)或氮碳化硅(silicon carbonitride)等材质。
值得说明的是，本实施例是同时形成横跨在两相邻的鳍状结构101与沟槽103之上的虚置栅极结构130，以及跨越单一鳍状结构101与部分浅沟隔离(即，位于沟槽102内的绝缘层104)的虚置栅极结构150，使虚置栅极结构130、150具有部分覆盖鳍状结构101的栅极132、152，如图3所示。其中，虚置栅极结构130的栅极132的底面B1位于绝缘层104的顶面S2切齐，也就是与鳍状结构101的顶面S1切齐，如图3所示。由此，利用虚置栅极结构130与间隙壁133覆盖在鳍状结构101经蚀刻后的边缘上，避免鳍状结构101受到后续制作工艺影响，例如是源极/漏极外延成长制作工艺，而导致结构变形、漏电流或破坏整体电性表现。此外，在另一实施态样中，也可以控制虚置栅极结构130的栅极(未绘示)宽度而使其完全或部分重叠沟槽103，而仅使间隙壁133覆盖在两相邻的鳍状结构101经蚀刻后的边缘上。
接着如图5～图6所示，至少在栅极结构170两侧的鳍状结构内形成外延层180，根据不同实施例，外延层180可包含一硅锗外延层，而适用于一PMOS晶体管，或者外延层180可包含一硅碳外延层，而适用于一NMOS晶体管。接着再进行一离子注入制作工艺以注入适当的掺质，或者于进行外延制作工艺时，同时掺杂适当的掺质，如此，外延层180便可用以作为一源/漏极区。在形成外延层180之后，可再进行一金属硅化物制作工艺(未绘示)，以在源/漏极中形成金属硅化物，其中金属硅化物制作工艺可包含前清洗制作工艺、金属沉积制作工艺、退火制作工艺、选择性蚀刻制作工艺及测试制作工艺等。然后全面性覆盖一接触蚀刻停止层182以及一介电层184于外延层180、虚置栅极结构130、150与栅极结构170上，并且进行一平坦化步骤P1，移除部分的接触蚀刻停止层182与介电层184，至少曝露出栅极结构170的顶面。
接下来，如图6所示，以一取代金属栅极制作工艺(replacement metal gate,RMG)，至少将栅极结构170中的虚置栅极172取代为金属层174。然后再次形成一介电层186覆盖于介电层184上，以及形成多个接触结构190，至少接触栅极结构170的金属层174以及源/漏极区域(例如外延层180)。此外，本发明中，虚置栅极结构130、150主要用来保护鳍状结构101，因此可能不与其他元件电连接，或是作为其他晶体管的栅极。本发明的一实施例中，若虚置栅极结构130、150与接触结构190电连接时(如图6所示)，由于沟槽103内绝缘层104与周围鳍状结构101的表面切齐，也就是说在虚置栅极结构130形成时，并不会埋入沟槽103中，如此可以降低漏电流的产生。
上述相关步骤与现有制作晶体管的步骤类似，在此不多加赘述。此外，本领域者应可轻易了解，本发明的半导体元件也可能以其他方式形成，并不限于前述的制作步骤。
本发明提供的一种半导体元件，结构可参考图6，包含有一鳍状结构101，设置于一基底100上，其中鳍状结构101具有一沟槽103；衬垫层105，设置在沟槽103内；一绝缘层104，位于衬垫层105上；以及一虚置栅极结构130，位于绝缘层104上并横跨沟槽103，其中虚置栅极结构130的底面B1与鳍状结构101的顶面S1切齐。
在本发明的一实施例中，还包含浅沟隔离(即位于沟槽102内的绝缘层104)，设置在基底100并且环绕鳍状结构101。上述浅沟隔离具有一深度d2，深度d2大于沟槽103的深度d1。
在本发明的一实施例中，虚置栅极结构130包含：一虚置栅极132，设置在沟槽103上，其中虚置栅极132的一部分填入沟槽103内；以及至少一间隙壁133，设置在鳍状结构101上，环绕虚置栅极132。
在本发明的一实施例中，还包含：一衬垫层131，设置在虚置栅极结构130的间隙壁133与鳍状结构101的表面之间。
在本发明的一实施例中，其中一衬垫层105的一顶面S3，绝缘层104的顶面S2以及鳍状结构101的顶面S1切齐。
在本发明的一实施例中，其中还包含一接触蚀刻停止层182位于鳍状结构101与虚置栅极结构130上。
在本发明的一实施例中，其中还包含至少一栅极结构170，位于鳍状结构101上，其中还包含至少一接触结构190，电连接栅极结构170。
下文将针对本发明半导体元件制作工艺的其他实施例或变化型进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
本发明第二优选实施例的半导体元件结构示意图，如图7～图8所示，与上述第一优选实施例不同之处在于，填入沟槽103的绝缘层104’材质与填入沟槽102的绝缘层104不同。优选而言，绝缘层104例如为氧化硅，而绝缘层104’例如为氮化硅，但不限于此。此外，绝缘层104的顶面(也就是浅沟隔离的表面)较鳍状结构101的顶面、以及绝缘层104’的顶面低。如此一来，后续形成栅极结构170仍可覆盖于鳍状结构101的顶面以及两侧壁，增加通道宽度(channel width)，本实施例其他后续步骤与特征与上述第一优选实施例相同，在此不另外赘述。
本发明的第三优选实施例的半导体元件结构示意图，如图9所示。为简化附图，部分元件例如衬垫层未绘示于图9中，在填入绝缘层104于沟槽后(可参考图2的剖视图)，此时绝缘层104的表面与鳍状结构101的顶面切齐。为了增加后续形成的栅极结构的通道宽度，可额外进行一蚀刻步骤，在鳍状结构101周围形成至少一沟槽106，上述沟槽106即为后续栅极结构170的形成区域(可一并参考上述第一优选实施例)，因此最终形成的栅极结构，由于同样覆盖鳍状结构101的顶面以及两侧壁，可增加通道宽度(channel width)，本实施例其他后续步骤与特征与上述第一优选实施例相同，在此不另外赘述。
综上而言，本发明的半导体元件及其形成方法，是利用调整沟槽的形成时序搭配设置在沟槽内的衬垫层来缩小沟槽的临界尺寸，使单一个虚置栅极结构即可同时横跨在两相邻的鳍状结构经蚀刻后的边缘与其间的沟槽之上，而提高集成度。由此可避免该沟槽的开口在形成浅沟隔离或介质层的制作工艺中，例如是流动式化学气相沉积制作工艺或热氧化制作工艺，与制作工艺中提供的氧过度反应而导致使沟槽临界尺寸变大的情况。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种半导体元件，包含：
鳍状结构，设置于一基底上，其中，该鳍状结构具有一沟槽；
第一衬垫层，设置在该沟槽内；
第一绝缘层，位于该第一衬垫层上；
浅沟隔离，设置在该基底并且环绕该鳍状结构；
第二沟槽，设置于该浅沟隔离的绝缘层中，位于该鳍状结构的相对两侧，且该第二沟槽的延伸方向垂直于该鳍状结构的延伸方向；
虚置栅极结构，位于该第一绝缘层上并横跨该沟槽，其中该虚置栅极结构的一底面与该鳍状结构的一顶面切齐；以及
第一栅极结构，横跨该鳍状结构并位于该第二沟槽中。
2.如权利要求1所述的半导体元件，其中，该浅沟隔离具有一深度，该深度大于该沟槽的深度。
3.如权利要求1所述的半导体元件，其中，该虚置栅极结构包含：
虚置栅极，设置在该沟槽上，其中该虚置栅极的一部分填入该沟槽内；以及
间隙壁，设置该鳍状结构上，环绕该虚置栅极。
4.如权利要求3所述的半导体元件，还包含：
第二衬垫层，设置在该虚置栅极结构的该间隙壁与该鳍状结构的表面之间。
5.如权利要求1所述的半导体元件，其中该一第一衬垫层的一顶面，该一第一绝缘层的一顶面以及该鳍状结构的一顶面切齐。
6.如权利要求1所述的半导体元件，其中还包含一接触蚀刻停止层位于该鳍状结构与该虚置栅极结构上。
7.如权利要求1所述的半导体元件，其中还包含至少一第二栅极结构，位于该鳍状结构上。
8.如权利要求7所述的半导体元件，其中还包含至少一接触结构，电连接该至少一第二栅极结构。
9.一种半导体元件的形成方法，包含：
提供一鳍状结构，设置于一基底上，其中，该鳍状结构具有一沟槽；
形成一第一衬垫层在该沟槽内；
形成一第一绝缘层于该第一衬垫层上；
形成一浅沟隔离在该基底并且环绕该鳍状结构；
形成第二沟槽于该浅沟隔离的绝缘层中，位于该鳍状结构的相对两侧，且该第二沟槽的延伸方向垂直于该鳍状结构的延伸方向；
形成一虚置栅极结构于该第一绝缘层上并横跨该沟槽，其中该虚置栅极结构的一底面与该鳍状结构的一顶面切齐；以及
形成第一栅极结构横跨该鳍状结构并位于该第二沟槽中。
10.如权利要求9所述的形成方法，其中该浅沟隔离具有一深度，该深度大于该沟槽的深度。
11.如权利要求9所述的形成方法，其中，该虚置栅极结构包含：
虚置栅极，设置在该沟槽上，其中该虚置栅极的一部分填入该沟槽内；以及
间隙壁，设置该鳍状结构上，环绕该虚置栅极。
12.如权利要求11所述的形成方法，还包含：
形成一第二衬垫层在该虚置栅极结构的该间隙壁与该鳍状结构的表面之间。
13.如权利要求9所述的形成方法，其中该一第一衬垫层的一顶面，该一第一绝缘层的一顶面以及该鳍状结构的一顶面切齐。
14.如权利要求9所述的形成方法，其中还包含形成一接触蚀刻停止层于该鳍状结构与该虚置栅极结构上。
15.如权利要求9所述的形成方法，其中还包含形成至少一第二栅极结构于该鳍状结构上。
16.如权利要求15所述的形成方法，其中还包含形成至少一接触结构，电连接该至少一第二栅极结构。
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