TWI744333B - 半導體裝置及其製程 - Google Patents

半導體裝置及其製程 Download PDF

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TWI744333B
TWI744333B TW106117128A TW106117128A TWI744333B TW I744333 B TWI744333 B TW I744333B TW 106117128 A TW106117128 A TW 106117128A TW 106117128 A TW106117128 A TW 106117128A TW I744333 B TWI744333 B TW I744333B
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layer
gate
sidewall
semiconductor device
device described
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TW201901964A (zh
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李榮原
童宇誠
陸俊岑
劉恩銓
陳冠宏
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聯華電子股份有限公司
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Priority to US15/641,236 priority patent/US10043807B1/en
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Abstract

一種半導體裝置及其製程，該半導體裝置包含多個鰭狀結構、多個閘極結構、側壁層與介電層。多個鰭狀結構設置於基底內，而多個閘極結構設置在基底上且橫跨多個鰭狀結構。側壁層設置在基底上，同時環繞多個閘極結構的側壁。介電層，設置在基底上，覆蓋多個鰭狀結構與多個閘極結構。

Description

半導體裝置及其製程
本發明是關於一種半導體裝置及其製程，尤指一種形成有應力層的半導體裝置及其製程。
近年來，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。藉此增加閘極與鰭狀結構的接觸面積，以進一步增加閘極對於載子通道區域的控制，從而抑制短通道效應(short channel effect,SCE)等問題。
一般來說，為能增加鰭狀場效電晶體元件的載子遷移率，可以選擇對於閘極通道施加壓縮應力或是伸張應力，例如是利用選擇性磊晶成長(selective epitaxial growth,SEG)技術於鰭狀基底內形成能產生合適應用的磊晶結構。然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構的設計仍存在許多瓶頸，容易導致整個元件的漏電流而 影響整體電性表現。因此如何改良現有鰭狀場效電晶體裝置與製程即為現今一重要課題。
本發明之一目的在於提供一種新穎的半導體裝置，其具有同時環繞兩閘極結構的應力層，而能具有更佳的元件可靠度。
本發明之另一目的在於提供一種新穎的半導體製程，其是形成能同時環繞兩閘極結構的應力層，以形成具有更佳可靠度之半導體裝置。
為達上述目的，本發明之另一實施例提供一種半導體裝置，其包含複數個鰭狀結構、二閘極結構、一側壁層以及一介電層。該些鰭狀結構設置於一基底內。該閘極結構設置在該基底上且橫跨該些鰭狀結構。該側壁層設置在該基底上，並同時環繞該二閘極結構的側壁。該介電層設置在該基底上，覆蓋該些鰭狀結構與該二閘極結構。
為達上述目的，本發明之另一實施例提供一種半導體裝置的製程，其包含以下步驟。首先，提供一基底，並在該基底上形成複數個閘極結構。然後，在該基底上形成二閘極結構，該二閘極結構橫跨該些鰭狀結構。接著，在該基底上形成一介電層，該介電層覆蓋該二閘極結構與該些鰭狀結構。而後，在形成該介電層後，在該基底上形成一側壁層，以同時環繞該二閘極結構。
整體來說，本發明是在各閘極結構的側壁上直接形成可同時環繞多個閘極結構的側壁層，該側壁層可選擇包含能提供適當應力的材質，例如是氮化矽等，藉此可利用該側壁層而對各閘極結構位在基底或各鰭狀結構內的通道區施加適當的應力。
100:基底
101:鰭狀結構
102:絕緣層
200:層間介電層
210:空隙層
300:閘極結構
301:閘極堆疊結構
310:閘極介電層
312:閘極
314:側壁子
316:源極/汲極區
318、328、338:側壁層
320:犧牲側壁子
348:空隙層
400:閘極結構
410:高介電常數介電層
412:功函數金屬層
414:金屬閘極
416:側壁子
418:源極/汲極區
G:間隙
T1:厚度
T2:厚度
第1圖至第8圖繪示本發明第一較佳實施例中半導體裝置的形成方法的步驟示意圖，其中：第1圖為本發明半導體裝置於形成方法之初的立體示意圖；第2圖為本發明半導體裝置於進行鰭狀結構切割製程後的立體示意圖；第3圖為本發明半導體裝置於形成側壁子後的立體示意圖；第4圖為本發明半導體裝置於形成犧牲側壁子後的立體示意圖；第5圖為本發明半導體裝置於形成源極/汲極區後的立體示意圖；第6圖為本發明半導體裝置於形成介電層後的立體示意圖；第7圖為本發明半導體裝置於移除犧牲側壁子後的立體示意圖；第8圖為本發明半導體裝置於形成側壁層後的立體示意圖。
第9圖繪示本發明第二較佳實施例中半導體裝置的立體示意圖。
第10圖繪示本發明第三較佳實施例中半導體裝置的立體示意圖。
第11圖繪示本發明第四較佳實施例中半導體裝置的立體示意圖。
為使熟習本發明所屬技術領域的一般技藝者能更進一步了 解本發明，下文特列舉本發明的數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成的功效。
請參照第1圖至第8圖，所繪示者為本發明第一較佳實施例中半導體裝置之製程的步驟示意圖。首先，如第1圖所示，提供一基底100，例如是一矽基底、一含矽基底或一矽覆絕緣(silicon-on-insulator,SOI)基底等半導體基底，基底100形成有至少一鰭狀結構101。在矽製程(bulk silicon)的實施態樣中，鰭狀結構101的形成方式例如是利用一側壁圖案轉移(sidewall image transfer,SIT)技術，包含透過一微影暨蝕刻製程在基底100上形成複數個圖案化犧牲層(未繪示)，依序進行沉積及蝕刻製程，以於各該圖案化犧牲層的側壁形成一側壁子(未繪示)，後續，去除該圖案化犧牲層，並透過該側壁子的覆蓋再進行一蝕刻製程，而在基底100內形成複數個淺溝渠(shallow trench，未繪示)，並同時定義出各鰭狀結構101。然後，依序進行沉積與回蝕刻製程，在該些淺溝渠內形成一絕緣層102,構成淺溝渠隔離(shallow trench isolation,STI)。然而，在其他實施例中，鰭狀結構101的形成方式也可選擇先形成一圖案化硬遮罩層(未繪示)於基底100上，再利用一磊晶製程於暴露於該圖案化遮罩層外的基底100上長出例如包含矽或矽鍺等的半導體層(未繪示)，以作為相對應的鰭狀結構。或者，在其他例如包含矽覆絕緣基底的實施態樣(未繪示)中，則可利用該側壁子來蝕刻基底100的一半導體層(未繪示)，並停止於該半導體層下方的一底氧化層(未繪示)以形成該等鰭狀結構(未繪示)。
接著，形成橫跨鰭狀結構101的閘極結構300。在本實施例 中，閘極結構300較佳是一多晶矽閘極，而其製程可與普遍應用的閘極製程整合。詳細來說，例如是先在鰭狀結構101形成一閘極介電層(未繪示)，例如是包含氧化矽等絕緣材質，以及一閘極層(未繪示)，再圖案化該閘極層及該閘極介電層，形成如第1圖所示的閘極堆疊結構301，其是沿著一方向(未繪示)延伸。該方向較佳是垂直於各鰭狀結構101的延伸方向，但不以此為限。閘極堆疊結構301包含由下而上依序堆疊的閘極介電層310及閘極312。之後，再次圖案化閘極堆疊結構301，使閘極堆疊結構301形成同時沿著該方向延伸的兩部分，且各部分的閘極堆疊結構301之間是相互分隔設置並分別橫跨一部分的鰭狀結構101，如第2圖所示。最後，形成覆蓋基底100、鰭狀結構101與閘極堆疊結構301的一側壁材料層(未繪示)，例如是包含氧化矽(SiO)或氮氧化矽(SiON)等絕緣材質，再經過回蝕刻製程，而在各部分的閘極堆疊結構301側壁形成環繞各部分閘極堆疊結構301的側壁子314，如第3圖所示。由此，即形成沿著該方向延伸的兩閘極結構300，並分別橫跨一部分的鰭狀結構101，如第3圖所示。其中，兩閘極結構300在該方向上是相互分隔設置且各閘極結構300之間具有一間隙G。也就是說，在本實施例中，兩閘極結構300之一的一端(短邊端)隔著間隔G相對於另一個閘極結構300的一端(短邊端)，如第3圖所示。
然而，閘極結構300的製程並非僅限於前述，在另一實施例中，可選擇在形成閘極堆疊結構301後，先形成環繞整個閘極堆疊結構301的一側壁子(未繪示)，再圖案化閘極堆疊結構301與該側壁子，來形成分隔設置的兩閘極結構(未繪示)。藉此，各該閘極結構的一側未被該側壁子環繞，也就是說，環繞各該閘極結構的該側壁子是呈現一 U型狀(未繪示)。
繼續形成一犧牲側壁子320。詳細來說，例如是形成覆蓋基底100、鰭狀結構101與閘極結構300的另一側壁材料層(未繪示)，例如是包含氮化矽(SiN)、碳氮化矽(SiCN)等與側壁子314材質具顯著蝕刻選擇的絕緣材質，使該側壁材料層可覆蓋各閘極結構300的所有側壁，包含前述兩閘極結構300的兩相對端，並填滿各閘極結構300之間的間隙G，再經過回蝕刻製程，而在各閘極結構300的側壁形成同時環繞兩分隔閘極結構300的犧牲側壁子320，如第4圖所示。犧牲側壁子320填滿間隙G的部分相較於其他部分具有較厚的一厚度T1，其約為其他部分厚度T2的3倍至5倍以上，但不以此為限。
然後，如第5圖所示，在各閘極結構300兩側的鰭狀結構101內，形成源極/汲極區316。源極/汲極區316的形成例如是依序進行一蝕刻製程與一選擇性磊晶成長(selective epitaxial growth,SEG)製程，以在各閘極結構300兩側的鰭狀結構101內分別形成一磊晶層(未繪示)，例如包含(silicon germanium,SiGe)、矽化鍺硼(silicon-germanium-boron,SiGeB)、碳化矽(silicon carbide,SiC)或碳磷化矽(silicon carbide-phosphate,SiCP)等合適的材質。該磊晶層可選擇在進行該選擇性磊晶成長製程時同步(in-situ)進行一離子摻雜製程，在該磊晶層內植入適當的摻質，以作為源極/汲極區316。或者，在其他實施例中，也可選擇在進行該選擇性磊晶成長製程後，再額外進行離子摻雜製程；或直接省略該磊晶層，而在閘極結構300兩側的鰭狀結構101內進行離子佈植製程，作為源極/汲極區(未繪示)；或 不蝕刻鰭狀結構101，而直接進行該選擇性磊晶成長，以於各閘極結構300兩側的鰭狀結構101上直接形成一磊晶層(未繪示)，作為該源極/汲極區。
此外，需注意的是，在本實施例中，源極/汲極區316是緊鄰環繞兩閘極結構300的犧牲側壁子320而形成的，使源極/汲極區316並不會重疊於源極/汲極區316，如第5圖所示。然而，在另一實施例中，可選擇在側壁子314形成後，先在閘極結構300兩側的鰭狀結構101內形成緊鄰側壁子314的源極/汲極區(未繪示)，再形成可同時環繞多個閘極結構300的犧牲側壁子(未繪示)。在此狀況下，該犧牲側壁子則會部分重疊位在下方的該源極/汲極區(未繪示)。
如第6圖所示，在基底100上形成一層間介電層200，例如是包含氧化矽或其他與犧牲側壁子320的材質具顯著蝕刻選擇的介電材質。其中，層間介電層200是直接覆蓋在各鰭狀結構101與閘極結構300上，使其頂表面可與閘極結構300或犧牲側壁子320的頂表面齊平，而其底部則會直接接觸基底100與鰭狀結構101的頂表面。再接著進行一置換製程，形成一側壁層318來取代之前形成的犧牲側壁子320。詳細來說，在層間介電層200形成後，可先進行一蝕刻製程，利用層間介電層200與犧牲側壁子320形成材質之間的顯著蝕刻選擇，完全移除犧牲側壁子320。由此，可在原本形成犧牲側壁子320的位置形成同時環繞兩閘極結構300的一空隙(air gap)層210，如第7圖所示。
之後，形成填滿空隙層210的側壁層318。側壁層318即形成 在原本形成犧牲側壁子320或空隙層210的位置，而能同時環繞兩閘極結構300。側壁層318同樣是覆蓋在各閘極結構300的所有側壁上，包含前述兩閘極結構300的兩相對端，並填滿各閘極結構300之間的間隙G。並且，側壁層318填滿間隙G的部分相較於其他部分同樣具有較厚的厚度T1，其約為其他部分厚度T2的3倍至5倍以上，但不以此為限。此外，原先緊鄰犧牲側壁子320而形成的源極/汲極區316，此時則緊鄰側壁層318設置，如第8圖所示。在本實施例中，側壁層318較佳是包含能提供適當應力的絕緣材質，以對各閘極結構300位在各鰭狀結構101內的通道區施加適當的應力。舉例來說，當各閘極結構300預計形成具P型導電型的電晶體結構時，側壁層318例如是包含能提供壓縮應力(compressive stress)的絕緣材質，例如是能提供壓縮應力的氮化矽(compressive stress nitride)，以作為一壓縮應力層而施加一壓縮應力層至該電晶體結構的通道區；而當各閘極結構300預計形成具N型導電型的電晶體結構時，側壁層318例如是包含能提供伸張應力(tensile stress)的絕緣材質，例如是能提供伸張應力的氮化矽(tensile stress nitride)，以作為一拉伸應力層而施加一拉伸應力層至該電晶體結構的通道區，但不以此為限。
需注意的是，本實施例應是先透過犧牲側壁子320定義出側壁層318的預計形成位置，再於介電層200形成後，正式形成可做為應力層的側壁層318。因此，側壁層318可具有完整的元件外型，且側壁層318的外型較不會像一般側壁子(如側壁子314)受到回蝕刻等製程的影響，而可能具有不完整的外型，如圓弧側壁(未繪示)。舉例來說，側壁層318在垂直於基底100的一剖面上是呈現I字型狀，如第8圖所 示，或者，其還可進一步覆蓋在側壁子314受到回蝕刻製程影響而形成的該圓弧側壁上，使側壁層318在垂直於基底100的一剖面上是呈現上大下窄的I字型狀(未繪示)，以補償側壁子314的結構缺陷。另一方面，側壁層318是直接形成在側壁子314上，而可較為貼近各閘極結構300通道區，以利於施加其應力效果。然而，在其他實施例中，亦可選擇在一開始，例如是在側壁子314形成後，直接以能提供合適應力的材質來形成該側壁層(未繪示)，以簡化整體製程。或者，在另一實施例中，也可選擇在移除犧牲側壁子320時，同時移除側壁子314，而形成能更貼近各閘極結構300通道區的側壁層(未繪示)。
由此，即完成本發明較佳實施例中半導體裝置的製程。而在後續製程中，則可進行一金屬閘極置換(replacement metal gate,RMG)製程，將閘極結構300的閘極312與閘極介電層310轉換為一高介電常數(high dielectric constant,high-k)介電層(未繪示)、一功函數金屬層(未繪示)，例如是包含鉭與氮化鉭(Ta/TaN)或鈦與氮化鈦(Ti/TiN)等金屬材質，以及一金屬閘極(未繪示)等，例如是包含銅(Cu)或鎢(W)等低阻質的金屬材質。
依據本實施例的製程，是在閘極結構300形成後，先形成環繞可同時環繞多個閘極結構300的犧牲側壁子320，並且使犧牲側壁子320可進一步填滿各閘極結構300之間的間隙G，來定義出後續側壁層318的形成位置。再於層間介電層200形成後，進行置換製程，將犧牲側壁子320置換為側壁層318，以確保側壁層318的結構完整不受損。側壁層318較佳是包含能提供適當應力的絕緣材質，如經處理後的氮化矽 等，而能作為一壓縮應力層或拉伸應力層，提供相對應的應力給位在各閘極結構300下方的通道區，藉此有效提升本發明之半導體裝置的元件效能。
然而，本領域者應可輕易了解，本發明的半導體裝置亦可能以其他方式形成，並不限於前述的製作步驟或結構。是以，下文將進一步針對本發明半導體裝置及其形成方法的其他實施例或變化型進行說明。且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重覆贅述。此外，本發明之各實施例中相同之元件係以相同之標號進行標示，以利於各實施例間互相對照。
請參照第9圖所示，其繪示本發明第二實施例中形成半導體裝置的示意圖。本實施例的半導體裝置的形成方法大體上和前述第一實施例中第1圖至第6圖所示步驟相同。然而，在本實施例中，該側壁層是由兩個部分組成，也就是分別環繞二分隔之閘極結構300的兩側壁層328、338，且兩側壁層328、338的一側相互鄰接，如第9圖所示。
具體來說，在移除犧牲側壁子320之前，可先形成覆蓋其中一閘極結構300與一部分犧牲側壁子320的一遮罩(未繪示)，並在該遮罩的覆蓋下，先移除環繞另一閘極結構300的犧牲側壁子320，再形成側壁層328來取代原先的犧牲側壁子320。移除該遮罩後，則形成覆蓋另一閘極結構300的另一遮罩(未繪示)，藉由該另一遮罩的覆蓋，移除剩餘的犧牲側壁子320，再接著形成側壁層338。其中，側壁層328、338可配合兩閘極結構300的導電型式而包含皆提供伸張應力或壓縮應 力的不同絕緣材質，或者，亦可選擇包含可分別提供伸張應力與壓縮應力的絕緣材質，但不以此為限。藉此，本實施例的兩個閘極結構300可被能提供伸張應力或壓縮應力的側壁層328、338分別環繞，或者，也可分別被同時具有伸張應力或壓縮應力但材質不同的側壁層328、338分別環繞，而使兩個閘極結構300的通道區能配合其預計形成的電晶體形式而呈現多樣化的元件效能。
請參照第10圖所示，其繪示本發明第三實施例中形成半導體裝置的示意圖。本實施例的半導體裝置的形成方法大體上和前述第一實施例中第1圖至第6圖所示步驟相同。然而，在本實施例中，該側壁層同樣是由兩個部分組成，其中，側壁層328僅環繞其中一閘極結構300，而另外一閘極結構300仍處於被空隙層348環繞的樣態，如第10圖所示。
詳細來說，在移除犧牲側壁子320之前，同樣是先形成覆蓋其中一閘極結構300與一部分犧牲側壁子320的一遮罩(未繪示)，並在該遮罩的覆蓋下，移除環繞另一閘極結構300的犧牲側壁子320，並形成側壁層328來取代原先的犧牲側壁子320。之後，在移除該遮罩後，直接選擇性地移除剩餘的犧牲側壁子320，形成空隙層348。最後，再於其上形成一介電層(未繪示)，整體性地覆蓋在層間介電層200、空隙層348與側壁層328上。藉此，本實施例的兩個閘極結構300，則是分別被能提供伸張應力或壓縮應力的側壁層328，以及不具無法提供任何應力的空隙層348環繞，而使兩個閘極結構300的通道區能配合其預計形成的電晶體形式而呈不同的元件效能。
請參照第11圖所示，其繪示本發明第四實施例中形成半導體裝置的示意圖。在本實施例中，是直接形成具有金屬閘極的閘極結構400，其包含依序堆疊的一高介電常數介電層410、一阻障層(未繪示)、一功函數金屬層412與一金屬閘極414，以及環繞高介電常數介電層410、該阻障層、功函數金屬層412與金屬閘極414的側壁子416，再圖案化閘極結構400，使其形成相互分隔設置的兩部分，且各部分的閘極結構400分別橫跨一部分的鰭狀結構101。
之後，再形成同時環繞兩閘極結構400的一犧牲側壁子(未繪示)、位於各閘極結構400兩側的源極/汲極區318，以及覆蓋基底100的層間介電層200，並透過一置換製程將該犧牲側壁子取代為一側壁層318，如第11圖所示。在本實施例中，側壁層318同樣可選擇包含能提供適當應力的材質，例如是矽鍺、矽碳或矽磷等，以對各閘極結構400位在各鰭狀結構101內的通道區施加適當的應力。藉此，使側壁層318可作為一壓縮應力層或拉伸應力層，提供相對應的應力給位在各閘極結構400下方的通道區，藉此有效提升本發明之半導體裝置的元件效能。此外，在本實施例中還可使該側壁層進一步覆蓋在閘極結構400的頂表面上，使該側壁層在垂直於基底100的一剖面上是呈現上ㄇ字型狀(未繪示)，以提供更均勻的應力給位在各閘極結構400下方的通道區。
此外，本領域者應可輕易理解，前述實施例雖皆是透過形成一犧牲層搭配進行一置換製程的方式來形成各側壁層318、328、338， 但其形成方式並不限於此。在其他實施例中，也可省略該犧牲層，而在形成層間介電層200後，利用一微影蝕刻製程來定義出各側壁層318、328、338預定形成位置，最後再利用沉積製程與回蝕刻製程，形成各側壁層318、328、338。
整體來說，本發明是在各閘極結構的側壁上直接形成可同時環繞多個閘極結構的側壁層，該側壁層可選擇包含能提供適當應力的材質，例如是矽鍺、矽碳或矽磷等，藉此可利用該側壁層而對各閘極結構位在基底或各鰭狀結構內的通道區施加適當的應力。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:基底
101:鰭狀結構
102:絕緣層
200:層間介電層
300:閘極結構
312:閘極
314:側壁子
316:源極/汲極區
318:側壁層
T1:厚度
T2:厚度

Claims (18)

  1. 一種半導體裝置，其特徵在於包含：複數個鰭狀結構，設置於一基底內；二閘極結構，設置於該基底上且橫跨該些鰭狀結構，該二閘極結構是延伸於同一方向上且在該方向上相互分隔，且該二閘極結構之一的第一端在該方向上相對於該二閘極結構之另一的第二端，各該閘極結構包含一閘極以及環繞該閘極的一側壁子；一側壁層，設置在該基底上，該側壁層同時環繞該二閘極結構的側壁，並同時覆蓋該二閘極結構的該第一端與該第二端，並且，該側壁層同時環繞該二閘極結構的該二側壁子，該側壁層具有能提供應力的絕緣材質；以及一介電層，設置在該基底上，並環繞該側壁層。
  2. 如申請專利範圍第1項所述之半導體裝置，其特徵在於，該介電層與該側壁層直接接觸該鰭狀結構。
  3. 如申請專利範圍第1項所述之半導體裝置，其特徵在於，該二閘極結構的該第一端與該第二端之間具有一間隙，該側壁層填滿該間隙。
  4. 如申請專利範圍第1項所述之半導體裝置，其特徵在於，各該閘極結構包含二源極/汲極區，該二源極/汲極區分別設置在各該閘極結構兩側的鰭狀結構內。
  5. 如申請專利範圍第4項所述之半導體裝置，其特徵在於，該二源極/汲極區緊鄰該側壁層。
  6. 如申請專利範圍第1項所述之半導體裝置，其特徵在於，該側壁層包含分別環繞該二閘極結構的一第一部份及一第二部份。
  7. 如申請專利範圍第6項所述之半導體裝置，其特徵在於，該第一部份包含應力氮化矽，以提供一拉伸應力至一N型導電型電晶體結構的通道區。
  8. 如申請專利範圍第6項所述之半導體裝置，其特徵在於，該第二部份包含應力氮化矽，以提供一壓縮應力至一P型導電型電晶體結構的通道區。
  9. 如申請專利範圍第6項所述之半導體裝置，其特徵在於，該第一部份包含應力氮化矽，以提供一拉伸應力或壓縮應力至一電晶體結構的通道區。
  10. 如申請專利範圍第6項所述之半導體裝置，其特徵在於，該第一部分包含一空隙層。
  11. 如申請專利範圍第6項所述之半導體裝置，其特徵在於，該第一部份與該第二部分彼此接觸。
  12. 一種半導體裝置的製程，其特徵在於包含下列步驟：提供一基底；在該基底上形成二閘極結構，該二閘極結構橫跨該些鰭狀結構，其中，該二閘極結構是延伸於同一方向上且在該方向上相互分隔，且該二閘極結構之一的第一端在該方向上相對於該二閘極結構之另一的第二端；在該基底上形成一介電層，該介電層覆蓋該二閘極結構與該些鰭狀結構；以及在形成該介電層後，在該基底上形成一側壁層，同時環繞該二閘極結構，該側壁層同時覆蓋該二閘極結構的該第一端與該第二端，該側壁層具有能提供應力的絕緣材質。
  13. 如申請專利範圍第12項所述之半導體裝置的製程，其特徵在於，形成該側壁層的步驟包含：形成一犧牲側壁子，該犧牲側壁子環繞該二閘極結構；移除該犧牲側壁子，形成環繞該二閘極結構的一空隙層；形成該側壁層，填滿該空隙層。
  14. 如申請專利範圍第13項所述之半導體裝置的製程，其特徵在於，該介電層是在該犧牲側壁子形成之後形成。
  15. 如申請專利範圍第13項所述之半導體裝置的製程，其特徵在於，該介電層是在該犧牲側壁子移除之前形成。
  16. 如申請專利範圍第13項所述之半導體裝置的製程，其特徵在於，更包含：形成二源極/汲極區，該二源極/汲極區分別設置在各該閘極結構兩側的鰭狀結構內，鄰接該犧牲側壁子。
  17. 如申請專利範圍第16項所述之半導體裝置的製程，其特徵在於，形成該二源極/汲極區的步驟包含：進行一選擇性磊晶成長製程，形成該二源極/汲極區。
  18. 如申請專利範圍第12項所述之半導體裝置的製程，其特徵在於，形成該二閘極結構的步驟包含：在該基底上形成一閘極介電層與一閘極層，覆蓋該些鰭狀結構；圖案化該閘極介電層與該閘極層，形成二堆疊結構；以及形成二側壁子，分別環繞該二堆疊結構，以形成該二閘極結構。
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