TW201413920A - 具有電介質襯裡之高電壓三維裝置 - Google Patents

具有電介質襯裡之高電壓三維裝置 Download PDF

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TW201413920A
TW201413920A TW102120901A TW102120901A TW201413920A TW 201413920 A TW201413920 A TW 201413920A TW 102120901 A TW102120901 A TW 102120901A TW 102120901 A TW102120901 A TW 102120901A TW 201413920 A TW201413920 A TW 201413920A
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gate
fin active
dielectric layer
dielectric
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TW102120901A
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TWI567943B (zh
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Walid M Hafez
Jeng-Ya D Yeh
Curtis Tsai
Joo-Dong Park
Chia-Hong Jan
Gopinath Bhimarasetti
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Intel Corp
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    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

說明具有電介質襯裡的高電壓三維裝置以及具有電介質襯裡的高電壓三維裝置的形成方法。舉例而言，半導體結構包含配置在上述基底上方的第一鰭主動區以及第二鰭主動區。第一閘極結構配置在第一鰭主動區的上表面上方、以及延著第一鰭主動區的側壁。第一閘極結構包含第一閘極電介質、第一閘極電極、及第一間隔器。第一閘極電介質由配置在第一鰭主動區上及延著第一間隔器側壁之第一電介層、以及配置在第一電介層上及延著第一間隔器側壁之第二、不同的電介層構成。半導體結構也包含配置在第二鰭主動區的上表面上方、以及延著第二鰭主動區的側壁之第二閘極結構。第二閘極結構包含第二閘極電介質、第二閘極電極、及第二間隔器。第二閘極電介質由配置在第二鰭主動區上及延著第二間隔器側壁之第二電介層構成。

Description

具有電介質襯裡之高電壓三維裝置
本發明的實施例是半導體裝置及製程的領域，特別關於具有電介質襯裡的高電壓三維裝置及有電介質襯裡的高電壓三維裝置的形成方法。
在過去數十年，積體電路的特徵比例一直是成長的半導體產業背後的推力。愈來愈小的特徵比例能夠在半導體晶片的有限不動產上增加功能單元的密度。舉例而言，縮小的電晶體尺寸允許將增加數目的記憶體裝置或邏輯裝置併入於晶片上，導致以增加容量製造產品。但是，對於愈來愈多的容量之推動一直是議題。使各裝置的性能最佳化的需求愈來愈重要。
在製造積體電路裝置時，隨著裝置尺寸持續縮小，例如三閘極電晶體等多閘極電晶體變得愈來愈重要。在習知的製程中，三閘極電晶體一般製於塊體矽基底或是絕緣體上矽基底上。在某些情形中，塊體矽基底由於較低成本且因為它們能夠使三閘極製程較不複雜，所以是較佳的。在 其它情形中，絕緣體上矽基底由於增進的三閘極電晶體的短通道表現，所以是較佳的。
但是，將多閘極電晶體比例化並不是沒有結果。隨著微電子電路的這些元件的尺寸降低以及隨著在給定區域中製造的元件的數目的急遽增加，用以圖型化這些元件的微影製程的限制變得很重要。特別地，在半導體堆疊(關鍵尺寸)中圖型化的特徵之最小尺寸與這些特徵之間的間隔之間有代價。
100A‧‧‧標準高電壓電晶體
100B‧‧‧比例化高電壓電晶體
102A‧‧‧閘極電極
102B‧‧‧閘極電極
104A‧‧‧接點
104B‧‧‧接點
106A‧‧‧高電壓閘極電介質
106B‧‧‧高電壓閘極電介質
108A‧‧‧基底
108B‧‧‧基底
200A‧‧‧標準低電壓電晶體
200B‧‧‧標準高電壓電晶體
200C‧‧‧低電壓電晶體
200D‧‧‧比例化高電壓電晶體
202A‧‧‧閘極電極
202B‧‧‧閘極電極
202C‧‧‧閘極電極
202D‧‧‧閘極電極
204A‧‧‧接點
204B‧‧‧接點
204C‧‧‧接點
204D‧‧‧接點
206A‧‧‧低電壓閘極電介質
206B‧‧‧高電壓閘極電介質
206C‧‧‧低電壓閘極電介質
206D‧‧‧高電壓閘極電介質
208A‧‧‧基底
208B‧‧‧基底
208C‧‧‧基底
208D‧‧‧基底
210A‧‧‧間隔器
210B‧‧‧間隔器
210C‧‧‧間隔器
210D‧‧‧間隔器
212A‧‧‧層間電介材料
212B‧‧‧層間電介材料
300A‧‧‧標準高電壓電晶體
300B‧‧‧比例化高電壓電晶體
300C‧‧‧比例化高電壓電晶體
302A‧‧‧閘極電極
302B‧‧‧閘極電極
302C‧‧‧閘極電極
304A‧‧‧接點
304B‧‧‧接點
304C‧‧‧接點
306A‧‧‧高電壓閘極電介質
306B‧‧‧高電壓閘極電介質
306C‧‧‧高電壓閘極電介質
308A‧‧‧基底
308B‧‧‧基底
308C‧‧‧基底
310A‧‧‧間隔器
310B‧‧‧間隔器
310C‧‧‧間隔器
312A‧‧‧層間電介材料
314C‧‧‧間隔器
400‧‧‧結構
402‧‧‧基底
404‧‧‧鰭
406‧‧‧隔離電介層
408‧‧‧假閘極結構
410‧‧‧間隔器
412‧‧‧接點
412A‧‧‧接點區
414‧‧‧隔離區
416‧‧‧內部間隔器電介質襯裡
418‧‧‧永久閘極電極
500‧‧‧計算裝置
502‧‧‧主機板
504‧‧‧處理器
506‧‧‧通訊晶片
圖1顯示根據本發明的實施例之(A)標準高電壓電晶體及(B)比例化高電壓電晶體的剖面視圖。
圖2A顯示標準的低電壓電晶體的剖面視圖。
圖2B顯示標準的高電壓電晶體的剖面視圖。
圖2C顯示根據本發明的實施例之在間距比例化之後低電壓電晶體的剖面視圖。
圖2D顯示根據本發明的實施例之比例化的高電壓電晶體的剖面視圖。
圖3顯示根據本發明的實施例之(A)標準高電壓電晶體、(B)比例化高電壓電晶體、及(C)具有內電介質間隔器的比例化高電壓電晶體的剖面視圖。
圖4A-4F顯示根據本發明的實施例之代表半導體結構的製造方法之不同操作的剖面視圖，其中：圖4A顯示包含形成在基底402上方的眾多鰭之啟始 結構；圖4B顯示形成為與圖4A的眾多鰭正交之眾多假閘極結構；圖4C顯示形成在圖4B的眾多假閘極結構的閘極之間的接點及/或隔離區；圖4D顯示移除眾多假閘極，留下圖4C的接點及圖4A的眾多鰭曝露；圖4E顯示與圖4D的結構保形之內部間隔器電介質襯裡的形成；以及圖4F顯示圖4E的內部間隔器電介質襯裡上或上方的眾多永久閘極電極的形成。
圖5顯示根據本發明的實施之計算裝置。
說明具有電介質襯裡的高電壓三維裝置及具有電介質襯裡的高電壓三維裝置的形成方法。在下述說明中，揭示眾多具體細節，例如特定集成及材料系，以助於完整瞭解本發明的實施例。習於此技藝者將瞭解，不用這些特定細節，仍可實施本發明的實施例。在其它情形中，未詳述例如積體電路設計佈局等習知特點，以免不必要地模糊本發明的實施例。此外，須瞭解，圖式中所示的各實施例是說明表示且不一定依比例繪製。
本發明的一或更多實施例關於包含電介質襯裡的結構或其形成，所述結構包含電介質襯裡以便能夠在例如積極 比例化的鰭式場效電晶體(finFET)等積極比例化的三維裝置架構上製造高電壓電晶體。舉例而言，在三維半導體本體上製造的閘極對準接點處理流程留下些許或沒有餘裕給裝置崩潰。如此，為了形成厚閘極電介層之基底矽消耗不再是用於形成用於此高電壓裝置的閘極電介層之可實行的選項。
此處所述的一或更多實施例克服積極比例化的非平面(例如，三維)電晶體架構上雙電壓技術的有關議題。根據莫爾(Moore)定律的要求，各世代之閘極間距應依約0.7的因數比例化以符合電晶體密度要求。此間距比例化的結果是閘極接點與源極/汲極接點之間的隔離厚度每一世代都會縮減。系統晶片(SoC)技術典型地依靠多電壓軌以便能夠造成所需的確保，特別是假使類比及/或RF通訊特點存在時。但是，習知的製造方式無法支援高度比例化製程技術上的此高電壓。
更具體而言，積極比例化技術的高電壓電晶體會遭受閘極與源極/汲極之間過早的裝置故障，而不是所需的閘極對基底機制。此過早故障導因於閘極至接點分離的接近以及可能是隔離間隔器材料之不良絕緣體品質。關於涉及的概念之實施例，圖1顯示根據本發明的實施例之(A)標準高電壓電晶體100A及(B)比例化高電壓電晶體100B的剖面視圖。
參考圖1，高電壓電晶體100A和100B分別包含閘極電極102A和102B、接點104A和104B、以及分別形成基 底108A和108B上的高電壓閘極電介質106A和106B。如圖1中所示，由於間隔的結果，在比例化的裝置100B中閘極102B與接點104B之間的近接降低(與裝置100A相比)。此間隔縮減在比例化的裝置中的閘極與接點之間造成不希望的優先崩潰路徑。
在特定實例中，為了說明目的，22nm技術可以可靠地支援閘極與源極和汲極(S/D)接點之間高達1.8伏特(V)。但是，由於導因於不充份的閘極電介材料之S/D接點與閘極之間過早的故障，而不支援3.3V非堆疊閘極解決方式。因此，未來節點(例如，14nm節點)無法如由22nm技術為基礎的裝置般支援達到1.8V的電軌。在14nm節點上能夠造成高電壓裝置的一解決方式是實質地放寬間距(例如，使得接點能夠設成更遠離閘極)。但是，放寬的間距無法與比例化密度共容，造成不希望的隱含面積及成本。又關於涉及的概念的實例，圖2顯示根據本發明的實施例之(A)標準的低電壓電晶體200A、(B)標準的高電壓電晶體200B、(C)間距比例化之後標準的低電壓電晶體200C、以及(D)比例化的高電壓電晶體200D的剖面視圖。
參考圖2，低電壓電晶體200A和200C分別包含閘極電極202A和202C、接點204A和204C、低電壓閘極電介質206A和206C、以及分別形成於基底208A和208C上的間隔器210A和210C。低電壓電晶體200A也包含某些層間電介質(ILD)材料212A，而低電壓電晶體200C則 否。同時，高電壓電晶體200B和200D分別包含閘極電極202B和202D、接點204B和204D、高電壓閘極電介質206B和206D、以及分別形成在基底208B和208D上的間隔器210B和210D。高電壓電晶體200B也包含某些ILD材料212B，而高電壓電晶體200D則否。如圖2所示，相較於標準電晶體200A和200B，比例化的電晶體200C和200D之閘極對接點間隔實質縮減。此閘極對接點間隔的縮減不利地影響可靠度，特別是高電壓可靠度。
因此，此處所述的一或更多實施例，在內間隔器製程的製造期間，能夠造成高電壓閘極至源極/汲極支援。在特定實施例中，方式使用更換金屬閘極流程以提供增加的電介質餘裕給比例化的高電壓裝置。關於涉及的概念的實例，圖3顯示根據本發明的實施例之(A)標準高電壓電晶體300A、(B)比例化高電壓電晶體300B、及(C)具有內電介質間隔器的比例化高電壓電晶體300C的剖面視圖。
參考圖3，高電壓電晶體300A、300B和300C分別包含閘極電極302A、302B和302C、接點304A、304B和304C、高電壓閘極電介質306A、306B和306C、以及分別形成在基底308A、308B和308C上的間隔器310A、310B和310C。標準的高電壓電晶體300A也包含某些ILD材料312A，而比例化的高電壓電晶體300B和300C則否。此外，根據本發明的實施例，比例化的高電壓電晶體300C包含例如內電介質襯裡層的形式之內間隔器 314C。
更具體而言，再參考圖3，標準的高電壓電晶體300A具有閘極電介層(306A)，閘極電介層(306A)是熱生長的氧化物及高k電介質層的混合成分。在接點304A與閘極材料302A之間的間隔包含保形地沈積的高k電介層(延著側壁的306A)、間隔器及/或氮化物蝕刻阻擋層(NESL)310A、及餘留的ILD氧化物312A。比例化的高電壓電晶體300B容納間距縮減，其將接點304B設置成接近閘極302B。如同配合圖1及2之上述所述般，裝置300B的配置雖然容易適合低電壓電晶體，但是因不良的可靠度而與高電壓操作不共容。特別地，參考裝置300B，相較於300A，間隔器310B的厚度已降低，以及，ILD實質降低(或者如同所示般，甚至消除)。在實施例中，如同所示，比例化高電壓電晶體300C包含高電壓閘極電介質306C(沈積以形成內間隔器314C)以及高k電介層。在一此實施例中，僅與高k層相對立的二保形層的沈積提供支援可靠的高電壓操作所需的餘裕。因此，相較於300B，300C的配置增加閘極302C至接點304C的間隔，這是支援相當高電壓供應所需的。
如此，高電壓閘極電介層的製造包含一層以上的電介質襯裡層的形成，以提供閘極材料與相鄰的源極及/或汲極接點之間的側壁間隔。舉例而言，圖4A-4F顯示代表根據本發明的實施例之製造半導體結構的方法中之不同操作的剖面視圖，方法包含產生氧化物襯裡間隔器的方法。
參考圖4A，啟始結構400包含形成於基底402上方的眾多鰭404(例如，三維半導體本體)。鰭部由隔離電介層406分開。
在實施例中，如圖4A中所示，眾多鰭404由塊體基底402形成。在一此實例中，塊體基底402及因而眾多鰭404由能耐受製程及電荷能於其中遷移的半導體材料構成。在實施例中，塊體基底402由摻雜有例如但不限於磷、砷、硼或其結合等電荷載子的鍺層、矽/鍺、或結晶矽。在一實施例中，在塊體基底402中的矽原子的濃度大於97%。在另一實施例中，塊體基底402由生長於不同的結晶基底上的磊晶層構成，例如，生長於硼摻雜塊矽單晶基底上的矽磊晶層。塊體基底402替代地由III-V族材料構成。在實施例中，塊體基底402由例如但不限於氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、銦鎵砷化物、鋁鎵砷化物、銦鎵砷化物、或其結合等III-V材料構成。在一實施例中，塊體基底402由III-V材料構成，以及，電荷載子摻雜劑雜質原子是例如但不限於碳、矽、鍺、氧、硫、硒或碲。在實施例中，塊體基底402及因而眾多鰭404未經摻雜或是僅輕度摻雜。在實施例中，在此階段或是在稍後的階段，眾多鰭404中的各鰭的至少一部份受應變。
替代地，基底包含上磊晶層及下塊體部份，上磊晶層及下塊體部份中任一者由單晶材料構成，包含但不限於矽、鍺、矽-鍺或III-V化合物半導體材料。由包含但不限 於二氧化矽、氮化矽或氧氮化矽材料構成之中介絕緣體層配置在上磊晶層與下塊體部份之間。
隔離電介層406由適合永久閘極結構與下方塊體基底最終電隔離或有助於隔離之材料構成。舉例而言，在一實施例中，隔離電介層406由例如但不限於二氧化矽、氧氮化矽、氮化矽、或碳摻雜的氮化矽等電介材料構成。須瞭解，形成全區層，然後使其凹陷以最終地曝露眾多鰭404的主動部份。
參考圖4B，例如多晶矽閘極結構等眾多假閘極結構408形成為與眾多鰭404正交及在隔離電介層406之上或上方。間隔器410形成為與眾多假閘極結構408中的各結構的側壁相鄰。圖4B的插圖提供進入及離開頁面的閘極結構之視圖。在此階段，在摻雜操作期間，使用眾多假閘極結構408和間隔器410作為掩罩，於眾多鰭404中形成摻雜的尖端及/或源極和汲極區。
在實施例中，如下所述，假閘極結構408由適用於更換閘極操作時移除的材料構成。在一實施例中，假閘極結構408由多晶矽、非晶矽、二氧化矽、氮化矽、或其組合構成。在另一實施例中，例如二氧化矽或氮化矽層等保護蓋層(未顯示)形成於假閘極結構408上方。在實施例中，包含下方假閘極電介層(也未顯示)。在實施例中，假閘極結構408。
間隔器410由適合最終電隔離、或有助於隔離永久閘極結構與相鄰的導電接點之材料構成。舉例而言，在一實 施例中，間隔器410由例如但不限於二氧化矽、氧氮化矽、氮化矽、或碳摻雜氮化矽等電介材料構成。
如上所述，在鰭中形成摻雜劑或擴散區。在一實施例中，此摻雜劑或擴散區是眾多鰭404的重度摻雜區。在一實施例中，眾多鰭由IV族材料構成以及一或更多部份摻雜硼、砷、磷、銦、或其組合。在另一實施例中，眾多鰭404由III-V族材料構成以及一或更多部份摻雜碳、矽、鍺、氧、硫、硒或碲。
參考圖4，接點412(例如金屬接點)及/或隔離區414(例如，氧化物、氮化物或碳化物電介材料)形成在眾多假閘極結構408的閘極與間隔器410之間。接點412與隔離區414的定位是視佈局而定的。圖4C的插圖提供根據實施例之接點412及隔離區414的此配置之更廣視圖。須瞭解，在此階段的接點412可以替代的是稍後由金屬接點材料取代之假接點(例如，假電介材料)。
在實施例中，以沈積及例如CMP等平坦化，由導電材料形成接點412。接點412由導電材料構成。在實施例中，接點412由金屬物構成。金屬物可以是純金屬，例如鎳或鈷，或是合金，例如金屬-金屬合金或是金屬-半導體合金(舉例而言，例如矽化物材料)。
隔離區414由適合最終電隔離、或有助於隔離永久閘極結構與其它閘極結構或接點結構之材料構成。舉例而言，在一實施例中，隔離電介質區414由例如但不限於二氧化矽、氧氮化矽、氮化矽、或碳摻雜氮化矽等電介材料 構成。
參考圖4D，移除眾多假閘極408，留下接點412、隔離區414及間隔器410，以及曝露眾多鰭404和隔離電介層406。圖4D的插圖對應於圖4C的插圖。也顯示與假閘極408的先前定位正交之接點區412A。
因此，曝露的眾多假閘極408最終在更換閘極製程設計中被取代。在此設計中，例如多晶矽或氮化矽丸材料等假閘極材料被移除及由永久閘極電極材料取代。在一此實施例中，與由較早的處理執行相反地，也在此製程中形成永久閘極電介層。
在實施例中，以乾蝕刻或濕蝕刻製程，移除眾多假閘極408。在一實施例中，眾多假閘極408由多晶矽或非晶矽構成且以包括SF6的乾蝕刻製程移除。在另一實施例中，眾多假閘極408由多晶矽或非晶矽構成且以包括含水NH4OH或氫氧化四鉀銨之濕蝕刻製程移除。在一實施例中，眾多假閘極408由氮化矽構成且以包括含水磷酸的濕蝕刻移除。
參考圖4E，內部間隔器電介質襯裡416(例如，內部間隔器氧化物襯裡)形成為與圖4D的結構保形的。圖4E的插圖對應於圖4D的插圖。
在實施例中，內部間隔器電介質襯裡416是由原子層沈積(ALD)或其它保形氧化物襯裡沈積形成的高品質、電閘極氧化物。在一此實施例中，內部間隔器電介襯裡是氧化矽(例如，SiO2)材料層。如圖4E所示，藉由使用 內部間隔器電介質襯裡416，增加有效間隔器厚度。也如同所示，由於使用原子層(或其它保形)沈積以沈積內部間隔器電介質襯裡416，所以，內部間隔器電介質襯裡416不僅遮蓋曝露的鰭404，也遮蓋間隔器410的側壁。在一實施例中，間隔器410材料很薄且具有不良的電品質(比電氧化物的等效厚度具有更低的崩潰電壓)，以及，內部間隔器電介質襯裡416的存在會提供大幅增進的電障壁。以ALD沈積高品質氧化物以將間隔器側壁襯裡，可以使間隔器材料的崩潰電壓增加至超越閘極對本體崩潰電壓。在一此實施例中，此配置適用於本質上可靠的電晶體。顯著地，相較於將利用鰭消耗以製造厚氧化物層的熱SiO2製程，內部間隔器電介質襯裡416的沈積消耗一些或不消耗鰭矽。
在內部間隔器電介質襯裡416形成之後，雖然未顯示，但是，可執行雙閘極氧化物形成。具體而言，薄閘極電介質電晶體(例如，低電壓電晶體)的製造涉及下述：在所有裝置區形成內部間隔器電介質襯裡416之後，將厚閘極電介質電晶體(例如，高電壓電晶體)的區域遮罩，但曝露低電壓電晶體的區域。執行蝕刻製程以移除將製造低電壓裝置的區域中之內部間隔器電介質襯裡416內部的部份。然後，藉由掩罩移除而再曝露高電壓裝置的區域，以及，在所有區域中形成例如高k閘極電介層等第二閘極電介層。因此，在實施例中，低電壓電晶體包含第二閘極電介層但不是內部間隔器電介質襯裡416，而高電壓電晶 體包含第二閘極電介層及內部間隔器電介質襯裡416。
在實施例中，第二閘極電介層由高K材料構成。舉例而言，在一實施例中，第二閘極電介層由例如但不限於氧化鉿、氧氮化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉛鈧鉭氧化物、鈮酸鉛鋅、或其組合所構成。此外，一部份的第二閘極電介層包含由內部間隔器電介質襯裡416已被移除的區域中(例如在低電壓裝置的區域中)的鰭404的上方少數層形成的熱氧化物(例如，1-2單層)薄層。在實施例中，第二閘極電介層由頂部高k部份及半導體材料的氧化物構成的下部構成。在一實施例中，第二閘極電介層由氧化鉿的頂部以及二氧化矽或氧氮化矽的底部構成。
參考圖4F，在移除眾多假閘極408時形成的開口中、以及在內部間隔器電介質襯裡416中或上方，形成眾多永久閘極電極418(例如，金屬閘極電極)。如圖4F所示，金屬永久閘極材料以及內部間隔器電介質襯裡416可以被平坦化以再曝露接點412、隔離區414及(可能是)間隔器410。圖4F的插圖對應於圖4E的插圖。
在實施例中，以化學機械平坦化(CMP)製程操作，將金屬永久閘極材料及內部間隔器電介質襯裡416平坦化。在一此實施例中，CMP製程操作係使用泥漿而在研磨墊上將金屬永久閘極材料及內部間隔器電介質襯裡416拋光。在另一實施例中，使用乾蝕刻製程。
在實施例中，眾多永久閘極電極418由金屬材料構 成。在一此實施例中，眾多永久閘極電極418由例如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳、或導電金屬氧化物等金屬層構成。在特定實施例中，眾多永久閘極電極418由形成於金屬功函數設定層上方的非功函數設定填充材料構成。在實施例中，眾多永久閘極電極418。
上述製程用以製造一或更多半導體裝置。半導體裝置可為電晶體或類似裝置。舉例而言，在實施例中，半導體裝置是用於邏輯或記憶體的金屬氧化物半導體(MOS)電晶體、或是雙極電晶體。而且，在實施例中，半導體裝置具有三維架構，例如，三閘極裝置，獨立存取雙閘極裝置、或是FIN-FET。
整體而言，隨著間距持續降低及因圖型化限制而變得離散，高電壓及/或類比電路比例化的困難變得愈來愈明顯。上述實施可用於在電路設計中實施多電壓供應，例如在22nm節點或更低之系統晶片產品中。
在特定實施中，在實施例中，用於1.8V電晶體的額定氧化物厚度約為3.5-4nm。對於高電壓技術，在閘極與S/D接點之間有實質餘裕(例如，35nm)，能夠在閘極與本體之間發生較佳的崩潰路徑。在後續的節點上，閘極至接點餘裕縮減至約4-7nm。隔離閘極與接點之4-7nm的電介質不是與隔離閘極與通道的3.5-4nm閘極電介質一般高品質的氧化物，存在有可靠度的風險。與上述相同之具有增加的氧化物襯裡的電晶體在閘極與接點之間提供餘 裕，此餘裕是因增加約2.5-3.5nm原子層沈積(ALD)閘極氧化物電介質而增進的，將接點至閘極間隔增進至大於約7-10nm。
與實施例相關連地，相較於習知的更換閘極整合設計，取得包含氧化物襯裡高電壓電晶體之裝置的匹配電晶體性能。與一實施例相關地，相較於標準流程，所示之可靠度結果顯示氧化物襯裡厚閘極流程的形狀因素之實質增進。與實施例相關連地，厚閘極NMOS可靠度資料顯示利用氧化物襯裡流程之形狀因素的增進。相較於標準流程，在較小的電壓範圍上發生崩潰事件，降低相對於時間及電壓之故障分佈。
大概更一般而言，本發明的一或更多實施例是關於閘極對準接點製程。可以實施此製程以形成例如用於積體電路製造等用於半導體結構製造的接點結構。在實施例中，接點圖案形成為對準現存的閘極圖案。相對地，習知的方式典型上涉及增加的微影製程，使微影接點圖案緊緊地定位至現存的閘極圖案並結合選擇性接點蝕刻。舉例而言，習知的製程包含多(閘極)柵圖型化，將接點與接點栓分別圖型化。
再度地，以更一般的觀點而言，根據此處所述的一或更多實施例，接點形成的方法涉及接點圖案的形成，其完美地對準現存的閘極圖並免除使用過度緊繃的定位預算之微影步驟。在一此實施例中，此方式能夠使用本質上高度選擇性的濕蝕刻(例如，各式各樣習知實施的乾或電漿蝕 刻)以產生接點開口。在實施例中，藉由利用現存的閘極圖案並接合接點栓微影操作，以形成接點圖案。在一此實施例中，方式能夠不需要習知方式中產生接點圖案的其它關鍵微影操作。在實施例中，溝槽接點柵未被分別地圖型化，而是形成在多(閘極)線之間。舉例而言，在一此實施例中，在閘極光柵圖型化之後但在閘極光柵切割之前，形成溝槽接點柵。
圖5顯示根據本發明的一實施之計算裝置500。計算裝置500容納主機板502。主機板502包含多個組件，多個組件包括但不限於處理器504及至少一通訊晶片506。處理器504實體地及電地耦合至主機板502。在某些實施中，至少一通訊晶片506也實體地及電地耦合至主機板502。在另外的實施中，通訊晶片506是處理器504的一部份。
取決於其應用，計算裝置500包含可以或不可以實體地及電地耦合至主機板502的其它組件。這些其它組件包含但不限於依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位訊號處理器、密碼處理器、晶片組、天線、顯示器、觸控幕顯示器、觸控幕控制器、電池、音頻編解碼、視頻編解碼、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚音器、相機、及大量儲存裝置(例如硬碟機、光碟(CD)、數位多樣式光碟(DVD)、等等)。
通訊晶片506能夠無線通訊以用於與計算裝置500傳輸資料。「無線」一詞及其衍生詞用以說明經由使用通過非固體介質之調變的電磁輻射來傳輸資料的電路、裝置、系統、方法、技術、通訊通道、等等。此詞並非意指相關連裝置未含有任何接線，但是，在某些實施例中，它們可能未含任何接線。通訊晶片506可以實施任何無線標準或是通信協定，包含但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長程演化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生、以及以3G、4G、5G、及更新的世代來標示的任何其它無線通信協定。計算裝置500包含眾多通訊晶片506。舉例而言，第一通訊晶片506可以專用於較短範圍的無線通訊，例如Wi-Fi及藍芽，而第二通訊晶片506可以專用於較長範圍的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。
計算裝置500的處理器504包含封裝在處理器504之內的積體電路晶粒。在本發明的某些實施中，處理器的積體電路晶粒包含根據本發明的實施建立之例如MOS-FET電晶體等一或更多裝置。「處理器」一詞意指處理來自暫存器及/或記憶體的電子資料以將電子資料轉換成儲存在暫存器及/或記憶體中的其它電子資料之任何裝置或裝置的一部份。
通訊晶片506也包含封裝於通訊晶片506之內的積體 電路晶粒。根據本發明的另一實施，通訊晶片的積體電路晶粒包含根據本發明的實施建立之例如MOS-FET電晶體等一或更多裝置。
在其它實施中，容納於計算裝置500之內的另一組件含有積體電路晶粒，積體電路晶粒包含根據本發明的實施建立之例如MOS-FET電晶體等一或更多裝置。
在各式各樣的實施中，計算裝置500可以是膝上型電腦、筆記型電腦、超薄筆記型電腦、智慧型電話、平板電腦、個人數位助理(PDA)、超薄行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或是數位攝影機。在又其它實施中，計算裝置500可為處理資料的任何其它電子裝置。
因此，本發明的實施例包含具有電介質襯裡的高電壓三維裝置以及具有電介質襯裡的高電壓三維裝置的形成方法。
在實施例中，半導體結構包含配置在上述基底上方的第一鰭主動區以及第二鰭主動區。第一閘極結構配置在第一鰭主動區的上表面上方、以及延著第一鰭主動區的側壁。第一閘極結構包含第一閘極電介質、第一閘極電極、及第一間隔器。第一閘極電介質由配置在第一鰭主動區上及延著第一間隔器側壁之第一電介層、以及配置在第一電介層上及延著第一間隔器側壁之第二、不同的電介層構成。半導體結構也包含配置在第二鰭主動區的上表面上 方、以及延著第二鰭主動區的側壁之第二閘極結構。第二閘極結構包含第二閘極電介質、第二閘極電極、及第二間隔器。第二閘極電介質由配置在第二鰭主動區上及延著第二間隔器側壁之第二電介層構成。
在一實施例中，第一鰭主動區及第二鰭主動區直接配置在基底上。
在一實施例中，基底是塊體單晶矽基底，以及，第一鰭主動區和第二鰭主動區由單晶矽構成。
在一實施例中，第一電介層由氧化矽構成，以及，第二電介層由高k材料構成。
在一實施例中，第二鰭主動區而不是第一鰭主動區，包含在鰭主動區的上表面之熱氧化物薄層。
在一實施例中，半導體結構又包含配置成直接相鄰第一間隔器的第一對接點、以及配置成直接相鄰第二間隔器的第二對接點。
在一實施例中，第一和第二閘極電極是金屬閘極電極。
在一實施例中，半導體結構又包含包括第一閘極結構的高電壓裝置、以及包含第二閘極結構的低電壓裝置。
在實施例中，半導體結構包含配置在基底上方的第一眾多鰭主動區及第二眾多鰭主動區。半導體結構也包含具有第一閘極電介質及第一閘極電極之高電壓裝置。第一閘極電介質由配置在第一眾多鰭主動區上以及延著第一閘極電極的側壁之第一電介層、以及配置在第一電介層以及延 著第一閘極電極的側壁之第二、不同的電介層構成。半導體結構也包含具有第二閘極電介質及第二閘極電極之低電壓裝置。第二閘極電介質由配置在第二眾多鰭主動區上以及延著第二閘極電極的側壁之第二電介層構成。
在一實施例中，第一眾多鰭主動區及第二眾多鰭主動區直接配置在基底上。
在一實施例中，基底是塊體單晶矽基底，以及，第一眾多鰭主動區和第二眾多鰭主動區由單晶矽構成。
在一實施例中，第一電介層由氧化矽構成，以及，第二電介層由高k材料構成。
在一實施例中，第二眾多鰭主動區而不是第一鰭主動區，包含在眾多鰭主動區的上表面之熱氧化物薄層。
在一實施例中，半導體結構又包含配置成直接相鄰第一間隔器的第一對接點、以及配置成直接相鄰第二間隔器的第二對接點。
在一實施例中，第一和第二閘極電極是金屬閘極電極。
在實施例中，半導體結構的製造方法包含：在基底上方形成第一眾多鰭主動區以及第二眾多鰭主動區。在第一及第二眾多鰭主動區上方，形成眾多假閘極結構。形成間隔器為相鄰於眾多假閘極結構中的各假閘極結構的側壁。假閘極結構被移除以形成由間隔器界定的眾多閘極區。在眾多閘極區中，形成第一保形電介層。從第一眾多閘極區而不是從第二眾多閘極區，移除第一保形電介層。接續 地，在眾多閘極區中，形成第二保形電介層。接續地，在第一眾多閘極區中，形成低電壓裝置，以及，在第二眾多閘極區中形成高電壓裝置。
在一實施例中，第一眾多鰭主動區及第二眾多鰭主動區直接形成在基底上。
在一實施例中，基底是塊體單晶矽基底，以及，第一眾多鰭主動區和第二眾多鰭主動區由塊體單晶矽基底形成。
在一實施例中，第一電介層由氧化矽構成，以及，第二電介層由高k材料構成。
在一實施例中，方法又包含在眾多第二鰭主動區的上表面而不是在第一眾多鰭主動區上，形成熱氧化物薄層。
在一實施例中，方法又包含形成直接相鄰第一間隔器的第一對接點、以及形成直接相鄰第二間隔器的第二對接點。
在一實施例中，形成低及高電壓裝置包括形成金屬閘極電極。
在一實施例中，形成第二保形電介層包括使用原子層沈積(ALD)以形成二層。
100A‧‧‧標準高電壓電晶體
100B‧‧‧比例化高電壓電晶體
102A‧‧‧閘極電極
102B‧‧‧閘極電極
104A‧‧‧接點
104B‧‧‧接點
106A‧‧‧高電壓閘極電介質
106B‧‧‧高電壓閘極電介質
108A‧‧‧基底
108B‧‧‧基底

Claims (23)

  1. 一種半導體結構，包括：第一鰭主動區以及第二鰭主動區，配置在基底上方；第一閘極結構，配置在該第一鰭主動區的上表面上方、以及延著該第一鰭主動區的側壁，該第一閘極結構包括第一閘極電介質、第一閘極電極、及第一間隔器，其中，該第一閘極電介質包括配置在該第一鰭主動區上及延著該第一間隔器的側壁之第一電介層、以及配置在該第一電介層上及延著該第一間隔器的側壁之第二、不同的電介層；以及第二閘極結構，配置在該第二鰭主動區的上表面上方、以及延著該第二鰭主動區的側壁，該第二閘極結構包含第二閘極電介質、第二閘極電極、及第二間隔器，其中，該第二閘極電介質包括配置在該第二鰭主動區上及延著該第二間隔器側壁之第二電介層。
  2. 如申請專利範圍第1項之半導體結構，其中，該第一鰭主動區及該第二鰭主動區直接配置在該基底上。
  3. 如申請專利範圍第2項之半導體結構，其中，該基底是塊體單結晶矽基底，以及，該第一鰭主動區和該第二鰭主動區包括單晶矽。
  4. 如申請專利範圍第1項之半導體結構，其中，該第一電介層包括氧化矽，以及，該第二電介層包括高k材料。
  5. 如申請專利範圍第1項之半導體結構，其中，該 第二鰭主動區而不是該第一鰭主動區，包括在該鰭主動區的上表面之熱氧化物薄層。
  6. 如申請專利範圍第1項之半導體結構，又包括：第一對接點，配置成直接相鄰該第一間隔器；以及第二對接點，配置成直接相鄰該第二間隔器。
  7. 如申請專利範圍第1項之半導體結構，其中，該第一和第二閘極電極是金屬閘極電極。
  8. 如申請專利範圍第1項之半導體結構，又包括：高電壓裝置，包含第一閘極結構；以及低電壓裝置，包含第二閘極結構。
  9. 一種半導體結構，包括：第一眾多鰭主動區及第二眾多鰭主動區，配置在基底上方；高電壓裝置，包括第一閘極電介質及第一閘極電極，其中，該第一閘極電介質包括在該第一眾多鰭主動區上以及延著該第一閘極電極的側壁之第一電介層、以及配置在該第一電介層以及延著該第一閘極電極的側壁之第二、不同的電介層；以及低電壓裝置，包含第二閘極電介質及第二閘極電極，其中，該第二閘極電介質包括配置在該第二眾多鰭主動區上以及延著該第二閘極電極的側壁之該第二電介層。
  10. 如申請專利範圍第9項之半導體結構，其中，該第一眾多鰭主動區及該第二眾多鰭主動區直接配置在該基底上。
  11. 如申請專利範圍第10項之半導體結構，其中，該基底是塊體單晶矽基底，以及，該第一眾多鰭主動區和該第二眾多鰭主動區包括單晶矽。
  12. 如申請專利範圍第9項之半導體結構，其中，該第一電介層包括氧化矽，以及，該第二電介層包括高k材料。
  13. 如申請專利範圍第9項之半導體結構，其中，該第二眾多鰭主動區而不是該第一鰭主動區，包括在該眾多鰭主動區的上表面之熱氧化物薄層。
  14. 如申請專利範圍第9項之半導體結構，又包括：第一對接點，配置成直接相鄰該第一間隔器；以及第二對接點，配置成直接相鄰該第二間隔器。
  15. 如申請專利範圍第9項之半導體結構，其中，該第一和第二閘極電極是金屬閘極電極。
  16. 一種半導體結構的製造方法，該方法包括：在基底上方形成第一眾多鰭主動區以及第二眾多鰭主動區；在該第一及該第二眾多鰭主動區上方，形成眾多假閘極結構；在相鄰於該眾多假閘極結構中的各假閘極結構的側壁形成間隔器；移除該假閘極結構以形成由該間隔器界定的眾多閘極區；在該眾多閘極區中，形成第一保形電介層； 從第一該眾多閘極區而不是從第二該眾多閘極區，移除該第一保形電介層；以及，接續地，在該眾多閘極區中，形成第二保形電介層；以及，接續地，在該第一該眾多閘極區中，形成低電壓裝置，以及，在該第二該眾多閘極區中形成高電壓裝置。
  17. 如申請專利範圍第16項之方法，其中，該第一眾多鰭主動區及該第二眾多鰭主動區直接形成在該基底上。
  18. 如申請專利範圍第17項之方法，其中，該基底是塊體單晶矽基底，以及，該第一眾多鰭主動區和該第二眾多鰭主動區由塊體單晶矽基底形成。
  19. 如申請專利範圍第16項之方法，其中，該第一電介層包括氧化矽，以及，該第二電介層包括高k材料。
  20. 如申請專利範圍第16項之方法，又包含：在該眾多第二鰭主動區的上表面而不是在該第一眾多鰭主動區上，形成熱氧化物薄層。
  21. 如申請專利範圍第16項之方法，又包括：形成直接相鄰該第一間隔器的第一對接點；以及形成直接相鄰該第二間隔器的第二對接點。
  22. 如申請專利範圍第16項之方法，其中，形成低及高電壓裝置包括形成金屬閘極電極。
  23. 如申請專利範圍第16項之方法，其中，形成第二保形電介層包括使用原子層沈積(ALD)以形成二層。
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