US9704969B1 - Fin semiconductor device having multiple gate width structures - Google Patents

Fin semiconductor device having multiple gate width structures Download PDF

Info

Publication number
US9704969B1
US9704969B1 US14/985,406 US201514985406A US9704969B1 US 9704969 B1 US9704969 B1 US 9704969B1 US 201514985406 A US201514985406 A US 201514985406A US 9704969 B1 US9704969 B1 US 9704969B1
Authority
US
United States
Prior art keywords
semiconductor fin
sidewall
gate
dummy gate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/985,406
Other versions
US20170194458A1 (en
Inventor
Che-Cheng Chang
Chih-Han Lin
Horng-Huei Tseng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US14/985,406 priority Critical patent/US9704969B1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSENG, HORNG-HUEI, CHANG, CHE-CHENG, LIN, CHIH-HAN
Priority to TW105137193A priority patent/TWI710030B/en
Priority to CN201611021154.4A priority patent/CN107026125B/en
Publication of US20170194458A1 publication Critical patent/US20170194458A1/en
Application granted granted Critical
Publication of US9704969B1 publication Critical patent/US9704969B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

Definitions

  • FinFETs fin-type field effect transistors
  • CMOS Complementary Metal Oxide Semiconductor
  • dummy gate strips are replaced by sequentially formed metal gates.
  • wet cleaning processes are performed and peeling issue of dummy gate strips resulted from the aforesaid wet cleaning processes may induce low yield rate.
  • FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with some embodiments.
  • FIGS. 2A-2K are perspective views of a method for fabricating a semiconductor device in accordance with some embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • the embodiments of the present disclosure describe the exemplary fabricating process of a semiconductor device which comprises a plurality of FinFETs with different gate profiles.
  • the semiconductor device may be formed on bulk silicon substrates in certain embodiments of the present disclosure. Still, the semiconductor device may be formed on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers or other semiconductor elements, such as transistors, diodes or the like. The embodiments are not limited in this context.
  • step S 10 a substrate is provided and the substrate is then patterned to form a plurality of trenches and a semiconductor fin between the trenches.
  • step S 12 a plurality of insulators are formed in the trenches.
  • the insulators are shallow trench isolation (STI) structures for insulating semiconductor fin, for example.
  • step S 14 a dielectric layer is formed to cover the semiconductor fin and the insulators.
  • STI shallow trench isolation
  • a first dummy gate strip and a second dummy gate strip are formed on the dielectric layer, wherein a lengthwise direction of the first and second dummy gate strips is different from a lengthwise direction of the semiconductor fin, the first dummy gate strip is penetrated by the semiconductor fin, the second dummy gate strip is not penetrated through by the semiconductor fin, and a bottom width of the second dummy gate strip is greater than a top width of the second dummy gate strip.
  • the first dummy gate strip and the second dummy gate strip are conductive strips, such as poly-silicon strips.
  • a pair of first spacers and a pair of second spacers are formed on sidewalls of the first and second dummy gate strips respectively.
  • the first and second dummy gate strips are removed.
  • a first gate and a second gate are formed between the pair of first spacers and the pair of second spacers respectively.
  • the first dummy gate strip and the second dummy gate strip may be formed by same deposition and chemical mechanical polish (CMP) processes and removal of the first dummy gate strip and the second dummy gate strip may be performed by the same etch process.
  • the first gate and the second gate may be formed by same deposition and chemical mechanical polish (CMP) processes.
  • FIG. 2A is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • a substrate 200 is provided.
  • the substrate 200 comprises a crystalline silicon substrate (e.g., wafer).
  • the substrate 200 may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate).
  • the doped regions may be doped with p-type and/or n-type dopants.
  • the doped regions may be doped with p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof.
  • the doped regions may be configured for an n-type FinFET, a p-type FinFET or the combination thereof.
  • the substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.
  • a pad layer 202 a and a mask layer 202 b are sequentially formed on the substrate 200 .
  • the pad layer 202 a may be a silicon oxide thin film formed, for example, by thermal oxidation process.
  • the pad layer 202 a may act as an adhesion layer between the substrate 200 and mask layer 202 b .
  • the pad layer 202 a may also act as an etch stop layer for etching the mask layer 202 b .
  • the mask layer 202 b is a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
  • LPCVD low-pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • FIG. 2B is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • the mask layer 202 b and the pad layer 202 a which are not covered by the patterned photoresist layer 204 are sequentially etched to form a patterned mask layer 202 b ′ and a patterned pad layer 202 a ′ so as to expose underlying substrate 200 .
  • the patterned mask layer 202 b ′, the patterned pad layer 202 a ′ and the patterned photoresist layer 204 as a mask, portions of the substrate 200 are exposed and etched to form trenches 206 and a semiconductor fin 208 .
  • the semiconductor fin 208 is covered by the patterned mask layer 202 b ′, the patterned pad layer 202 a ′ and the patterned photoresist layer 204 .
  • the number of the semiconductor fin 208 is not limited, two or more semiconductor fins 208 may be formed on the substrate 200 a .
  • the height of the semiconductor fin 208 and the depth of the trenches 206 range from about 5 nm to about 500 nm, for example.
  • the width W of the semiconductor fin 208 may be smaller than about 30 nm, for example.
  • the patterned photoresist layer 204 is then removed.
  • a cleaning process may be performed to remove a native oxide of the substrate 200 a and the semiconductor fin 208 .
  • the cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions.
  • FIG. 2C is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • an insulating material 210 are formed over the substrate 200 a to cover the semiconductor fin 208 and fill up the trenches 206 .
  • the insulating material 210 further covers the patterned pad layer 202 a ′ and the patterned mask layer 202 b ′.
  • the insulating material 210 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material.
  • the insulating material 210 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on.
  • HDP-CVD high-density-plasma chemical vapor deposition
  • SACVD sub-atmospheric CVD
  • FIG. 2D is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • a chemical mechanical polish (CMP) process is, for example, performed to remove a portion of the insulating material 210 , the patterned mask layer 202 b ′ and the patterned pad layer 202 a ′ until the semiconductor fin 208 are exposed.
  • CMP chemical mechanical polish
  • top surfaces of the polished insulating material 210 is substantially coplanar with top surface T 2 of the semiconductor fin 208 .
  • FIG. 2E is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • the polished insulating material 210 filled in the trenches 206 is partially removed by an etch process such that insulators 210 a are formed on the substrate 200 a .
  • the etch process may be a wet etch process with hydrofluoric acid (HF) or a dry etch process.
  • the top surfaces T 1 of the insulators 210 a are lower than the top surface T 2 of the semiconductor fin 208 .
  • the semiconductor fin 208 protrudes from the top surfaces T 1 of the insulators 210 a and sidewalls SW of the semiconductor fin 208 are thus exposed.
  • the height difference between the top surface T 2 of the semiconductor fin 208 and the top surfaces T 1 of the insulators 210 a is H, and the above-mentioned height difference H ranges from about 15 nm to about 50 nm.
  • FIG. 2F is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • a dielectric layer 212 is formed to conformally cover the top surface T 1 of the insulators 210 a , the top surface T 2 of the semiconductor fin 208 and the sidewalls SW of the semiconductor fin 208 .
  • the dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. High-k dielectrics comprise metal oxides.
  • metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof.
  • the dielectric layer 212 may be formed by a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation or UV-ozone oxidation.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the dielectric layer 212 may have suitable thickness and good quality so as to serve as a gate dielectric layer in FinFETs.
  • the dielectric layer 212 may be a high-k dielectric layer having a thickness in the range of about 0.2 nm to 5 nm. In some alternative embodiments, for long channel FinFETs (e.g., channel length is greater than 50 nm), the dielectric layer 212 may be a high-k dielectric layer having a thickness greater than 5 nm.
  • FIG. 2G is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • Step S 16 in FIG. 1 and as shown in FIGS. 2F-2G one first dummy gate strip 214 a and two second dummy gate strip 214 b , 214 c are formed on the dielectric layer 212 , wherein a lengthwise direction D 1 of the first, second and third dummy gate strips 214 a , 214 b , 214 c is different from a lengthwise direction D 2 of the semiconductor fin 208 .
  • the lengthwise direction D 1 of the first, second and third dummy gate strips 214 a , 214 b , 214 c are perpendicular to the lengthwise direction D 2 of the semiconductor fin 208 , for example.
  • the number of the dummy gate strips ( 214 a , 214 b , 214 c ) shown in FIG. 2G is merely for illustration. As shown in FIG. 2G , the first dummy gate strip 214 a is penetrated by the semiconductor fin 208 , the second dummy gate strips 214 b , 214 c are not penetrated by the semiconductor fin 208 .
  • the semiconductor fin 208 penetrates the first dummy gate strip 214 a from one side to the other side of the first dummy gate strip 214 a ; one end of the semiconductor fin 208 is embedded in the second dummy gate strip 214 b and does not penetrate the second dummy gate strip 214 b ; and the semiconductor fin 208 is not in contact with the second dummy gate strip 214 c .
  • more than two first dummy gate strips 214 a may be formed on the dielectric layer 212 in accordance with actual design requirements; and one or more than three second dummy gate strips 214 b , 214 c may be formed on the dielectric layer 212 in accordance with actual design requirements.
  • the formation of the second dummy gate strip 214 b or the formation of the second dummy gate strip 214 c may be emitted in accordance with actual requirements. In other words, it is not necessary to simultaneously form the second dummy gate strip 214 b and the second dummy gate strip 214 c on the dielectric layer 212 . In some embodiments, merely the first dummy gate strip 214 a and the second dummy gate strip 214 b are formed on the dielectric layer 212 . In some alternative embodiments, merely the first dummy gate strip 214 a and the second dummy gate strip 214 c are formed on the dielectric layer 212 .
  • the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c may be formed by forming a conductive layer on the dielectric layer 212 and patterning the conductive layer so as to form the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c .
  • the patterning process of the conductive layer includes an etch process.
  • the conductive layer may be patterned by N 2 , He, Ar, O 2 , SF 6 , NF 3 , CxFy (x and y>0), CF 4 , HBr, Cl 2 , CHF 3 , CH 2 F 2 , SO 2 , CH 3 F or other suitable etch gas.
  • the temperature of the above-mentioned etch process ranges from about 10 degree Celsius to about 120 degree Celsius
  • the pressure of the above-mentioned etch process ranges from about 1 mTorr to about 100 mTorr
  • the power of the above-mentioned etch process ranges from about 10 W to about 1500 W
  • the bias of the above-mentioned etch process ranges from about 10 W to about 1000 W.
  • the first and second dummy gate strips 214 a , 214 b , 214 c include a silicon-containing material, such as poly-silicon, amorphous silicon or a combination thereof.
  • the width of the first dummy gate strip 214 a and the second dummy gate strip 214 b , 214 c may range from 5 nm to 50 nm (i.e., for short channel FinFETs) or may be greater than 50 nm (i.e., for long channel FinFETs).
  • the first dummy gate strip 214 a is penetrated by the semiconductor fin 208 and the width CD of the first dummy gate strip 214 a keeps constant in the thickness direction D 3 .
  • One end of the semiconductor fin 208 is embedded in the second dummy gate strip 214 b and the second dummy gate strip 214 b includes a broadened portion 214 b 1 disposed on the dielectric layer 212 and a top portion 214 b 2 disposed on the broadened portion 214 b 1 , wherein a bottom width BCD 1 of the broadened portion 214 b 1 is greater than a width TCD 1 of the top portion 214 b 2 .
  • the width TCD 1 of the top portion 214 b 2 keeps constant in the thickness direction D 3 , and a top width (TCD 1 ) of the broadened portion 214 b 1 is substantially equal to width TCD 1 of the top portion 214 b 2 .
  • the height of the broadened portion 214 b 1 of the second dummy gate strip 214 b substantially equals to the height of the semiconductor fin 208 .
  • the broadened portion 214 b 1 has a first sidewall SW 1 and a second sidewall SW 2 opposite to the first sidewall SW 1 , the broadened portion 214 b 1 has a recess R located at the first sidewall SW 1 for accommodating the end of the semiconductor fin 208 , and the second sidewall SW 2 of the broadened portion 214 b 1 is a tapered sidewall.
  • the broadened portion 214 b 1 of the second dummy gate strip 214 b is an asymmetric geometry.
  • the semiconductor fin 208 is not in contact with the second dummy gate strip 214 c and the second dummy gate strip 214 c includes a broadened portion 214 c 1 disposed on the dielectric layer 212 and a top portion 214 c 2 disposed on the broadened portion 214 c 1 , wherein a bottom width BCD 2 of the broadened portion 214 c 1 is greater than a width TCD 2 of the top portion 214 c 2 .
  • the width TCD 2 of the top portion 214 c 2 keeps constant in the thickness direction D 3
  • a top width (TCD 2 ) of the broadened portion 214 c 1 is substantially equal to width TCD 2 of the top portion 214 c 2 .
  • the height of the broadened portion 214 c 1 of the second dummy gate strip 214 c substantially equals to the height of the semiconductor fin 208 .
  • the broadened portion 214 c 1 has a first sidewall SW 3 and a second sidewall SW 4 opposite to the first sidewall SW 3 , and the first sidewall SW 3 and the second sidewall SW 4 of the broadened portion 214 c 1 are tapered sidewalls.
  • the broadened portion 214 c 1 of the second dummy gate strip 214 c is a symmetric geometry.
  • Formation of the second dummy gate strips 214 b and/or 214 c facilitates reduction of loading effect and enlarges process window during fabrication of the first dummy gate strip 214 a.
  • Step S 18 in FIG. 1 and as shown in FIG. 2H after the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c are formed, a pair of first spacers 216 a and pairs of second spacers 216 b , 216 c are formed on sidewalls of the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c respectively. As shown in FIG.
  • the first spacers 216 a are formed on the dielectric layer 212 and extend along the sidewalls of the first dummy gate strip 214 a
  • the second spacers 216 b are formed on the dielectric layer 212 and extend along the sidewalls of the second dummy gate strip 214 b
  • the second spacers 216 c are formed on the dielectric layer 212 and extend along the sidewalls of the second dummy gate strip 214 c .
  • the first spacers 216 a and the second spacers 216 b , 216 c are formed of dielectric materials, such as silicon nitride or SiCON.
  • the first and second spacers 216 a , 216 b may include a single layer or multilayer structure.
  • FIG. 2I is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • interlayer dielectric layers 218 are formed to cover the dielectric layer 212 that are not covered by the dummy gate strips 214 a , 214 b , 214 c and the spacers 216 a , 216 b , 216 c .
  • Top surfaces of the interlayer dielectric layers 218 are substantially coplanar with top surfaces of the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c .
  • some processes e.g., patterning process of dielectric layer 212 , fin recessing process, strained source/drain epitaxial process on the semiconductor fin, silicidation process and so on
  • processes e.g., patterning process of dielectric layer 212 , fin recessing process, strained source/drain epitaxial process on the semiconductor fin, silicidation process and so on
  • Details of the aforesaid processes are omitted.
  • wet cleaning processes are performed before the gate replacement process is performed. Geometries of the dummy gate strips 214 a , 214 b , 214 c reduce peeling possibility of the dummy gate strips 214 a , 214 b , 214 c.
  • FIG. 2J is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • Step S 20 in FIG. 1 and as shown in FIGS. 2I-2J the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c are removed.
  • the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c are removed, for example, by an etch process.
  • the first dummy gate strip 214 a and the second dummy gate strips 214 b , 214 c are removed without damaging the interlayer dielectric layers 218 , the dielectric layer 212 , the first spacers 216 a and the second spacer 216 b , 216 c significantly.
  • a first cavity C 1 between the pair of first spacers 216 a , a second cavity C 2 between the pair of second spacers 216 b and a third cavity C 3 between the pair of second spacers 216 c are formed.
  • the dielectric layer 212 is partially exposed by the first cavity C 1 , the second cavity C 2 and the third cavity C 3 .
  • FIG. 2K is a perspective view of the semiconductor device at one of various stages of the manufacturing method.
  • Step S 22 in FIG. 1 and as shown in FIGS. 2J-2K after the first cavity C 1 , the second cavity C 2 and the third cavity C 3 are formed, a first gate 220 a is formed in the first cavity C 1 and a plurality of second gates 220 b , 220 c are formed in the second cavity C 2 and the third cavity C 3 respectively.
  • the first gate 220 a and the second gates 220 b may be formed by same deposition and chemical mechanical polish (CMP) processes.
  • CMP chemical mechanical polish
  • the first gate 220 a is penetrated by the semiconductor fin 208 and the width CD of the first gate 220 a keeps constant in the thickness direction D 3 .
  • One end of the semiconductor fin 208 is embedded in the second gate 220 b and the second gate 220 b includes a broadened portion 220 b 1 disposed on the dielectric layer 212 and a top portion 220 b 2 disposed on the broadened portion 220 b 1 , wherein a bottom width BCD 1 of the broadened portion 220 b 1 is greater than a width TCD 1 of the top portion 220 b 2 .
  • the width TCD 1 of the top portion 220 b 2 keeps constant in the thickness direction D 3 , and a top width (TCD 1 ) of the broadened portion 220 b 1 is substantially equal to width TCD 1 of the top portion 220 b 2 .
  • the height of the broadened portion 220 b 1 of the second gate 220 b substantially equals to the height of the semiconductor fin 208 .
  • the broadened portion 220 b 1 has a first sidewall SW 5 and a second sidewall SW 6 opposite to the first sidewall SW 5 , the broadened portion 220 b 1 has a recess R located at the first sidewall SW 5 for accommodating the end of the semiconductor fin 208 , and the second sidewall SW 6 of the broadened portion 220 b 1 is a tapered sidewall.
  • the broadened portion 220 b 1 of the second gate 220 b is an asymmetric geometry.
  • the semiconductor fin 208 is not in contact with the second gate 220 c and the second gate 220 c includes a broadened portion 220 c 1 disposed on the dielectric layer 212 and a top portion 220 c 2 disposed on the broadened portion 220 c 1 , wherein a bottom width BCD 2 of the broadened portion 220 c 1 is greater than a width TCD 2 of the top portion 220 c 2 .
  • the width TCD 2 of the top portion 220 c 2 keeps constant in the thickness direction D 3
  • a top width (TCD 2 ) of the broadened portion 220 c 1 is substantially equal to width TCD 2 of the top portion 220 c 2 .
  • the height of the broadened portion 220 c 1 of the second gate 220 c substantially equals to the height of the semiconductor fin 208 .
  • the broadened portion 220 c 1 has a first sidewall SW 7 and a second sidewall SW 8 opposite to the first sidewall SW 7 , and the first sidewall SW 7 and the second sidewall SW 8 of the broadened portion 220 c 1 are tapered sidewalls.
  • the broadened portion 220 c 1 of the second gate 220 c is a symmetric geometry.
  • the first gate 220 a serves as gate electrode of a FinFET while the second gates 220 b and 220 c function as dummy gates.
  • channel region of the semiconductor fin 208 is covered by the first gate 220 a and portions of the semiconductor fin 208 that are covered by the second gates 220 b and 220 c do not serve as channel regions of FinFETs.
  • the above-mentioned second dummy gate strips 214 b and 214 c includes broadened portions 214 b 1 and 214 c 1 , process window of gate replacement process is enlarged. Therefore, yield and reliability of the semiconductor device are enhanced.
  • a method for fabricating a semiconductor device includes at least the following steps.
  • a substrate is patterned to form a plurality of trenches in the substrate and a semiconductor fin between the trenches.
  • a plurality of insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators.
  • a first dummy gate strip and a second dummy gate strip are formed on the dielectric layer, wherein a lengthwise direction of the first and second dummy gate strips is different from a lengthwise direction of the semiconductor fin, wherein the first dummy gate strip is penetrated by the semiconductor fin, the second dummy gate strip is not penetrated through by the semiconductor fin, and a bottom width of the second dummy gate strip is greater than a top width of the second dummy gate strip.
  • a pair of first spacers and a pair of second spacer are formed on sidewalls of the first dummy gate strip and the second dummy gate strip respectively. The first and second dummy gate strips are removed.
  • a first gate and a second gate are formed between the pair of first spacers and the pair of second spacers respectively.
  • a semiconductor device including a substrate, a plurality of insulators, a dielectric layer, a first gate and a second gate.
  • the substrate includes a plurality of trenches and a semiconductor fin between trenches.
  • the insulators are disposed in the trenches.
  • the dielectric layer covers the semiconductor fin and the insulators.
  • the first gate is disposed on the dielectric layer and is penetrated by the semiconductor fin.
  • the second gate is disposed on the dielectric layer, wherein a lengthwise direction of the first and second gates is different from a lengthwise direction of the semiconductor fin, the second gate is not penetrated through by the semiconductor fin, and a bottom width of the second gate is greater than a top width of the second gate.
  • a semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates.
  • the substrate includes a plurality of trenches and a semiconductor fin between trenches.
  • the insulators are disposed in the trenches.
  • the dielectric layer covers the semiconductor fin and the insulators.
  • a lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin.
  • the gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin.
  • the second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

Description

BACKGROUND
As the semiconductor devices keeps scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistors (FinFETs), have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the conducting channel that is formed by the fin further provides a better electrical control over the channel.
For the gate replacement process of the FinFETs, dummy gate strips are replaced by sequentially formed metal gates. Before the gate replacement process is performed, wet cleaning processes are performed and peeling issue of dummy gate strips resulted from the aforesaid wet cleaning processes may induce low yield rate.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with some embodiments.
FIGS. 2A-2K are perspective views of a method for fabricating a semiconductor device in accordance with some embodiments.
 DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The embodiments of the present disclosure describe the exemplary fabricating process of a semiconductor device which comprises a plurality of FinFETs with different gate profiles. The semiconductor device may be formed on bulk silicon substrates in certain embodiments of the present disclosure. Still, the semiconductor device may be formed on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers or other semiconductor elements, such as transistors, diodes or the like. The embodiments are not limited in this context.
Referring to FIG. 1, illustrated is a flow chart illustrating a method for fabricating a semiconductor device in accordance with some embodiments of the present disclosure. The fabricating method at least includes steps S10, step S12, step S14, step S16, step S18, step S20 and step 22. First, in step S10, a substrate is provided and the substrate is then patterned to form a plurality of trenches and a semiconductor fin between the trenches. In step S12, a plurality of insulators are formed in the trenches. The insulators are shallow trench isolation (STI) structures for insulating semiconductor fin, for example. In step S14, a dielectric layer is formed to cover the semiconductor fin and the insulators. In step S16, a first dummy gate strip and a second dummy gate strip are formed on the dielectric layer, wherein a lengthwise direction of the first and second dummy gate strips is different from a lengthwise direction of the semiconductor fin, the first dummy gate strip is penetrated by the semiconductor fin, the second dummy gate strip is not penetrated through by the semiconductor fin, and a bottom width of the second dummy gate strip is greater than a top width of the second dummy gate strip. The first dummy gate strip and the second dummy gate strip are conductive strips, such as poly-silicon strips. In step S18, a pair of first spacers and a pair of second spacers are formed on sidewalls of the first and second dummy gate strips respectively. In step S20, the first and second dummy gate strips are removed. In step S22, a first gate and a second gate are formed between the pair of first spacers and the pair of second spacers respectively.
As illustrated in step S20 in FIG. 1, the first dummy gate strip and the second dummy gate strip may be formed by same deposition and chemical mechanical polish (CMP) processes and removal of the first dummy gate strip and the second dummy gate strip may be performed by the same etch process. Similarly, as illustrated in step S22 in FIG. 1, the first gate and the second gate may be formed by same deposition and chemical mechanical polish (CMP) processes.
FIG. 2A is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step 10 in FIG. 1 and as shown in FIG. 2A, a substrate 200 is provided. In one embodiment, the substrate 200 comprises a crystalline silicon substrate (e.g., wafer). The substrate 200 may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type and/or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, a p-type FinFET or the combination thereof. In some alternative embodiments, the substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.
In one embodiment, a pad layer 202 a and a mask layer 202 b are sequentially formed on the substrate 200. The pad layer 202 a may be a silicon oxide thin film formed, for example, by thermal oxidation process. The pad layer 202 a may act as an adhesion layer between the substrate 200 and mask layer 202 b. The pad layer 202 a may also act as an etch stop layer for etching the mask layer 202 b. In at least one embodiment, the mask layer 202 b is a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer 202 b is used as a hard mask during subsequent photolithography processes. Then, a patterned photoresist layer 204 having a predetermined pattern is formed on the mask layer 202 b.
FIG. 2B is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S10 in FIG. 1 and as shown in FIGS. 2A-2B, the mask layer 202 b and the pad layer 202 a which are not covered by the patterned photoresist layer 204 are sequentially etched to form a patterned mask layer 202 b′ and a patterned pad layer 202 a′ so as to expose underlying substrate 200. By using the patterned mask layer 202 b′, the patterned pad layer 202 a′ and the patterned photoresist layer 204 as a mask, portions of the substrate 200 are exposed and etched to form trenches 206 and a semiconductor fin 208. After the substrate 200 is patterned, the semiconductor fin 208 is covered by the patterned mask layer 202 b′, the patterned pad layer 202 a′ and the patterned photoresist layer 204. In some embodiments, the number of the semiconductor fin 208 is not limited, two or more semiconductor fins 208 may be formed on the substrate 200 a. The height of the semiconductor fin 208 and the depth of the trenches 206 range from about 5 nm to about 500 nm, for example. The width W of the semiconductor fin 208 may be smaller than about 30 nm, for example.
After the trenches 206 and the semiconductor fin 208 are formed, the patterned photoresist layer 204 is then removed. In one embodiment, a cleaning process may be performed to remove a native oxide of the substrate 200 a and the semiconductor fin 208. The cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions.
FIG. 2C is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2B-2C, an insulating material 210 are formed over the substrate 200 a to cover the semiconductor fin 208 and fill up the trenches 206. In addition to the semiconductor fin 208, the insulating material 210 further covers the patterned pad layer 202 a′ and the patterned mask layer 202 b′. The insulating material 210 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material. The insulating material 210 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on.
FIG. 2D is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2C-2D, a chemical mechanical polish (CMP) process is, for example, performed to remove a portion of the insulating material 210, the patterned mask layer 202 b′ and the patterned pad layer 202 a′ until the semiconductor fin 208 are exposed. As shown in FIG. 2D, after the insulating material 210 is polished, top surfaces of the polished insulating material 210 is substantially coplanar with top surface T2 of the semiconductor fin 208.
FIG. 2E is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2D-2E, the polished insulating material 210 filled in the trenches 206 is partially removed by an etch process such that insulators 210 a are formed on the substrate 200 a. In one embodiment, the etch process may be a wet etch process with hydrofluoric acid (HF) or a dry etch process. The top surfaces T1 of the insulators 210 a are lower than the top surface T2 of the semiconductor fin 208. In other words, the semiconductor fin 208 protrudes from the top surfaces T1 of the insulators 210 a and sidewalls SW of the semiconductor fin 208 are thus exposed. The height difference between the top surface T2 of the semiconductor fin 208 and the top surfaces T1 of the insulators 210 a is H, and the above-mentioned height difference H ranges from about 15 nm to about 50 nm.
FIG. 2F is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S14 in FIG. 1 and as shown in FIGS. 2E-2F, after the insulators 210 a are formed, a dielectric layer 212 is formed to conformally cover the top surface T1 of the insulators 210 a, the top surface T2 of the semiconductor fin 208 and the sidewalls SW of the semiconductor fin 208. In one embodiment, the dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. The dielectric layer 212 may be formed by a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation or UV-ozone oxidation. The dielectric layer 212 may have suitable thickness and good quality so as to serve as a gate dielectric layer in FinFETs. In some embodiments, for short channel FinFETs (e.g., channel length ranges from 5 nm to 50 nm), the dielectric layer 212 may be a high-k dielectric layer having a thickness in the range of about 0.2 nm to 5 nm. In some alternative embodiments, for long channel FinFETs (e.g., channel length is greater than 50 nm), the dielectric layer 212 may be a high-k dielectric layer having a thickness greater than 5 nm.
FIG. 2G is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S16 in FIG. 1 and as shown in FIGS. 2F-2G, one first dummy gate strip 214 a and two second dummy gate strip 214 b, 214 c are formed on the dielectric layer 212, wherein a lengthwise direction D1 of the first, second and third dummy gate strips 214 a, 214 b, 214 c is different from a lengthwise direction D2 of the semiconductor fin 208. The lengthwise direction D1 of the first, second and third dummy gate strips 214 a, 214 b, 214 c are perpendicular to the lengthwise direction D2 of the semiconductor fin 208, for example. The number of the dummy gate strips (214 a, 214 b, 214 c) shown in FIG. 2G is merely for illustration. As shown in FIG. 2G, the first dummy gate strip 214 a is penetrated by the semiconductor fin 208, the second dummy gate strips 214 b, 214 c are not penetrated by the semiconductor fin 208. Specifically, the semiconductor fin 208 penetrates the first dummy gate strip 214 a from one side to the other side of the first dummy gate strip 214 a; one end of the semiconductor fin 208 is embedded in the second dummy gate strip 214 b and does not penetrate the second dummy gate strip 214 b; and the semiconductor fin 208 is not in contact with the second dummy gate strip 214 c. In some alternative embodiments, more than two first dummy gate strips 214 a may be formed on the dielectric layer 212 in accordance with actual design requirements; and one or more than three second dummy gate strips 214 b, 214 c may be formed on the dielectric layer 212 in accordance with actual design requirements.
It should be noted that the formation of the second dummy gate strip 214 b or the formation of the second dummy gate strip 214 c may be emitted in accordance with actual requirements. In other words, it is not necessary to simultaneously form the second dummy gate strip 214 b and the second dummy gate strip 214 c on the dielectric layer 212. In some embodiments, merely the first dummy gate strip 214 a and the second dummy gate strip 214 b are formed on the dielectric layer 212. In some alternative embodiments, merely the first dummy gate strip 214 a and the second dummy gate strip 214 c are formed on the dielectric layer 212.
The first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c may be formed by forming a conductive layer on the dielectric layer 212 and patterning the conductive layer so as to form the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c. In some embodiments, the patterning process of the conductive layer includes an etch process. The conductive layer may be patterned by N2, He, Ar, O2, SF6, NF3, CxFy (x and y>0), CF4, HBr, Cl2, CHF3, CH2F2, SO2, CH3F or other suitable etch gas. The temperature of the above-mentioned etch process ranges from about 10 degree Celsius to about 120 degree Celsius, the pressure of the above-mentioned etch process ranges from about 1 mTorr to about 100 mTorr, the power of the above-mentioned etch process ranges from about 10 W to about 1500 W, and the bias of the above-mentioned etch process ranges from about 10 W to about 1000 W. The first and second dummy gate strips 214 a, 214 b, 214 c include a silicon-containing material, such as poly-silicon, amorphous silicon or a combination thereof. In some embodiments, the width of the first dummy gate strip 214 a and the second dummy gate strip 214 b, 214 c may range from 5 nm to 50 nm (i.e., for short channel FinFETs) or may be greater than 50 nm (i.e., for long channel FinFETs).
As shown in FIG. 2G, the first dummy gate strip 214 a is penetrated by the semiconductor fin 208 and the width CD of the first dummy gate strip 214 a keeps constant in the thickness direction D3. One end of the semiconductor fin 208 is embedded in the second dummy gate strip 214 b and the second dummy gate strip 214 b includes a broadened portion 214 b 1 disposed on the dielectric layer 212 and a top portion 214 b 2 disposed on the broadened portion 214 b 1, wherein a bottom width BCD1 of the broadened portion 214 b 1 is greater than a width TCD1 of the top portion 214 b 2. The width TCD1 of the top portion 214 b 2 keeps constant in the thickness direction D3, and a top width (TCD1) of the broadened portion 214 b 1 is substantially equal to width TCD1 of the top portion 214 b 2. The height of the broadened portion 214 b 1 of the second dummy gate strip 214 b substantially equals to the height of the semiconductor fin 208. The broadened portion 214 b 1 has a first sidewall SW1 and a second sidewall SW2 opposite to the first sidewall SW1, the broadened portion 214 b 1 has a recess R located at the first sidewall SW1 for accommodating the end of the semiconductor fin 208, and the second sidewall SW2 of the broadened portion 214 b 1 is a tapered sidewall. In other words, the broadened portion 214 b 1 of the second dummy gate strip 214 b is an asymmetric geometry.
The semiconductor fin 208 is not in contact with the second dummy gate strip 214 c and the second dummy gate strip 214 c includes a broadened portion 214 c 1 disposed on the dielectric layer 212 and a top portion 214 c 2 disposed on the broadened portion 214 c 1, wherein a bottom width BCD2 of the broadened portion 214 c 1 is greater than a width TCD2 of the top portion 214 c 2. The width TCD2 of the top portion 214 c 2 keeps constant in the thickness direction D3, and a top width (TCD2) of the broadened portion 214 c 1 is substantially equal to width TCD2 of the top portion 214 c 2. The height of the broadened portion 214 c 1 of the second dummy gate strip 214 c substantially equals to the height of the semiconductor fin 208. The broadened portion 214 c 1 has a first sidewall SW3 and a second sidewall SW4 opposite to the first sidewall SW3, and the first sidewall SW3 and the second sidewall SW4 of the broadened portion 214 c 1 are tapered sidewalls. In other words, the broadened portion 214 c 1 of the second dummy gate strip 214 c is a symmetric geometry.
Formation of the second dummy gate strips 214 b and/or 214 c facilitates reduction of loading effect and enlarges process window during fabrication of the first dummy gate strip 214 a.
In Step S18 in FIG. 1 and as shown in FIG. 2H, after the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c are formed, a pair of first spacers 216 a and pairs of second spacers 216 b, 216 c are formed on sidewalls of the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c respectively. As shown in FIG. 2H, the first spacers 216 a are formed on the dielectric layer 212 and extend along the sidewalls of the first dummy gate strip 214 a, the second spacers 216 b are formed on the dielectric layer 212 and extend along the sidewalls of the second dummy gate strip 214 b and the second spacers 216 c are formed on the dielectric layer 212 and extend along the sidewalls of the second dummy gate strip 214 c. The first spacers 216 a and the second spacers 216 b, 216 c are formed of dielectric materials, such as silicon nitride or SiCON. The first and second spacers 216 a, 216 b may include a single layer or multilayer structure.
FIG. 2I is a perspective view of the semiconductor device at one of various stages of the manufacturing method. As shown in FIG. 2I, interlayer dielectric layers 218 are formed to cover the dielectric layer 212 that are not covered by the dummy gate strips 214 a, 214 b, 214 c and the spacers 216 a, 216 b, 216 c. Top surfaces of the interlayer dielectric layers 218 are substantially coplanar with top surfaces of the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c. In some embodiments, before the interlayer dielectric layers 218 are formed, some processes (e.g., patterning process of dielectric layer 212, fin recessing process, strained source/drain epitaxial process on the semiconductor fin, silicidation process and so on) may be performed in advance. Details of the aforesaid processes are omitted.
In some embodiments, before the gate replacement process is performed, wet cleaning processes are performed. Geometries of the dummy gate strips 214 a, 214 b, 214 c reduce peeling possibility of the dummy gate strips 214 a, 214 b, 214 c.
FIG. 2J is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S20 in FIG. 1 and as shown in FIGS. 2I-2J, the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c are removed. In one embodiment, the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c are removed, for example, by an etch process. Through properly selecting of etchant, the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c are removed without damaging the interlayer dielectric layers 218, the dielectric layer 212, the first spacers 216 a and the second spacer 216 b, 216 c significantly. After the first dummy gate strip 214 a and the second dummy gate strips 214 b, 214 c are removed, a first cavity C1 between the pair of first spacers 216 a, a second cavity C2 between the pair of second spacers 216 b and a third cavity C3 between the pair of second spacers 216 c are formed. In other words, the dielectric layer 212 is partially exposed by the first cavity C1, the second cavity C2 and the third cavity C3.
FIG. 2K is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S22 in FIG. 1 and as shown in FIGS. 2J-2K, after the first cavity C1, the second cavity C2 and the third cavity C3 are formed, a first gate 220 a is formed in the first cavity C1 and a plurality of second gates 220 b, 220 c are formed in the second cavity C2 and the third cavity C3 respectively. For example, the first gate 220 a and the second gates 220 b may be formed by same deposition and chemical mechanical polish (CMP) processes.
As shown in FIG. 2K, the first gate 220 a is penetrated by the semiconductor fin 208 and the width CD of the first gate 220 a keeps constant in the thickness direction D3. One end of the semiconductor fin 208 is embedded in the second gate 220 b and the second gate 220 b includes a broadened portion 220 b 1 disposed on the dielectric layer 212 and a top portion 220 b 2 disposed on the broadened portion 220 b 1, wherein a bottom width BCD1 of the broadened portion 220 b 1 is greater than a width TCD1 of the top portion 220 b 2. The width TCD1 of the top portion 220 b 2 keeps constant in the thickness direction D3, and a top width (TCD1) of the broadened portion 220 b 1 is substantially equal to width TCD1 of the top portion 220 b 2. The height of the broadened portion 220 b 1 of the second gate 220 b substantially equals to the height of the semiconductor fin 208. The broadened portion 220 b 1 has a first sidewall SW5 and a second sidewall SW6 opposite to the first sidewall SW5, the broadened portion 220 b 1 has a recess R located at the first sidewall SW5 for accommodating the end of the semiconductor fin 208, and the second sidewall SW6 of the broadened portion 220 b 1 is a tapered sidewall. In other words, the broadened portion 220 b 1 of the second gate 220 b is an asymmetric geometry.
The semiconductor fin 208 is not in contact with the second gate 220 c and the second gate 220 c includes a broadened portion 220 c 1 disposed on the dielectric layer 212 and a top portion 220 c 2 disposed on the broadened portion 220 c 1, wherein a bottom width BCD2 of the broadened portion 220 c 1 is greater than a width TCD2 of the top portion 220 c 2. The width TCD2 of the top portion 220 c 2 keeps constant in the thickness direction D3, and a top width (TCD2) of the broadened portion 220 c 1 is substantially equal to width TCD2 of the top portion 220 c 2. The height of the broadened portion 220 c 1 of the second gate 220 c substantially equals to the height of the semiconductor fin 208. The broadened portion 220 c 1 has a first sidewall SW7 and a second sidewall SW8 opposite to the first sidewall SW7, and the first sidewall SW7 and the second sidewall SW8 of the broadened portion 220 c 1 are tapered sidewalls. In other words, the broadened portion 220 c 1 of the second gate 220 c is a symmetric geometry.
The first gate 220 a serves as gate electrode of a FinFET while the second gates 220 b and 220 c function as dummy gates. In other words, channel region of the semiconductor fin 208 is covered by the first gate 220 a and portions of the semiconductor fin 208 that are covered by the second gates 220 b and 220 c do not serve as channel regions of FinFETs. Since the above-mentioned second dummy gate strips 214 b and 214 c includes broadened portions 214 b 1 and 214 c 1, process window of gate replacement process is enlarged. Therefore, yield and reliability of the semiconductor device are enhanced.
In accordance with some embodiments of the present disclosure, a method for fabricating a semiconductor device includes at least the following steps. A substrate is patterned to form a plurality of trenches in the substrate and a semiconductor fin between the trenches. A plurality of insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A first dummy gate strip and a second dummy gate strip are formed on the dielectric layer, wherein a lengthwise direction of the first and second dummy gate strips is different from a lengthwise direction of the semiconductor fin, wherein the first dummy gate strip is penetrated by the semiconductor fin, the second dummy gate strip is not penetrated through by the semiconductor fin, and a bottom width of the second dummy gate strip is greater than a top width of the second dummy gate strip. A pair of first spacers and a pair of second spacer are formed on sidewalls of the first dummy gate strip and the second dummy gate strip respectively. The first and second dummy gate strips are removed. A first gate and a second gate are formed between the pair of first spacers and the pair of second spacers respectively.
In accordance with alternative embodiments of the present disclosure, a semiconductor device including a substrate, a plurality of insulators, a dielectric layer, a first gate and a second gate is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. The first gate is disposed on the dielectric layer and is penetrated by the semiconductor fin. The second gate is disposed on the dielectric layer, wherein a lengthwise direction of the first and second gates is different from a lengthwise direction of the semiconductor fin, the second gate is not penetrated through by the semiconductor fin, and a bottom width of the second gate is greater than a top width of the second gate.
In accordance with yet alternative embodiments of the present disclosure, a semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (16)

What is claimed is:
1. A semiconductor device, comprising:
a substrate comprising a plurality of trenches and a semiconductor fin between trenches;
a plurality of insulators in the trenches;
a dielectric layer covering the semiconductor fin and the insulators;
a first gate disposed on the dielectric layer, the first gate being penetrated by the semiconductor fin; and
a second gate disposed on the dielectric layer, a lengthwise direction of the first and second gates being different from a lengthwise direction of the semiconductor fin, wherein the second gate is not penetrated through by the semiconductor fin, and a bottom width of the second gate is greater than a top width of the second gate.
2. The semiconductor device of claim 1, wherein an end of the semiconductor fin is embedded in the second gate.
3. The semiconductor device of claim 2, wherein the second gate comprises:
a broadened portion disposed on the dielectric layer; and
a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.
4. The semiconductor device of claim 3, wherein a height of the broadened portion of the second gate substantially equals to a height of the semiconductor fin.
5. The semiconductor device of claim 3, wherein the broadened portion has a first sidewall and a second sidewall opposite to the first sidewall, the broadened portion has a recess located at the first sidewall for accommodating the end of the semiconductor fin, and the second sidewall of the broadened portion is a tapered sidewall.
6. The semiconductor device of claim 1, wherein the semiconductor fin is not in contact with the second gate.
7. The semiconductor device of claim 6, wherein the second gate comprises:
a broadened portion disposed on the dielectric layer; and
a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.
8. The semiconductor device of claim 7, wherein a height of the broadened portion of the second gate substantially equals to a height of the semiconductor fin.
9. The semiconductor device of claim 7, wherein the broadened portion has a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall and the second sidewall of the broadened portion are tapered sidewalls.
10. A semiconductor device, comprising:
a substrate comprising a plurality of trenches and a semiconductor fin between trenches;
a plurality of insulators in the trenches;
a dielectric layer covering the semiconductor fin and the insulators;
a plurality of gates disposed on the dielectric layer, a lengthwise direction of the gates being different from a lengthwise direction of the semiconductor fin, the gates comprising at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin, the second gate comprising:
a broadened portion disposed on the dielectric layer; and
a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.
11. The semiconductor device of claim 10, wherein an end of the semiconductor fin is embedded in the second gate.
12. The semiconductor device of claim 11, wherein a height of the broadened portion of the second gate substantially equals to a height of the semiconductor fin.
13. The semiconductor device of claim 11, wherein the broadened portion has a first sidewall and a second sidewall opposite to the first sidewall, the broadened portion has a recess located at the first sidewall for accommodating the end of the semiconductor fin, and the second sidewall of the broadened portion is a tapered sidewall.
14. The semiconductor device of claim 10, wherein the semiconductor fin is not in contact with the second gate.
15. The semiconductor device of claim 14, wherein a height of the broadened portion of the second gate substantially equals to a height of the semiconductor fin.
16. The semiconductor device of claim 14, wherein the broadened portion has a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall and the second sidewall of the broadened portion are tapered sidewalls.
US14/985,406 2015-12-31 2015-12-31 Fin semiconductor device having multiple gate width structures Active US9704969B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/985,406 US9704969B1 (en) 2015-12-31 2015-12-31 Fin semiconductor device having multiple gate width structures
TW105137193A TWI710030B (en) 2015-12-31 2016-11-15 Semiconductor device and fabricating method of semiconductor device
CN201611021154.4A CN107026125B (en) 2015-12-31 2016-11-15 Semiconductor device and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/985,406 US9704969B1 (en) 2015-12-31 2015-12-31 Fin semiconductor device having multiple gate width structures

Publications (2)

Publication Number Publication Date
US20170194458A1 US20170194458A1 (en) 2017-07-06
US9704969B1 true US9704969B1 (en) 2017-07-11

Family

ID=59226769

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/985,406 Active US9704969B1 (en) 2015-12-31 2015-12-31 Fin semiconductor device having multiple gate width structures

Country Status (3)

Country Link
US (1) US9704969B1 (en)
CN (1) CN107026125B (en)
TW (1) TWI710030B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361280B2 (en) 2017-08-30 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure for semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102287271B1 (en) 2014-06-26 2021-08-06 인텔 코포레이션 Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same
US10020304B2 (en) * 2015-11-16 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
KR102652370B1 (en) * 2017-02-15 2024-03-27 삼성전자주식회사 Thin film transistor, making method thereof, and electronic device comprising thereof
TWI754722B (en) 2018-02-13 2022-02-11 聯華電子股份有限公司 Layout of semiconductor device, semiconductor device and method of forming the same

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001692A (en) * 1996-10-22 1999-12-14 Lg Semicon Co., Ltd. Method of fabricating trench MOS
US20050250285A1 (en) * 2004-05-04 2005-11-10 Jae-Man Yoon Fin field effect transistor device and method of fabricating the same
US20110068405A1 (en) * 2009-09-24 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor
US20120261726A1 (en) * 2011-04-14 2012-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Divot engineering for enhanced device performance
US8659097B2 (en) * 2012-01-16 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Control fin heights in FinFET structures
US8664064B2 (en) * 2006-05-13 2014-03-04 Samsung Electronics Co., Ltd. Fin field effect transistor and method for forming the same
US9048219B2 (en) * 2013-07-15 2015-06-02 Samsung Electronics Co., Ltd. High integration semiconductor device and method for fabricating the same
US9070577B2 (en) * 2012-12-24 2015-06-30 SK Hynix Inc. Semiconductor device having fin structure in peripheral region and method for forming the same
US20150187571A1 (en) * 2013-12-27 2015-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium-Containing FinFET and Methods for Forming the Same
US20150206956A1 (en) * 2014-01-21 2015-07-23 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20150206890A1 (en) * 2012-11-14 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cell Layout for SRAM FinFET Transistors
US20150236131A1 (en) * 2014-02-14 2015-08-20 Taiwan Semiconductor Manufacturing Co., Ltd Fin field effect transistor (finfet) device and method for forming the same
US20150311342A1 (en) * 2014-04-23 2015-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Finfet with esd protection
US20160049400A1 (en) * 2014-06-26 2016-02-18 Globalfoundries Inc. Threshold voltage control for mixed-type non-planar semiconductor devices
US9306037B2 (en) * 2012-06-29 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy gate electrode of semiconductor device
US20160111449A1 (en) * 2012-06-28 2016-04-21 Walid M. Hafez High voltage three-dimensional devices having dielectric liners
US20160163799A1 (en) * 2014-12-04 2016-06-09 So-Yeon Kim Semiconductor devices and methods of manufacturing the same
US20160225764A1 (en) * 2015-01-30 2016-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9537010B2 (en) * 2015-02-04 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US20170005005A1 (en) * 2015-07-02 2017-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finfet) device structure and method for forming the same
US9548309B2 (en) * 2014-05-08 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor devices including a dummy gate structure on a fin

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927353B2 (en) * 2007-05-07 2015-01-06 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method of forming the same
CN101587839B (en) * 2008-05-23 2011-12-21 清华大学 Method for producing thin film transistors
US8624326B2 (en) * 2011-10-20 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8872228B2 (en) * 2012-05-11 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel semiconductor device fabrication
JP2014120661A (en) * 2012-12-18 2014-06-30 Tokyo Electron Ltd Method of forming dummy gate
US9276087B2 (en) * 2013-05-10 2016-03-01 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001692A (en) * 1996-10-22 1999-12-14 Lg Semicon Co., Ltd. Method of fabricating trench MOS
US20050250285A1 (en) * 2004-05-04 2005-11-10 Jae-Man Yoon Fin field effect transistor device and method of fabricating the same
US8664064B2 (en) * 2006-05-13 2014-03-04 Samsung Electronics Co., Ltd. Fin field effect transistor and method for forming the same
US20110068405A1 (en) * 2009-09-24 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor
US20120261726A1 (en) * 2011-04-14 2012-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Divot engineering for enhanced device performance
US8659097B2 (en) * 2012-01-16 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Control fin heights in FinFET structures
US20160111449A1 (en) * 2012-06-28 2016-04-21 Walid M. Hafez High voltage three-dimensional devices having dielectric liners
US9306037B2 (en) * 2012-06-29 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy gate electrode of semiconductor device
US20150206890A1 (en) * 2012-11-14 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cell Layout for SRAM FinFET Transistors
US9070577B2 (en) * 2012-12-24 2015-06-30 SK Hynix Inc. Semiconductor device having fin structure in peripheral region and method for forming the same
US9048219B2 (en) * 2013-07-15 2015-06-02 Samsung Electronics Co., Ltd. High integration semiconductor device and method for fabricating the same
US20150187571A1 (en) * 2013-12-27 2015-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium-Containing FinFET and Methods for Forming the Same
US20150206956A1 (en) * 2014-01-21 2015-07-23 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20150236131A1 (en) * 2014-02-14 2015-08-20 Taiwan Semiconductor Manufacturing Co., Ltd Fin field effect transistor (finfet) device and method for forming the same
US20150311342A1 (en) * 2014-04-23 2015-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Finfet with esd protection
US9548309B2 (en) * 2014-05-08 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor devices including a dummy gate structure on a fin
US20160049400A1 (en) * 2014-06-26 2016-02-18 Globalfoundries Inc. Threshold voltage control for mixed-type non-planar semiconductor devices
US20160163799A1 (en) * 2014-12-04 2016-06-09 So-Yeon Kim Semiconductor devices and methods of manufacturing the same
US20160225764A1 (en) * 2015-01-30 2016-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9537010B2 (en) * 2015-02-04 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US20170005005A1 (en) * 2015-07-02 2017-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finfet) device structure and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361280B2 (en) 2017-08-30 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure for semiconductor device
US10741672B2 (en) 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co. Ltd. Gate structure for semiconductor device

Also Published As

Publication number Publication date
CN107026125A (en) 2017-08-08
US20170194458A1 (en) 2017-07-06
TWI710030B (en) 2020-11-11
TW201724280A (en) 2017-07-01
CN107026125B (en) 2022-11-11

Similar Documents

Publication Publication Date Title
US20200243520A1 (en) Semiconductor device
US9461044B1 (en) Fin field effect transistor, semiconductor device and fabricating method thereof
US10872968B2 (en) Semiconductor device
US10727132B2 (en) Fin field effect transistor, semiconductor device and method for fabricating the same
US11018261B2 (en) Fin field effect transistor
US20170140992A1 (en) Fin field effect transistor and method for fabricating the same
US9773871B2 (en) Fin field effect transistor and method for fabricating the same
US10811412B2 (en) Method of fabricating semiconductor device
US9704752B1 (en) Fin field effect transistor and method for fabricating the same
US9704969B1 (en) Fin semiconductor device having multiple gate width structures
US9691766B1 (en) Fin field effect transistor and method for fabricating the same
US9620503B1 (en) Fin field effect transistor and method for fabricating the same
US10158023B2 (en) Fabricating method of fin field effect transistor
US9716093B1 (en) Semiconductor device
US10109739B2 (en) Fin field effect transistor
US9553191B1 (en) Fin field effect transistor and method for fabricating the same
US9929268B2 (en) Fin field effect transistor and method for fabricating the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, CHE-CHENG;LIN, CHIH-HAN;TSENG, HORNG-HUEI;SIGNING DATES FROM 20151224 TO 20151229;REEL/FRAME:037388/0362

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4