CN114093766A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
本发明公开一种半导体装置及其制造方法,其中该半导体装置的制造方法包括:形成第一晶体管。所述第一晶体管的形成方法包括:在衬底中形成多个淡掺杂区;在所述衬底上形成第一栅极结构,所述第一栅极结构覆盖部分所述多个淡掺杂区及部分所述衬底;在所述第一栅极结构的侧壁形成多个第一间隙壁;在所述多个淡掺杂区中形成多个掺杂区;在所述衬底上形成刻蚀停止层;图案化所述刻蚀停止层与所述第一栅极结构,以形成第二栅极结构,并在所述第二栅极结构与所述多个第一间隙壁之间形成多个沟槽;以及在所述衬底上形成第一介电层,以覆盖所述刻蚀停止层并填入所述多个沟槽中。填入所述多个沟槽中的第一介电层作为多个虚设间隙壁。
Description
技术领域
本发明涉及一种集成电路及其制造方法,且特别是涉及一种半导体装置及其制造方法。
背景技术
随着装置尺寸不断缩小,不仅栅极的宽度减少,间隙壁的宽度也随之减小。然而,对于同时包含两种不同操作电压的半导体装置而言,若依照操作电压较小的装置形成间隙壁,则操作电压较大的装置会因为间隙壁的宽度不足而造成栅极诱发漏极漏电流(GIDL)变大以及漏电流(IOFF)的变异变大。
发明内容
本发明实施例针对一种半导体装置,可以避免间隙壁的宽度不足而造成栅极诱发漏极漏电流(GIDL)变大以及漏电流(IOFF)的变异变大等问题。
本发明实施例针对一种半导体装置的制造方法,可以与现有工艺兼容并可增加工艺窗。
根据本发明的实施例,提出一种半导体装置的制造方法,包括:形成第一晶体管,包括:在衬底中形成多个淡掺杂区;在所述衬底上形成第一栅极结构,所述第一栅极结构覆盖部分所述多个淡掺杂区及部分所述衬底;在所述第一栅极结构的侧壁形成多个第一间隙壁;在所述多个第一间隙壁两侧以及所述多个淡掺杂区中形成多个掺杂区;在所述衬底上形成刻蚀停止层,以覆盖所述第一栅极结构、所述多个第一间隙壁以及所述多个掺杂区;图案化所述刻蚀停止层与所述第一栅极结构,以形成第二栅极结构,并在所述第二栅极结构与所述多个第一间隙壁之间形成多个沟槽;以及在所述衬底上形成第一介电层,以覆盖所述刻蚀停止层并填入所述沟槽中。填入所述沟槽中的第一介电层作为多个虚设间隙壁。
根据本发明的实施例,提出一种半导体装置,其特征在于包括:第一晶体管,包括:多个淡掺杂区,彼此分离,位于衬底中;第一栅极结构,覆盖部分所述多个淡掺杂区及部分所述衬底;多个第一间隙壁,侧向位于所述第一栅极结构旁;多个第一掺杂区,位于所述多个第一间隙壁两侧的所述多个淡掺杂区中;刻蚀停止层,覆盖所述多个第一间隙壁与所述掺杂区;介电层,覆盖所述刻蚀停止层;多个接触窗,穿过所述介电层与所述刻蚀停止层,与所述多个第一掺杂区电连接;以及多个虚设间隙壁,位于所述第一栅极结构与所述多个第一间隙壁之间,其中所述虚设间隙壁与所述介电层的材料相同。
基于上述,本发明的实施例中,通过在栅极导体层与间隙壁之间形成虚设间隙壁可以增加接触窗与栅极导体层之间的距离,使得晶体管可以符合所需的操作电压。此外,本发明实施例的形成虚设间隙壁的工艺可以与现有工艺兼容并可增加工艺窗,而且可以避免操作电压较大的晶体管的间隙壁的宽度太小而造成栅极诱发漏极漏电流变大以及漏电流的变异变大等问题。
附图说明
图1A至图1I是本发明实施例的一种半导体装置的制造方法的剖面示意图;
图2是图1I的上视图;
图3是本发明实施例的一种半导体装置的制造方法的剖面示意图;
图4A至图4D是本发明另一实施例的一种半导体装置的制造方法的剖面示意图;
图5是图4D的上视图;
图6A至图6B是本发明又一实施例的一种半导体装置的制造方法的剖面示意图。
具体实施方式
现将详细地参考本发明的示范性实施例,示范性实施例的实例说明于附图中。只要有可能,相同元件符号在附图和描述中用来表示相同或相似部分。
参照图1A,提供衬底100。衬底100为半导体衬底,例如是掺杂硅衬底、未掺杂硅衬底、绝缘体上覆硅(SOI)衬底或外延衬底。衬底100中已形成阱区102,且在阱区102中已形成阱区104。衬底100与阱区104例如是具有第一导电型掺质,而阱区102例如是具有第二导电型掺质。第二导电型与第一导电型相反。举例来说,第一导电型例如是P型;第二导电型例如是N型,反之亦然。P型掺质例如是硼、氟化硼(BF2)、铟(In)或其组合。N型掺质例如是磷、砷或其组合。接着,在阱区104中形成淡掺杂区106。淡掺杂区106可以在衬底100上形成掩模层PR1,然后经由离子注入工艺IMP1来形成的。掩模层PR1例如是图案化的光刻胶层。
参照图1B,移除掩模层PR1。之后,在衬底100上形成栅介电层108。栅介电层108例如是氧化硅、氮化硅或是介电常数大于4的高介电常数材料或其组合。高介电常数材料可以是金属氧化物,例如稀土金属氧化物。稀土金属氧化物如氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO)、硅酸铪氮氧化合物(hafnium siliconoxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化钇(yttrium oxide,Y2O3)氧化镧(lanthanum oxide,La2O3)、铝酸镧(lanthanum aluminum oxide,LaAlO)、氧化钽(tantalum oxide,Ta2O5)、氧化锆(zirconium oxide,ZrO2)、硅酸锆氧化合物(zirconiumsilicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO)或锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT),或其组合。栅介电层108的形成方法例如是化学气相沉积法或原子层沉积法(ALD)。
接着,在栅介电层108上形成栅极导体层110。栅极导体层110覆盖在部分的栅介电层108上。栅极导体层110的形成方法例如是在栅介电层108上形成导体材料层,然后经由光刻与刻蚀工艺进行图案化。导体材料层的材料例如是掺杂的多晶硅或是未掺杂的多晶硅。在一些实施例中,还在栅极导体层110上形成顶盖层(未示出)。顶盖层为介电材料,例如是氧化硅或是氮化硅。栅介电层108、栅极导体层110以及顶盖层可合称为栅极结构GS1。
接着,在栅极导体层110的侧壁形成间隙壁112。间隙壁112的形成方法可以先形成间隙壁材料层,然后,再进行各向异性刻蚀工艺。间隙壁112的材料包括氮化硅、氧化硅或其组合。间隙壁112可以是单层或是双层。在一些实施例中,间隙壁112为包括内间隙壁112a与外间隙壁112b的双层结构。内间隙壁112a为氧化硅,外间隙壁112b为氮化硅。内间隙壁112a例如是呈I型或是L型,外间隙壁112b例如是呈I型。在一些示例实施例中,图1B的区A的内间隙壁112a呈L型,外间隙壁112b呈I型,如,局部放大图A’所示。外间隙壁112b位于内间隙壁112a的垂直部的侧壁,并覆盖在内间隙壁112a的水平部的上表面上。在另一些示例实施例中,图1B的区A的内间隙壁112a与外间隙壁112b均呈I型,如局部放大图A”所示。外间隙壁112b位于内间隙壁112a的侧壁上。
其后,进行离子注入工艺IMP2,以在间隙壁112两侧的淡掺杂区106中形成掺杂区114。掺杂区114又可称为浓掺杂区。掺杂区114具有第二导电型掺质,例如是磷、砷或其组合。之后,可以再进行退火工艺,以活化掺杂区114中的掺质。
参照图1B,在掺杂区114上形成金属硅化物层115。金属硅化物层115可以采用自行对准硅化物(self-aligned silicide,salicide)工艺来形成。金属硅化物层115包括的形成方法例如是先在衬底100上形成金属层。金属层的材料可以是钛、钼、钴、镍、铂或钨。金属层的形成方法例如是物理气相沉积法。之后,进行退火工艺,以使金属层反应形成金属硅化物层115。其后金属层移除。当栅极导体层110上没有覆盖顶盖层时,栅极导体层110亦会形成金属硅化物层115。当栅极导体层110上有覆盖顶盖层时,栅极导体层110则不会形成金属硅化物层115。
参照图1C,在形成金属硅化物层115之后,在衬底100上形成刻蚀停止层116。刻蚀停止层116的材料例如是氮化硅、氮氧化硅、碳化硅或其组合。刻蚀停止层116的形成的方法例如是化学气相沉积法。接着,在刻蚀停止层116上形成掩模层PR2。掩模层PR2具有开口OP1,裸露出栅极导体层110边缘上方的刻蚀停止层116。掩模层PR2例如是图案化的光刻胶层。开口OP1可以通过曝光与显影光刻胶层而形成。在一些实施例中,开口OP1的侧壁对准栅极导体层110的侧壁。在另一些实施例中,开口OP1的侧壁未对准栅极导体层110的侧壁,如图4A所示,其后再详述。
参照图1D,进行刻蚀工艺,例如是各向异性刻蚀工艺,以移除开口OP1所裸露的刻蚀停止层116以及栅极导体层110,以形成栅极导体层110a与沟槽OP2。在一些实施例中,沟槽OP2的侧壁裸露出刻蚀停止层116、栅极导体层110以及间隙壁112,沟槽OP2的底部裸露出栅介电层118。由于形成了沟槽OP2,因此,栅极导体层110a的宽度W12比栅极导体层110的宽度W11小。
参照图1E,移除掩模层PR2。接着,在刻蚀停止层116上以及沟槽OP2中形成介电层118。介电层118的材料可以是氧化硅、磷硅玻璃、硼磷硅玻璃、氮化硅、氮氧化硅、碳化硅(SiC)、氮碳化硅(SiCN)、氮碳氧化硅(SiCON)或其组合。介电层118的形成方法例如是化学气相沉积法或是旋涂法。
参照图1F,进行平坦化工艺,例如是化学机械抛光工艺,以移除部分的介电层118以及部分的刻蚀停止层116,使栅极导体层110a的顶面裸露出来,留下介电层118a、虚设间隙壁118b以及刻蚀停止层116a。介电层118a覆盖在刻蚀停止层116a上。虚设间隙壁118b留在沟槽OP2之中,且介于栅极导体层110a以及间隙壁112之间。
参照图1G与1H,在一些实施例中,更进一步进行金属栅极取代工艺,将栅极导体层110a取代为栅极导体层120。金属栅极取代工艺的工艺可以采用以下所述的方法来进行。首先,进行刻蚀工艺,例如是各向异性刻蚀工艺,以移除栅极导体层110a,裸露出栅介电层108,以形成栅极沟槽GT。在一些实施例中,栅介电层108不是高介电常数材料层,而仅是氧化硅层,则可以先在栅极沟槽GT中先形成高介电常数材料层。在另一些实施例中,栅介电层108为高介电常数材料层。之后,在衬底100上以及栅极沟槽GT中形成功函数层122。功函数层122的材料包括P型功函数层或N型功函数层。所述P型功函数层包含选自但不仅限于以下群组的具有足够大的有效功函数的金属:氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)、或其组合。所述P型功函数层包含选自但不仅限于以下群组的具有足够低的有效功函数的金属:钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(tantalum carbide nitride,TaCN)、氮化钽硅(TaSiN)、或其组合。
接着,将金属填充层124形成在功函数层122上,并填满栅极沟槽GT。金属填充层124可包含铝(Al)、钨(W)、钴(Co)、铜(Cu)、及/或其他适合的材料。在一些实施例中,在功函数层122与金属填充层124之间还可以包括阻障层(未示出)。在另一些实施例中,在功函数层122与栅介电层108之间还可以包括高介电常数材料层(未示出)。在另一些实施例中,在功函数层122与栅介电层108之间还可以包括缓冲层。其后,进行平坦化工艺,例如是化学机械平坦化工艺,以移除栅极沟槽GT以外的金属填充层124与功函数层122。留在栅极沟槽GT之中的金属填充层124与功函数层122合称为栅极导体层120。栅极导体层120与栅介电层108合称为栅极结构GS1’。
参照图1I,在衬底100上形成另一介电层126。介电层126的材料可以与介电层118a的材料相同或是相异。介电层126的材料化硅、磷硅玻璃、硼磷硅玻璃、氮化硅、氮氧化硅、碳化硅(SiC)、氮碳化硅(SiCN)、氮碳氧化硅(SiCON)、介电常数低于4的介电材料或其组合。介电层126形成的方法例如是化学气相沉积法或是旋涂法。介电层126也可以选择性进行平坦化工艺,例如是化学机械抛光工艺,以使其具平坦的顶面。
之后,在介电层126中形成与金属硅化物层115电连接的接触窗132。接触窗132的形成方法例如是在介电层126与118a以及刻蚀停止层116中形成接触窗开口。在一些实施例中,金属硅化物层115也可以在接触窗开口形成之后才形成。然后,在接触窗开口中填入金属层130。金属层130的材料例如是钨、铜或其他合适的材料。金属层130的形成方法可以物理气相沉积法、化学气相沉积法或其组合。在一些实施例中,在形成金属层130之前,还先形成阻障层128。阻障层128可以是共形层。阻障层128可以是单层或是双层。阻障层128的材料包括金属、金属氮化物或其组合。阻障层128的材料钽、钛、氮化钽、氮化钛或其他合适的材料。阻障层128的形成方法可以是物理气相沉积法、化学气相沉积法或其组合。在形成阻障层128与金属层130之后,进行平坦化工艺,例如是化学机械抛光工艺,以移除接触窗开口以外的阻障层128与金属层130,使留下的阻障层128与金属层130作为接触窗132。
参照图1I与图2,在本实施例中,栅极结构GS1’、间隙壁112、虚设间隙壁118b、淡掺杂区106以及掺杂区114形成晶体管T1。栅极结构GS1’包括栅极导体层120与栅介电层108。栅极导体层120设置在栅介电层108上。栅介电层108设置在栅极导体层120下方,并延伸至间隙壁112的下方。间隙壁112设置在栅极导体层120的两侧,未与栅极导体层120直接接触。虚设间隙壁118b设置于栅极导体层120与间隙壁112之间以及栅介电层108的上方。在一些实施例中,在栅极导体层120的两侧的虚设间隙壁118b以及间隙壁112大致对称。在另一些实施例中,在栅极导体层120的两侧的虚设间隙壁118b以及间隙壁112不对称,如图4D所示,其后再详述。淡掺杂区106彼此分隔,且被栅极结构GS1’、虚设间隙壁118b以及间隙壁112覆盖。掺杂区114位于间隙壁112旁的淡掺杂区106之中。接触窗132通过金属硅化物层115与掺杂区114电连接。
掺杂区114具有侧壁114S1与114S2。掺杂区114的侧壁114S1靠近栅极导体层120。掺杂区114的侧壁114S2远离栅极导体层120。掺杂区114的侧壁114S1与栅极导体层120的侧壁120S2之间具有距离d11。接触窗132具有侧壁132S1与132S2。接触窗132的侧壁132S1靠近栅极导体层120。接触窗132的侧壁132S2远离栅极导体层120。接触窗132的侧壁132S1与掺杂区114的侧壁114S1之间具有距离d12。在本实施例中,距离d11大于距离d12。此外,接触窗132与栅极导体层120也具有足够的距离(为距离d11与d12的和),因此可以避免间隙壁112的宽度W14太小而造成的栅极诱发漏极漏电流变大以及漏电流的变异变大等问题。
在一些示例中,栅极导体层120的宽度W12例如是0.6至1.4微米。虚设间隙壁118b的宽度W13例如是0.052~0.056微米。间隙壁112的宽度W14例如是0.024~0.026微米。间隙壁112具有相对的侧壁112S1与112S2。间隙壁112的侧壁112S1与虚设间隙壁118b接触,且间隙壁112的侧壁112S1与接触窗132的侧壁132S1之间的距离d13例如是0.025~0.029微米。
参照图3,在一些实施例中,上述晶体管T1形成在衬底100的区域R1,且在形成晶体管T1的同时,也在衬底100的区域R2中形成晶体管T2。晶体管T2包括栅极结构GS2’、间隙壁212、淡掺杂区206与掺杂区214。掺杂区214上有金属硅化物层215。栅极结构GS2’包括栅极导体层220与栅介电层208。晶体管T2的操作电压小于晶体管T1的操作电压,且晶体管T2的栅极导体层220的宽度W22小于晶体管T1的栅极导体层120的宽度W12。
栅极结构GS2’的栅介电层208可与栅极结构GS1’的栅极导体层120同时形成或分别形成。在一些实施例中,栅介电层108与208的形成方法如下所述。进行热氧化工艺,以在区R1与R2的衬底100上同时形成厚氧化硅层,然后将区R2的衬底100上的厚氧化硅层移除。之后,再进行另一热工艺,以在区R2的衬底100上形成薄氧化层,此时区R1的厚氧化层无法再氧化,或仅能使得厚氧化层再些微氧化而使其厚度些微增加。
栅极导体层220设置在栅介电层208上。栅极导体层220可与栅极导体层120同时形成。然而,栅极导体层120是经过两次的图案化工艺使其从宽度W11减小为宽度W12,再进行栅极金属取代工艺。而栅极导体层220是经过一次的图案化工艺,因此其始终具有宽度W21。在一些实施例中,栅极导体层220的宽度W21例如是28纳米;栅极导体层120的宽度W12例如是1微米。
栅极导体层220包括功函数层222与金属填充层224。功函数层222与金属填充层224的材料可以分别与功函数层122与金属填充层124的材料相同或相似。栅介电层208设置在栅极导体层220下方,并延伸至间隙壁212的下方。晶体管T2不包括虚设间隙壁。间隙壁212设置在栅极导体层220的两侧,且与栅极导体层220直接接触。
淡掺杂区206与掺杂区214可以形成在衬底100中,或形成在衬底100的阱区(未示出)中。淡掺杂区206与掺杂区214具有相同的导电型,其可以具有与掺杂区114的导电型相同或相异。换言之,淡掺杂区206与掺杂区214可以具有第二导电型掺质或具有第一导电型掺质。淡掺杂区206彼此分隔,位于栅极导体层220两侧的衬底100中且被间隙壁212覆盖。掺杂区214位于间隙壁212旁的衬底100中,与淡掺杂区206相邻。在一些实施例中,淡掺杂区206与掺杂区214具有相同的导电型,掺杂区214可以与掺杂区114同时通过单一的离子注入工艺形成。在另一些实施例中,掺杂区214可以与掺杂区114分别通过离子注入工艺形成。
接触窗232通过金属硅化物层215与掺杂区214电连接。接触窗232可以与接触窗132同时形成。接触窗232包括阻障层228与金属层230。阻障层228与金属层230的材料可以分别与阻障层128与金属层130的材料相同或相似。
间隙壁212与间隙壁112同时形成,且间隙壁212与间隙壁112是由相同的材料形成,因此间隙壁212与间隙壁112具有相同的结构,且间隙壁212的宽度W24与间隙壁112的宽度W14大致相同。
晶体管T1的间隙壁112与栅极导体层120相隔非零距离,其彼此之间以虚设间隙壁118b相隔开。晶体管T2的间隙壁212与栅极导体层220直接接触,其彼此之间无虚设间隙壁。由于本发明在晶体管T1的间隙壁112与栅极导体层120之间设置的虚设间隙壁118b具有宽度W13,可以增加掺杂区114以及接触窗132与栅极导体层120之间的距离。换言之,掺杂区114的侧壁114S1与栅极导体层120的侧壁120S2之间的距离d11大于掺杂区114的侧壁114S1与栅极导体层120的侧壁120S2之间的距离d21。因此,操作电压较大的晶体管T1的间隙壁112与电压较小的晶体管T2的间隙壁212可以同时形成,且间隙壁112的宽度W14可以依照所需的间隙壁212的宽度W24形成。因此,本发明实施例的半导体装置不仅可以与现有工艺兼容,且可以使得晶体管T1与晶体管T2分别符合所需的操作电压,且可以避免晶体管T1的间隙壁112的宽度W14太小而造成栅极诱发漏极漏电流(GIDL)变大以及漏电流(IOFF)的变异变大等问题。
参照图4A至图4C,在另一实施例中,上述在形成开口OP1的过程中,若是发生错误对准,开口OP1将会偏移而未对齐栅极导体层110的侧壁,将会形成位置不同的沟槽OP2与OP2’,或导致间隙壁112具有不同的宽度W14与W14’。在一些实施例中,沟槽OP2与OP2’的宽度相同。在另一些实施例中,间隙壁112的刻蚀特性与栅极导体层110的刻蚀特性的不同,因而形成两个相对位置与宽度均不同的沟槽OP2与OP2’。沟槽OP2的侧壁仍裸露出刻蚀停止层116、栅极导体层110以及间隙壁112。沟槽OP2’的侧壁则裸露出刻蚀停止层116与栅极导体层110,而未裸露出间隙壁112。沟槽OP2与OP2’的宽度不同将造成后续形成的虚设间隙壁118b的宽度W13与虚设间隙壁118b’的宽度W13’不同。
此外,栅极导体层110将被分成两部分P1与P2。部分P1与P2在后续的工艺中,将被后续形成的虚设间隙壁118b分隔,如图4C与图5所示。若还进一步进行栅极导体层110的金属栅极取代工艺,则部分P1与P2将被金属取代为P1’与P2’,如图4D与图5所示。部分P1’的结构与上述的栅极导体层120相似,同样包括功函数层122与金属填充层124。部分P1’与部分P2’均为导体结构。部分P2’的宽度W12’小于部分P1’的宽度W12。在一些实施例中,部分P2’的宽度W12’足够大,且部分P2’的结构可以与部分P1’的结构相似,同样包括功函数层122与金属填充层124。在另一些实施例中,部分P2’的宽度W12’小,且部分P2’的部分P2’的结构可以仅包含功函数层122,而不具有金属填充层124。
在本实施例中,晶体管T1’具有左右不对称的结构,如图4D所示。在栅极导体层120的一侧的虚设间隙壁118b未与间隙壁112接触,且其彼此之间以部分P2’分隔;在栅极导体层120的另一侧的虚设间隙壁118b则与间隙壁112接触,且其彼此之间则无部分P2’。
请参照图6A,在另一实施例中,上述在形成沟槽OP2的刻蚀工艺还进一步移除栅介电层118,使得沟槽OP2的侧壁裸露出刻蚀停止层116、栅极导体层110、间隙壁112以及栅介电层118,且沟槽OP2的底部裸露出淡掺杂区106,如图6A所示。因此,后续形成的虚设间隙壁118b的底面将会与淡掺杂区106直接接触,如图6B所示。在一些实施例中,栅介电层118被过度刻蚀,使得沟槽OP2延伸到淡掺杂区106中,从而使得后续形成的虚设间隙壁118b的底面与下侧壁与淡掺杂区106直接接触。
综上所述,本发明的实施例中,操作电压较大的晶体管的间隙壁宽度可以依照电压较小的晶体管所需的间隙壁的宽度来制作,且通过在操作电压较大的晶体管的栅极导体层与间隙壁之间形成虚设间隙壁可以使得两个晶体管分别符合所需的操作电压。本发明实施例的形成虚设间隙壁的工艺可以与现有工艺兼容并可增加工艺窗,而且可以避免操作电压较大的晶体管的间隙壁的宽度太小而造成栅极诱发漏极漏电流变大以及漏电流的变异变大等问题。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (17)
1.一种半导体装置的制造方法,其特征在于,包括:
形成第一晶体管,包括:
在衬底中形成多个淡掺杂区;
在所述衬底上形成第一栅极结构,所述第一栅极结构覆盖部分所述多个淡掺杂区及部分所述衬底;
在所述第一栅极结构的侧壁形成多个第一间隙壁;
在所述多个第一间隙壁两侧以及所述多个淡掺杂区中形成多个掺杂区;
在所述衬底上形成刻蚀停止层,以覆盖所述第一栅极结构、所述多个第一间隙壁以及所述多个掺杂区;
图案化所述刻蚀停止层与所述第一栅极结构,以形成第二栅极结构,并在所述第二栅极结构与所述多个第一间隙壁之间形成多个沟槽;以及
在所述衬底上形成第一介电层,以覆盖所述刻蚀停止层并填入所述多个沟槽中,其中填入所述多个沟槽中的第一介电层作为多个虚设间隙壁。
2.根据权利要求1所述的半导体装置的制造方法,其中所述多个沟槽裸露出所述第一栅极结构的栅介电层。
3.根据权利要求1所述的半导体装置的制造方法,其中所述多个沟槽裸露出所述多个掺杂区。
4.根据权利要求1所述的半导体装置的制造方法,还包括:
在形成所述刻蚀停止层之前,在所述多个掺杂区上形成多个金属硅化物层。
5.根据权利要求1所述的半导体装置的制造方法,还包括:
对所述第一介电层进行平坦化工艺,直至裸露出所述第二栅极结构的顶面;
移除所述第二栅极结构的第一栅极导体层,以形成栅极沟槽;
在所述栅极沟槽中形成第二栅极导体层;
在所述底衬底上形成第二介电层;以及
形成贯穿在所述第二介电层、所述第一介电层以及所述刻蚀停止层且与所述多个掺杂区电连接的多个接触窗。
6.根据权利要求1所述的半导体装置的制造方法,还包括:
形成第二晶体管,其中所述第二晶体管的操作电压低于所述第一晶体管的操作电压,且所述第二晶体管的第三栅极结构与所述第一晶体管的所述第一栅极结构同时形成。
7.根据权利要求6所述的半导体装置的制造方法,其中:
所述第二晶体管的第二间隙壁与所述第一晶体管的所述第一间隙壁同时形成。
8.一种半导体装置,其特征在于,包括:
第一晶体管,包括:
多个淡掺杂区,彼此分离,位于衬底中;
第一栅极结构,覆盖部分所述多个淡掺杂区及部分所述衬底;
多个第一间隙壁,侧向位于所述第一栅极结构旁;
多个第一掺杂区,位于所述多个第一间隙壁两侧的所述多个淡掺杂区中;
刻蚀停止层,覆盖所述多个第一间隙壁与所述多个第一掺杂区;
介电层,覆盖所述刻蚀停止层;
多个接触窗,穿过所述介电层与所述刻蚀停止层,与所述多个第一掺杂区电连接;以及
多个虚设间隙壁,位于所述第一栅极结构与所述多个第一间隙壁之间,其中所述虚设间隙壁与所述介电层的材料相同。
9.根据权利要求8所述的半导体装置,其中所述多个虚设间隙壁与所述第一栅极结构以及所述多个第一间隙壁接触。
10.根据权利要求8所述的半导体装置,还包括导体结构,位于所述多个虚设间隙壁的其中之一与所述多个第一间隙壁的其中之一之间。
11.根据权利要求10所述的半导体装置,其中所述多个虚设间隙壁的所述其中之一介于所述导体结构与所述第一栅极结构之间且与其接触,且所述多个虚设间隙壁其中之另一与所述第一栅极结构以及所述多个第一间隙壁接触。
12.根据权利要求8所述的半导体装置,其中:
所述第一栅极结构的栅介电层延伸至所述多个虚设间隙壁与所述多个淡掺杂区之间以及所述多个第一间隙壁与所述多个淡掺杂区之间。
13.根据权利要求8所述的半导体装置,其中:
所述多个虚设间隙壁的底面与所述多个淡掺杂区接触。
14.根据权利要求8所述的半导体装置,其中所述多个虚设间隙壁的宽度大于所述多个第一间隙壁的宽度。
15.根据权利要求8所述的半导体装置,其中所述多个第一掺杂区的邻近所述第一栅极结构的第一侧壁与所述多个淡掺杂区的邻近所述第一栅极结构的所述第一侧壁之间具有第一距离,所述多个第一掺杂区的所述第一侧壁与所述多个接触窗的邻近所述第一栅极结构的第一侧壁之间具有第二距离,其中所述第一距离大于所述第二距离。
16.根据权利要求8所述的半导体装置,还包括:
第二晶体管,包括第二栅极结构、多个第二间隙壁与多个第二掺杂区,
其中所述第二晶体管的操作电压低于所述第一晶体管,且所述第二晶体管的多个第二间隙壁的宽度与所述第一晶体管的所述多个第一间隙壁的宽度相等。
17.根据权利要求16所述的半导体装置,其中
所述多个第一掺杂区的邻近所述第一栅极结构的第一侧壁与所述第一栅极结构的所述第一侧壁之间具有第一距离,
所述多个第二掺杂区的邻近所述第二栅极结构的第一侧壁与所述第二栅极结构的所述第一侧壁之间具有第二距离,
其中所述第一距离大于所述第二距离。
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