CN1797786A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

Info

Publication number
CN1797786A
CN1797786A CN200510124242.2A CN200510124242A CN1797786A CN 1797786 A CN1797786 A CN 1797786A CN 200510124242 A CN200510124242 A CN 200510124242A CN 1797786 A CN1797786 A CN 1797786A
Authority
CN
China
Prior art keywords
layer
etching stopping
semiconductor element
silicon
stopping layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200510124242.2A
Other languages
English (en)
Other versions
CN100399580C (zh
Inventor
陈忠义
关欣
陈枝城
叶任贤
张启宣
刘俊秀
宋自强
刘家玮
张介亭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN1797786A publication Critical patent/CN1797786A/zh
Application granted granted Critical
Publication of CN100399580C publication Critical patent/CN100399580C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种半导体元件及其制造方法，具体涉及一种用在高电压下的晶体管元件中的蚀刻停止层，该蚀刻停止层为一电阻率大于10ohm－cm的高电阻薄膜，当栅极电压超过5V时，可用来预防漏电流及改善崩溃电压。本发明的高电压元件的制造方法，可相容于低电压元件及中等电压元件的制程。

Description

半导体元件及其制造方法
技术领域
本发明有关于一种应用在高电压的晶体管元件，而特别有关于一种具有蚀刻停止层的高电压晶体管元件，其中蚀刻停止层可预防漏电流及改善崩溃电压。
背景技术
高电压元件可应用在多种领域中，包括：液晶显示器的驱动ICs、电源管理元件、电源供应器，非易失性存储器、通讯电路以及控制电路。其中较特别的是，液晶显示器的驱动IC需要在低电压或中等电压下以驱动相关的逻辑电路，而以高电压来驱动液晶显示器。由于单一晶片上的元件需要不同的崩溃电压，因此如何使高电压元件制程与低电压及中等电压元件制程相容为一重要问题。
一般而言，大部分金属氧化物半导体晶体管中会在栅极与源极/漏极区域之间加入一绝缘层，来降低沟道中的垂直电场。也可将绝缘层下的漂移区域(drift regions)与源极及漏极区域下的区域轻微掺杂，提供一必要的电压梯度。上述两种方法可增加源极及漏极区域中的接面崩溃电压，因此可使金属氧化物半导体晶体管在高电压下(例如电压大于5V)也可正常运作。DMOS(doublediffused drain MOS)为一种高电压晶体管，依其电流路径方向可归类为VDMOS(vertical DMOS)晶体管及LDMOS(lateralDMOS)晶体管。参照美国专利U.S.Pat.NO.6468870，揭露一种具有层间介电层的LDMOS晶体管的制造方法。
传统上，源极及漏极区域电性连接至层间介电层中的导电接触窗，且在电路结构上通常会形成一蚀刻停止层，使后续接触窗蚀刻制程中不会伤害到电路结构。U.S.Pat.NO.6630398揭露一种具有氮氧化硅蚀刻停止层的无边界接触窗。U.S.Pat.NO.6235653及U.S.Pat.NO.6316348揭露一种硅摩尔百分比介于约58％至62％的富硅氮氧化硅薄膜，这种富硅的氮氧化硅薄膜不足以在高电压元件应用中当作缓冲绝缘，因为富硅的氮氧化硅薄膜会在漏电流处引发额外的漏电流。额外的漏电流路径会在栅极至源极间引发大量漏电流，而降低栅极氧化物的崩溃电压。晶片可靠度测试显示，具有富硅氮氧化硅薄膜的高电压金属氧化物半导体晶体管无法通过GOI(gate oxide integrating)测试，且会引发时依性漏极电流。
发明内容
有鉴于此，本发明的目的就在于提供一高电压晶体管元件，具有电阻率超过10ohm-cm的蚀刻停止层，可预防漏电流及改善崩溃电压。
为达成上述目的，本发明提供一种高电压晶体管元件，其制造方法包括：提供一半导体基底；在一高电压元件区域上形成一栅极结构；在高电压元件区域及半导体基底上形成至少一扩散区域，且侧面地排列于栅极结构的侧壁；在栅极结构及扩散区域上形成一蚀刻停止层，其中蚀刻停止层的电阻率大于10ohm-cm；在该蚀刻停止层上形成一层间介电层，其中至少一接触窗穿过层间介电层及蚀刻停止层并露出扩散区域。蚀刻停止层选择自除富硅但氧化硅外的所有介电材料。
本发明的高电压晶体管元件包括：一栅极结构，置于一半导体基底的一高电压元件区域上；至少一扩散区域，形成在该高电压元件区域中，且侧面地位于该栅极结构的一侧或两侧；一蚀刻停止层，置于该栅极结构及该扩散区域之上，其中该蚀刻停止层的电阻率大于10ohm-cm；以及一层间介电层，置于该蚀刻停止层之上，且具有至少一接触窗，穿过该层间介电层及该蚀刻停止层。
本发明所述的半导体元件，该蚀刻停止层选择自除硅摩尔百分比超过55％的氮氧化硅外的所有介电材料。
本发明所述的半导体元件，该蚀刻停止层为一氮化硅层。
本发明所述的半导体元件，该蚀刻停止层包括一氧化硅层及一氮化硅层。
本发明所述的半导体元件，该蚀刻停止层为一硅摩尔百分比低于55％的氮氧化硅层。
本发明所述的半导体元件，该半导体元件为一操作电压超过5V的高电压晶体管。
本发明还提供一种半导体元件的制造方法，所述半导体元件的制造方法包括下列步骤：提供一半导体基底，具有一高电压元件区域；形成一栅极结构于该高电压元件区域上；在该高电压元件区域中形成至少一扩散区域，其中该扩散区域侧面地位于该栅极结构的一侧或两侧；在该栅极结构及该扩散区域上形成一蚀刻停止层，其中该蚀刻停止层的电阻率大于10ohm-cm；在该蚀刻停止层上形成一层间介电层；以及在该层间介电层中形成至少一接触窗，穿过该层间介电层及该蚀刻停止层。
本发明所述的半导体元件的制造方法，该蚀刻停止层选择自除硅摩尔百分比超过55％的氮氧化硅外的所有介电材料。
本发明所述的半导体元件的制造方法，该蚀刻停止层为一氮化硅层。
本发明所述的半导体元件的制造方法，该蚀刻停层包括一氧化硅层及一氮化硅层。
本发明所述的半导体元件的制造方法，该蚀刻停止层为一硅摩尔百分比低于55％的氮氧化硅层。
本发明所述半导体元件及其制造方法，其高电阻介电薄膜阻止栅极至源极间额外漏电流路径的产生，并改善栅极氧化层的崩溃电压，以通过GOI测试及解决时依性的问题。由于后段制程步骤大抵相同，因此本发明的高电压元件制程也与目前低电压元件制程及中等电压元件制程相容。
附图说明
图1为本发明实施例中非对称型NMOS元件的截面图；
图2为本发明实施例中非对称型PMOS元件的截面图；
图3为本发明实施例中隔离型NMOS元件的截面图；
图4为本发明实施例中隔离型PMOS元件的截面图；
图5为本发明实施例中对称型PMOS元件的截面图；
图6为本发明实施例中非对称型DDDMOS晶体管的截面图；
图7为本发明实施例中对称型DDDMOS晶体管的截面图。
具体实施方式
为了让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下：
本发明的较佳实施例提供一高电压晶体管元件，具有层间介电层及蚀刻停止层。本发明较佳实施例中的蚀刻停止层选择自除富硅氮氧化硅之外的任何介电材料，特别的是，本发明提供一电阻率大于10ohm-cm的高电阻介电薄膜来当作蚀刻停止层，配置在层间介电层之下，用来在高电压元件制程中形成接触窗，高电阻率的蚀刻停止层可达所需的绝缘效果，以预防晶体管元件中的栅极在高电压下运作时所产生的漏电流(例如当电压大于5V)。高电阻介电薄膜阻止栅极至源极间额外漏电流路径的产生，并改善栅极氧化层的崩溃电压，以通过GOI测试及解决时依性的问题。由于后段制程步骤大抵相同，因此本发明的高电压元件制程也与目前低电压元件制程及中等电压元件制程相容。
本说明书中“蚀刻停止层”是指形成在层间或之上并与其上的材料不同，且较佳具有较其上的材料慢的被蚀刻速率，作为蚀刻制程停止的指示。在本发明部分实施例中，蚀刻停止层为氮化硅(SixNy)的单层结构，其中x及y为原子组成比例，在此皆是指SiN。不管命名法，依形成SiN薄膜的沉积制程及参数薄膜实质上的成分可能为氢。本发明其他实施例中，蚀刻停止层为一复合材料层，包括氧化硅及氮化硅(SiN)。本发明另一实施例中，蚀刻停止层为一非富硅的氮氧化硅层，在此是指非富硅SixOyNz，其中x、y、z为原子组成比例，在此是指非富硅SiON。此外，氢也可为薄膜的组成。如本发明说明书中所述，非富硅是指SiON是指硅原子摩尔百分比小于约55％。例如，在本发明一实施例中非富硅SiON薄膜的硅、氧及氮原子组成比例约12∶21∶42，相较之下，传统的高电压元件中，非富硅SiON薄膜的硅、氧及氮原子组成比例约158∶72∶144。
本发明中，“高电压晶体管元件”是指一操作电压大于5V的MOS晶体管，一般在10V至80V之间。本发明可应用至多种工业，包括但不限于高电压应用的集成电路制造、微电子制造，光电制造，例如：液晶显示器的驱动IC、电源管理元件，电源供应器、非易失性存储器、通讯电路以及控制电路。特别的是，本发明提供一电压在12V至60V的液晶显示器最佳化高电压MOS晶体管。本发明可采用浅沟槽绝缘(STI)或局部硅氧化(LOCOS)绝缘技术来制造非对称型高电压MOS晶体管或对称型高电压MOS晶体管，其中高电压MOS晶体管依电流路径方向包括DMOS晶体管、LDMOS晶体管以及VDMOS晶体管。
在本发明实施例中，蚀刻停止层为一单层氮化硅层，在另一实施例中，蚀刻停止层为一复合层，包括一氧化硅层及一氮化硅层。在另一实施例中，蚀刻停止层为一非富含硅的氮氧化硅层，在此非富含硅的氮氧化硅是指硅摩尔百分比低于55％。
图1显示本发明一较佳实施例的非对称型NMOS元件，包括一半导体基底10，较佳为一P型半导体，包括一P型阱12及一N型阱14，形成在高电压元件区域中的主动区HV。半导体基底10包括但不限于硅、绝缘层上硅层(SOI)、绝缘层上硅锗或上述的组合。形成P阱区适合的掺杂物包括硼(B)及BF2，掺杂量约在6.0×1012至9.0×1012ions/cm2之间。形成N型阱适合的掺杂物包括砷(As)、锑(Sb)以及磷(P)，其掺杂量约在6.0×1012至9.0×1012ions/cm2之间。在半导体基底10中注入临界电压调整离子，形成临界电压调整区15。浅沟槽绝缘结构16a及16b形成在半导体基底10中来定义高电压元件主动区HV。一额外的浅沟槽绝缘结构18形成在部分主动区中。浅沟槽绝缘结构18较佳形成在N型阱中并靠近漏极。
接着以现有技术形成一栅极结构，包括一栅极介电层20及一栅极层22，其中有部分栅极结构形成在主动区上，部分形成在浅沟槽绝缘结构18之上。栅极介电层20例如是氧化硅、氮氧化硅、氮化硅、高介电常数k材料(例如k大于4)、过渡金属氧化物及稀土金属氧化物，可以现有沉积技术形成，例如：热氧化制程及化学气相沉积。栅极介电层20的厚度可视高电压元件技术的所需作调整。栅极层22的材料可为多晶硅、非晶质硅、掺杂的多晶硅、多晶硅锗、金属或上述的组合，栅极层22的制造方法可为化学气相沉积、溅镀或热成长制程。
之后以轻掺杂制程在半导体基底10中形成一轻掺杂漏极区(LDD)24，较佳为一形成在P型阱中的N-区。轻掺杂漏极区24的边缘大抵顺着栅极结构的侧壁排列。轻掺杂制程可在能量约1至100KeV下进行，掺杂量约1.0×1013至1.0×1015ions/cm2。接着以沉积及回蚀刻的方式，沿着栅极结构的侧壁形成介电间隙壁26。介电间隙壁26的材料例如是氮化硅、氧化硅、氮氧化硅、氮化硅及氧化硅的间隔层或上述的组合。接着以介电间隙壁26为掩膜，以一重掺杂制程分别在P型阱及N型阱中形成N+区，用来当作源极区28及漏极区30。源极区及漏极区的边界分别大抵顺着介电间隙壁侧壁的外部排列。漏极区30形成在浅沟槽绝缘18及16b之间的N型阱中，并与栅极结构间分隔出一段距离。重掺杂制程可在能量约1至100KeV下进行，掺杂量约5.0×1013至1.0×1016ions/cm2。接着利用耐火金属，例如：钴、钨、钛、镍在栅极层22、源极区28及漏极区30上选择性形成一金属硅化物层32，以降低电阻。
在半导体基底10上沉积一蚀刻停止层34，该蚀刻停止层34材料选择自除富含硅的氮氧化硅之外任何介电材料。其中较特别的是，蚀刻停止层34为一电阻率超过10ohm-cm的高电阻薄膜，可达所需的绝缘效果以阻止在高电压下(例如超过5V)栅极产生额外的漏电流沟道。在本发明实施例中，蚀刻停止层34为氮化硅层，可利用不同的沉积技术进行沉积，例如：低压化学气相沉积、等离子加强化学气相沉积。更具体来说，氮化硅层可通过SiH4、NH3、SiCl2H2或N2的混合，例如在压力约200mTorr至400mTorr之间，温度约300至800℃下沉积约100埃至1000埃。
本发明另一实施例中，蚀刻停止层34包括一氧化硅层及一氮化硅层。氧化硅层可利用各种沉积技术，例如：热氧化法、低压化学气相沉积、等离子加强化学气相沉积。更具体来说，氧化硅层通过SiH4及N2O两种反应物混合，以等离子加强化学气相沉积法沉积，另外也可利用低压化学气相沉积在温度约700至950℃之间沉积厚度10至1000埃。在本发明另一实施例中，利用一复合蚀刻停止层，例如：氧化硅/氮化硅或氮化硅/氧化硅的双层结构，而其中氧化硅层及氮化硅层厚度的选择则视实际介电需求而作适当调整。
在本发明另一实施例中，蚀刻停止层34为非富硅的氮氧化硅层，其硅的摩尔百分比低于55％，可利用各种沉积技术形成，例如：低压化学气相沉积、等离子加强化学气相沉积。在一实际应用上，利用N2O、SiH4、He或NH3、N2的混合以等离子加强化学气相沉积在温度约300至600℃之间，沉积厚度约100至1000埃。
将一层间介电层36沉积在蚀刻停止层34上，再以一化学机械研磨制程(CMP)进行抛光。层间介电层包括但不限于：二氧化硅、未掺杂硅酸盐玻璃(USG)、氟硅玻璃(FSG)、氟化四乙基正硅酸盐(FTEOS)、含硅倍半氧烷(HSQ)以及低介电常数材料(介电常数低于4)。层间介电层36的厚度约在3000至8000埃之间。
形成层间介电层之后，接着在层间介电层中形成多个接触窗38，并填满导电材料40以电性连接至源极区域28及漏极区域30。接触窗可利用传统的微影蚀刻技术完成，例如：在层间介电层上形成一光致抗蚀剂层，将接触窗图案转换至光致抗蚀剂层形成一接触窗图案的掩膜，进行一非等向性蚀刻制程，将未遮蔽部分的层间介电层移除。例如，当层间介电层为未掺杂硅玻璃或氟硅玻璃时，蚀刻制程可利用蚀刻气体包括：C4F8约10至20sccm、C2F6约10至20sccm、CO约30至50sccm及Ar。
接着再以另一蚀刻制程将蚀刻停止层未遮蔽的部分移除且不伤害到层间介电层36及金属硅化物层32。此蚀刻制程为一非等向性蚀刻，利用蚀刻气体，例如：O2、C2F6、C4F8、CH2F2及He，在压力约10至200mTorr蚀刻10至80秒。因此即在层间介电层36中完成接触窗38，并露出源极及漏极区域28、30上的金属硅化物层32。
图2显示本发明实施例的非对称型PMOS元件的截面图，相较于非对称性NMOS元件，形成在高电压区域的主动区域上的非对称性PMOS，更包括一置于N型阱14及P型阱12之下的N型埋层(NBL)11，其中轻掺杂漏极区24a为一形成在N型阱14中的P-区、源极区28为一形成在N型阱中的P+区、漏极区30为一形成在P型阱12中的P+区。
图3显示本发明实施例的隔离型NMOS元件的截面图，相较于非对称型NMOS元件，形成在高电压区域的主动区HV上的隔离型NMOS元件更包括一置于P型阱12及N型阱14之下的N型埋层(NBL)11，其中源极区28包括一N+区29a及一P+区29b。
图4显示本发明实施例的对称型NMOS元件的截面图，相较于非对称型NMOS元件，形成在高电压区域的主动区HV上的对称型NMOS元件包括两个被P型阱12分开的N型阱14a及14b，以及两浅沟槽绝缘结构18a及18b，分别形成在分开的N型阱14a及14b中。靠近源极的栅极结构置于部分浅沟槽绝缘结构18a及N型阱14a的邻近部分上。靠近漏极的栅极结构置于部分浅沟槽绝缘18b及N型阱14b邻近的部分上。
图5显示本发明实施例的对称型PMOS元件的截面图，相较于非对称型PMOS元件，形成在高电压区域的主动区HV上的对称型PMOS元件包括两浅沟槽绝缘结构18a及18b，分别形成在分开的P型阱12a及12b中。靠近源极的栅极结构，置于部分浅沟槽绝缘结构18a及P型阱12a的邻近部分上。靠近漏极的栅极结构，置于部分浅沟槽绝缘18b及P型阱12b邻近的部分上。
图6显示本发明实施例的非对称型DDDMOS晶体管的截面图，相较于非对称型LDMOS晶体管，非对称型DDDMOS晶体管包括两场氧化区17a及17b，形成在半导体基底10中，用来定义高电压元件区的主动区HV。场氧化区17a及17b可以现有LOCOS绝缘技术来形成。扩散延伸区31邻近于靠近漏极区的栅极结构，并环绕漏极区30以建构出双扩散漏极区。扩散延伸区31具有相对较大的面积及较轻微的掺杂量，而漏极区具有相对较小的区域及相对较重的掺杂量。作为NMOS的基底，扩散延伸区域31为掺杂量约6.0×1012至9.0×1012ions/cm2的N型区域，而漏极区30及源极区28为掺杂量约5.0×1013至1.0×1016ions/cm2的N+区域。作为PMOS晶体管的基底，扩散延伸区31为一掺杂量约6.0×1012至9.0×1012ions/cm2的P型区域，而漏极30及源极区28为掺杂量约5.0×1013至1.0×1016ions/cm2的P+区域。
图7显示本发明实施例的对称型DDDMOS晶体管的截面图，相较于非对称型DDDMOS晶体管，对称型DDDMOS晶体管包括两隔开的扩散延伸区31a及31b，介于两场氧化区17a及17b之间。扩散延伸区31a邻近于靠近源极端的栅极结构，并环绕源极区28形成一双扩散源极区。另一对称的扩散延伸区31b，邻近于靠近漏极区的栅极结构并环绕漏极区30，形成一双扩散漏极区。
虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下：
半导体基底：10
P型阱：12
N型阱：14、14a、14b、14c
临界电压调整区：15
浅沟槽绝缘结构：16a、16b
场氧化区：17a、17b
浅沟槽绝缘结构：18、18a、18b
栅极介电层：20
栅极：22
轻掺杂漏极区：24
介电间隙壁：26
源极区：28
N+区：29a
P+区：29b
漏极区：30
扩散延伸区：31、31a、31b
金属硅化物层：32
蚀刻停止层：34
层间介电层：36
接触窗：38
金属材料：40

Claims (11)

1.一种半导体元件，其特征在于，所述半导体元件包括：
一栅极结构，置于一半导体基底的一高电压元件区域上；
至少一扩散区域，形成在该高电压元件区域中，且侧面地位于该栅极结构的一侧或两侧；
一蚀刻停止层，置于该栅极结构及该扩散区域之上，其中该蚀刻停止层的电阻率大于10ohm-cm；以及
一层间介电层，置于该蚀刻停止层之上，且具有至少一接触窗，穿过该层间介电层及该蚀刻停止层。
2.根据权利要求1所述的半导体元件，其特征在于，该蚀刻停止层选择自除硅摩尔百分比超过55％的氮氧化硅外的所有介电材料。
3.根据权利要求1所述的半导体元件，其特征在于，该蚀刻停止层为一氮化硅层。
4.根据权利要求1所述的半导体元件，其特征在于，该蚀刻停止层包括一氧化硅层及一氮化硅层。
5.根据权利要求1所述的半导体元件，其特征在于，该蚀刻停止层为一硅摩尔百分比低于55％的氮氧化硅层。
6.根据权利要求1所述的半导体元件，其特征在于，该半导体元件为一操作电压超过5V的高电压晶体管。
7.一种半导体元件的制造方法，其特征在于，所述半导体元件的制造方法包括下列步骤：
提供一半导体基底，具有一高电压元件区域；
形成一栅极结构于该高电压元件区域上；
在该高电压元件区域中形成至少一扩散区域，其中该扩散区域侧面地位于该栅极结构的一侧或两侧；
在该栅极结构及该扩散区域上形成一蚀刻停止层，其中该蚀刻停止层的电阻率大于10ohm-cm；
在该蚀刻停止层上形成一层间介电层；以及
在该层间介电层中形成至少一接触窗，穿过该层间介电层及该蚀刻停止层。
8.根据权利要求7所述的半导体元件的制造方法，其特征在于，该蚀刻停止层选择自除硅摩尔百分比超过55％的氮氧化硅外的所有介电材料。
9.根据权利要求7所述的半导体元件的制造方法，其特征在于，该蚀刻停止层为一氮化硅层。
10.根据权利要求7所述的半导体元件的制造方法，其特征在于，该蚀刻停层包括一氧化硅层及一氮化硅层。
11.根据权利要求7所述的半导体元件的制造方法，其特征在于，该蚀刻停止层为一硅摩尔百分比低于55％的氮氧化硅层。
CNB2005101242422A 2004-11-29 2005-11-29 高电压晶体管元件及其制造方法 Active CN100399580C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/999,508 US7301185B2 (en) 2004-11-29 2004-11-29 High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage
US10/999,508 2004-11-29

Publications (2)

Publication Number Publication Date
CN1797786A true CN1797786A (zh) 2006-07-05
CN100399580C CN100399580C (zh) 2008-07-02

Family

ID=36566588

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005101242422A Active CN100399580C (zh) 2004-11-29 2005-11-29 高电压晶体管元件及其制造方法

Country Status (4)

Country Link
US (1) US7301185B2 (zh)
JP (1) JP2006156990A (zh)
CN (1) CN100399580C (zh)
TW (1) TWI258182B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148254A (zh) * 2011-01-21 2011-08-10 北京大学 深能级杂质电离碰撞晶体管
CN102842621A (zh) * 2011-06-24 2012-12-26 联发科技股份有限公司 半导体二极管
CN104979381A (zh) * 2014-04-01 2015-10-14 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN105810589A (zh) * 2014-12-30 2016-07-27 北大方正集团有限公司 一种pad制作方法
CN106098692A (zh) * 2015-04-28 2016-11-09 爱思开海力士有限公司 半导体器件及制造其的方法
CN101859702B (zh) * 2009-04-10 2016-12-07 赛普拉斯半导体公司 含多层氧氮化物层的氧化物-氮化物-氧化物堆栈
CN110137133A (zh) * 2019-03-07 2019-08-16 上海华虹宏力半导体制造有限公司 半导体器件的制作方法
CN114093766A (zh) * 2020-08-24 2022-02-25 联华电子股份有限公司 半导体装置及其制造方法

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4331690B2 (ja) * 2003-04-30 2009-09-16 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US7525150B2 (en) * 2004-04-07 2009-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage double diffused drain MOS transistor with medium operation voltage
JP2006031795A (ja) * 2004-07-14 2006-02-02 Renesas Technology Corp 不揮発性半導体記憶装置
US7067365B1 (en) * 2005-05-26 2006-06-27 United Microelectronics Corp. High-voltage metal-oxide-semiconductor devices and method of making the same
US7453127B2 (en) * 2006-02-13 2008-11-18 Taiwan Semiconductor Manufacturing Co., Ltd. Double-diffused-drain MOS device with floating non-insulator spacers
US7521741B2 (en) * 2006-06-30 2009-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Shielding structures for preventing leakages in high voltage MOS devices
KR20080008797A (ko) * 2006-07-21 2008-01-24 동부일렉트로닉스 주식회사 반도체 장치의 제조 방법
US8643124B2 (en) 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8063434B1 (en) 2007-05-25 2011-11-22 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8614124B2 (en) * 2007-05-25 2013-12-24 Cypress Semiconductor Corporation SONOS ONO stack scaling
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
JP5172223B2 (ja) * 2007-06-19 2013-03-27 ローム株式会社 半導体装置
DE102007052050B4 (de) * 2007-10-31 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement und Verfahren zum Erhöhen der Ätzselektivität während der Strukturierung einer Kontaktstruktur des Halbleiterbauelements
US9431549B2 (en) 2007-12-12 2016-08-30 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a high dielectric constant blocking region
US7898852B1 (en) 2007-12-27 2011-03-01 Cypress Semiconductor Corporation Trapped-charge non-volatile memory with uniform multilevel programming
US8207559B2 (en) * 2008-07-14 2012-06-26 Texas Instruments Incorporated Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
US8294216B2 (en) * 2008-08-14 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors
JP5444694B2 (ja) * 2008-11-12 2014-03-19 ソニー株式会社 固体撮像装置、その製造方法および撮像装置
US8643090B2 (en) * 2009-03-23 2014-02-04 Infineon Technologies Ag Semiconductor devices and methods for manufacturing a semiconductor device
US20110012267A1 (en) * 2009-07-17 2011-01-20 Stmicroelectronics S.R.L. Semiconductor integrated device having a contact structure, and corresponding manufacturing process
JP5434501B2 (ja) * 2009-11-13 2014-03-05 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよび半導体集積回路装置、半導体装置
US9577079B2 (en) 2009-12-17 2017-02-21 Infineon Technologies Ag Tunnel field effect transistors
JP5623898B2 (ja) * 2010-12-21 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5582030B2 (ja) 2010-12-28 2014-09-03 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよびその製造方法
JP5605241B2 (ja) * 2011-01-27 2014-10-15 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよび半導体集積回路装置の製造方法
US8536648B2 (en) 2011-02-03 2013-09-17 Infineon Technologies Ag Drain extended field effect transistors and methods of formation thereof
TWI408811B (zh) * 2011-02-25 2013-09-11 Richtek Technology Corp 高壓元件及其製造方法
JP5734725B2 (ja) * 2011-04-27 2015-06-17 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2013069777A (ja) * 2011-09-21 2013-04-18 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
US9356158B2 (en) * 2012-07-20 2016-05-31 Semiconductor Components Industries, Llc Electronic device including a tunnel structure
KR101883010B1 (ko) * 2012-08-06 2018-07-30 매그나칩 반도체 유한회사 반도체 소자 및 그 소자의 제조 방법
TWI577020B (zh) * 2013-05-15 2017-04-01 聯華電子股份有限公司 高壓金氧半導體電晶體元件
US8921972B2 (en) * 2013-05-16 2014-12-30 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device
US8981475B2 (en) 2013-06-18 2015-03-17 International Business Machines Corporation Lateral diffusion metal oxide semiconductor (LDMOS)
FR3011678B1 (fr) * 2013-10-07 2017-01-27 St Microelectronics Crolles 2 Sas Procede de relaxation des contraites mecaniques transversales dans la region active d'un transistor mos, et circuit integre correspondant
US9130033B2 (en) * 2013-12-03 2015-09-08 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
JP6194516B2 (ja) * 2014-08-29 2017-09-13 豊田合成株式会社 Ｍｉｓ型半導体装置
US9741726B2 (en) * 2014-12-05 2017-08-22 Semiconductor Components Industries, Llc Non-volatile memory cell and method of manufacture
TW201640566A (zh) * 2015-05-11 2016-11-16 聯華電子股份有限公司 半導體元件及其製作方法
US9935176B1 (en) * 2016-11-18 2018-04-03 Monolithic Power Systems, Inc. Method for fabricating LDMOS using CMP technology
US9893170B1 (en) * 2016-11-18 2018-02-13 Monolithic Power Systems, Inc. Manufacturing method of selectively etched DMOS body pickup
US10224407B2 (en) 2017-02-28 2019-03-05 Sandisk Technologies Llc High voltage field effect transistor with laterally extended gate dielectric and method of making thereof
TWI676289B (zh) * 2018-09-17 2019-11-01 世界先進積體電路股份有限公司 半導體裝置及其製造方法
CN111524960A (zh) * 2020-04-28 2020-08-11 电子科技大学 一种横向高压器件
CN111969060B (zh) * 2020-08-07 2024-04-16 长江存储科技有限责任公司 一种半导体器件及其制作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3677755B2 (ja) * 1995-09-26 2005-08-03 富士通株式会社 半導体装置及びその製造方法
KR100276387B1 (ko) * 1998-01-08 2000-12-15 윤종용 반도체 장치의 자기정렬 콘택 형성 방법
JPH11204641A (ja) * 1998-01-16 1999-07-30 Hitachi Ltd 半導体集積回路装置の製造方法
US6124217A (en) * 1998-11-25 2000-09-26 Advanced Micro Devices, Inc. In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects
US6245669B1 (en) * 1999-02-05 2001-06-12 Taiwan Semiconductor Manufacturing Company High selectivity Si-rich SiON etch-stop layer
US6074908A (en) * 1999-05-26 2000-06-13 Taiwan Semiconductor Manufacturing Company Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits
US6235653B1 (en) * 1999-06-04 2001-05-22 Taiwan Semiconductor Manufacturing Company Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer
US6576546B2 (en) * 1999-12-22 2003-06-10 Texas Instruments Incorporated Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications
US6492222B1 (en) * 1999-12-22 2002-12-10 Texas Instruments Incorporated Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6468870B1 (en) * 2000-12-26 2002-10-22 Taiwan Semiconductor Manufacturing Company Method of fabricating a LDMOS transistor
JP2002314069A (ja) * 2001-04-16 2002-10-25 Mitsubishi Electric Corp 半導体装置
US6444566B1 (en) * 2001-04-30 2002-09-03 Taiwan Semiconductor Manufacturing Company Method of making borderless contact having a sion buffer layer
JP4082014B2 (ja) * 2001-10-12 2008-04-30 富士電機デバイステクノロジー株式会社 半導体装置の製造方法
CN1198325C (zh) * 2001-12-04 2005-04-20 联华电子股份有限公司 金氧半导体晶体管的制造方法
JP4489345B2 (ja) * 2002-12-13 2010-06-23 株式会社ルネサステクノロジ 半導体装置の製造方法
KR100485384B1 (ko) * 2003-02-03 2005-04-27 삼성전자주식회사 반도체 소자의 제조방법
KR100680467B1 (ko) * 2004-11-10 2007-02-08 매그나칩 반도체 유한회사 정전기 방전 보호 소자

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859702B (zh) * 2009-04-10 2016-12-07 赛普拉斯半导体公司 含多层氧氮化物层的氧化物-氮化物-氧化物堆栈
CN102148254A (zh) * 2011-01-21 2011-08-10 北京大学 深能级杂质电离碰撞晶体管
CN102842621A (zh) * 2011-06-24 2012-12-26 联发科技股份有限公司 半导体二极管
CN104979381A (zh) * 2014-04-01 2015-10-14 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN104979381B (zh) * 2014-04-01 2018-07-13 世界先进积体电路股份有限公司 半导体装置及其制造方法
CN105810589A (zh) * 2014-12-30 2016-07-27 北大方正集团有限公司 一种pad制作方法
CN105810589B (zh) * 2014-12-30 2018-09-28 北大方正集团有限公司 一种导电垫pad制作方法
CN106098692A (zh) * 2015-04-28 2016-11-09 爱思开海力士有限公司 半导体器件及制造其的方法
CN110137133A (zh) * 2019-03-07 2019-08-16 上海华虹宏力半导体制造有限公司 半导体器件的制作方法
CN114093766A (zh) * 2020-08-24 2022-02-25 联华电子股份有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
TW200618064A (en) 2006-06-01
TWI258182B (en) 2006-07-11
US20060113627A1 (en) 2006-06-01
US7301185B2 (en) 2007-11-27
JP2006156990A (ja) 2006-06-15
CN100399580C (zh) 2008-07-02

Similar Documents

Publication Publication Date Title
CN100399580C (zh) 高电压晶体管元件及其制造方法
US10811533B2 (en) Medium high voltage MOSFET device
US6924530B2 (en) Double diffused MOS transistor and method for manufacturing same
US7893490B2 (en) HVNMOS structure for reducing on-resistance and preventing BJT triggering
CN107710418A (zh) 多屏蔽沟槽栅极场效应晶体管
CN1797762A (zh) 半导体晶片的半导体结构及其形成方法
US9000516B2 (en) Super-junction device and method of forming the same
CN1507064A (zh) 整合型晶体管及其制造方法
CN105118855A (zh) 具有多种厚度的栅极电介质的半导体元件
CN1738057A (zh) 具有增强的屏蔽结构的金属氧化物半导体器件
TW201916174A (zh) 半導體結構和半導體製造方法
US20070164325A1 (en) Three-dimensional multi-gate device and fabricating method thereof
US8823087B2 (en) Semiconductor device including auxiliary structure and methods for manufacturing a semiconductor device
CN100580892C (zh) 具有y型金属栅极的金属氧化物半导体晶体管及其工艺
US9105495B2 (en) Semiconductor device and related fabrication methods
CN1812060A (zh) 半导体器件的制造方法
TWI834903B (zh) 半導體裝置與其形成方法與鰭狀場效電晶體的形成方法
CN100345281C (zh) 半导体装置的制造方法
US20130307064A1 (en) Power transistor device and fabricating method thereof
US8466019B2 (en) Semiconductor device and bipolar-CMOS-DMOS
TW201535734A (zh) 半導體裝置及其製造方法
US20080054348A1 (en) Semiconductor device and a method of fabricating the same
EP2673806A1 (en) Semiconductor device and related fabrication methods
TWI730165B (zh) 半導體結構與半導體結構的製造方法
KR20090025757A (ko) Ｄｍｏｓ 트랜지스터 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant