TW201640566A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW201640566A
TW201640566A TW104114958A TW104114958A TW201640566A TW 201640566 A TW201640566 A TW 201640566A TW 104114958 A TW104114958 A TW 104114958A TW 104114958 A TW104114958 A TW 104114958A TW 201640566 A TW201640566 A TW 201640566A
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dielectric layer
substrate
gate dielectric
gate
semiconductor device
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TW104114958A
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蕭世楹
游焜煌
李年中
李文芳
王智充
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聯華電子股份有限公司
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Priority to TW104114958A priority Critical patent/TW201640566A/zh
Priority to CN201510308597.0A priority patent/CN106298485A/zh
Priority to US14/749,610 priority patent/US20160336417A1/en
Publication of TW201640566A publication Critical patent/TW201640566A/zh

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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，然後利用一第一圖案化遮罩形成一閘極介電層於基底上，去除第一圖案化遮罩，去除部分閘極介電層以及形成一淺溝隔離於閘極介電層兩側之基底中。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於基底上的高壓元件區製作淺溝隔離與閘極介電層的方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而在現今金屬閘極電晶體製作過程中，由於高壓區的閘極介電層通常突出於基底表面，因此高壓區所完成的金屬閘極一般明顯高於低壓區的金屬閘極，使後續以化學機械研磨(chemical mechanical polishing, CMP)製程去除部分層間介電層時容易磨掉大部分高壓區的金屬閘極。因此如何改良現行金屬閘極製程以解決此問題即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後利用一第一圖案化遮罩形成一閘極介電層於基底上，去除第一圖案化遮罩，去除部分閘極介電層以及形成一淺溝隔離於閘極介電層兩側之基底中。
本發明另一實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一硬遮罩於該基底上，形成一圖案化遮罩於硬遮罩旁，去除部分基底及硬遮罩以形成一第一凹槽以及一第二凹槽於第一凹槽兩側，以及形成一材料層於第一凹槽及第二凹槽內以形成一閘極介電層以及一淺溝隔離於閘極介電層兩側。
本發明又一實施例揭露一種半導體元件，包含一基底具有一低壓區以及一高壓區、一閘極介電層設於高壓區之基底內以及一淺溝隔離設於閘極介電層兩側。
請參照第1圖至第5圖，第1圖至第5圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板。基底12上定義有一元件區，例如一高壓元件區(或簡稱高壓區14)，其較佳於後續製程中用來製作一高壓半導體元件。在本實施例中，基底12表面可具有一氧化層16，其可為一原生氧化層(native oxide)或可利用臨場蒸氣產生技術(in-situ steam generation, ISSG)於基底12表面所形成之一薄氧化層，用來當作一緩衝氧化(buffer oxide)層，然後再形成一圖案化遮罩18於氧化層16上。在本實施例中，圖案化遮罩18較佳由氮化矽所構成，但不侷限於此。
接著如第2圖所示，利用圖案化遮罩18進行一氧化製程以形成一閘極介電層20於基底12上，其中閘極介電層20較佳形成於圖案化遮罩18未覆蓋的基底12上且與原本設於基底12表面的氧化層16融為一體。在本實施例中，閘極介電層20較佳與氧化層16由相同材料所構成，例如均由氧化矽所構成，且閘極介電層20的厚度較佳介於1500埃至1700埃，或更佳為1600埃。
如第3圖所示，先利用一乾蝕刻或濕蝕刻製程去除圖案化遮罩18，然後進行一濕蝕刻製程去除基底12表面的氧化層16及部分閘極介電層20。更具體而言，本實施例於拔除圖案化遮罩18後較佳以濕蝕刻去除閘極介電層20周圍的氧化層16以暴露出基底12表面，並同時去除部分閘極介電層20，包括去除靠近基底12的外圍閘極介電層20並同時降低原本閘極介電層20的整體厚度。至此形成一約略梯形的閘極介電層20於基底12內，其中閘極介電層20的上表面較佳與基底12表面齊平或低於基底12表面，而閘極介電層20靠近並接觸基底12的兩側則分別向下傾斜而構成一約略梯形的形狀。
隨後如第4圖所示，先於基底12表面，例如閘極介電層20周圍的基底12上再沉積一氧化層22，用來當作另一緩衝氧化層，然後形成另一圖案化遮罩24於氧化層22上並覆蓋部分氧化層22與部分閘極介電層20。在本實施例中，圖案化遮罩24與閘極介電層20較佳由不同材料所構成，其中圖案化遮罩24可選自由氮化矽、氮氧化矽以及氮碳化矽等所構成的群組。
如第5圖所示，接著進行另一蝕刻製程，利用圖案化遮罩24來去除部分氧化層22、部分基底12以及部分閘極介電層20，以形成一凹槽26於閘極介電層20周圍的基底12中。之後填入一材料層(圖未示)於凹槽26內，去除圖案化遮罩24及氧化層22並搭配進行一平坦化製程，例如以CMP方式去除部分材料層以形成一淺溝隔離28環繞並直接接觸閘極介電層20且淺溝隔離28與閘極介電層20上表面均與基底12表面齊平。在本實施例中，材料層及閘極介電層20較佳包含相同材料，例如兩者均由氧化矽所構成。此外，依據本發明另一實施例，又可選擇性於填入材料層後先以CMP方式去除部分材料層並停止於圖案化遮罩24表面，接著去除圖案化遮罩24以形成淺溝隔離28。由於此時間點之淺溝隔離28與閘極介電層20表面可能略高於基底12表面，可再利用後續所進行之清洗製程使淺溝隔離28與閘極介電層20表面與基底12表面齊平。若氧化層22未被完全去除，之後可擇性去除氧化層22，或直接進行另一氧化製程形成另一氧化層30於基底12、閘極介電層20與淺溝隔離28表面，用來當作其他低壓半導體元件的閘極介電層。至此即完成本發明第一實施例之一半導體元件的製作。
請參照第6圖至第9圖，第6圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖。如第6圖所示，首先提供一基底32，例如一矽基底或矽覆絕緣(SOI)基板。基底32上定義有一元件區，例如一高壓元件區(或簡稱高壓區34)，其較佳於後續製程中用來製作一高壓半導體元件。如同第一實施例，基底32表面設有一氧化層36，其可為一原生氧化層(native oxide)或利用臨場蒸氣產生技術(in-situ steam generation, ISSG)所形成之一薄氧化層，用來當作另一緩衝氧化層。接著形成一硬遮罩38於氧化層36上，其中硬遮罩38較佳由氧化矽所構成，但不侷限於此。在本實施例中，硬遮罩38之形成方式可先全面沉積一由氧化矽所構成的材料層於氧化層36上，然後利用微影暨蝕刻方式去除部分材料層以形成硬遮罩38。
然後如第7圖所示，形成一圖案化遮罩40於硬遮罩38旁的氧化層36上，例如環繞整個硬遮罩38。在本實施例中，硬遮罩38及圖案化遮罩40較佳由不同材料所構成，例如當硬遮罩38由氧化矽所構成時，圖案化遮罩40可選自由氮化矽、氮氧化矽及碳氧化矽等所構成的群組。
如第8圖所示，接著進行一蝕刻製程，利用圖案化遮罩40為遮罩去除硬遮罩38、部分氧化層36及部分基底32，以於基底32中形成一第一凹槽42及第二凹槽44環繞第一凹槽42。值得注意的是，本實施例利用蝕刻去除硬遮罩38與部分基底32時較佳利用硬遮罩38與基底32之間蝕刻選擇比的不同，亦即氧化矽與純矽之間不同的蝕刻選擇比來形成第一凹槽42與第二凹槽44。由於氧化矽所構成的硬遮罩38相較於純矽所構成的基底32具有較低的蝕刻率，本實施例利用前述蝕刻製程所形成的第一凹槽42與第二凹槽44分別具有不同深度，例如第一凹槽42之底表面較佳低於基底32之上表面但高於第二凹槽44之底表面。
隨後如第9圖所示，形成一較佳由氧化矽所構成的材料層(圖未示)於第一凹槽42與第二凹槽44內及圖案化遮罩40上，並利用一平坦化製程，例如以CMP去除部分材料層、圖案化遮罩40與氧化層36，使第一凹槽42與第二凹槽44內所剩餘的材料層與基底32表面齊平，以於原本第一凹槽42的位置形成一閘極介電層46以及於原本第二凹槽44的位置形成一淺溝隔離48直接接觸閘極介電層46，且淺溝隔離48與閘極介電層46上表面均與基底32表面齊平。若氧化層36於CMP過程中與圖案化遮罩40被一同去除，可再選擇性進行一氧化步驟形成另一氧化層64於基底32、淺溝隔離48與閘極介電層46表面，且此氧化層64亦可以當作其他低壓半導體元件的閘極介電層。至此即完成本發明第二實施例的製作。
請繼續參照第10圖，本發明於形成第5圖或第9圖之淺溝隔離後可依據製程需求搭配低壓區進行後續電晶體製程，包括於低壓區50及高壓區34的氧化層64上分別形成一閘極結構52，其中低壓區50的閘極結構52上表面較佳與高壓區34的閘極結構52上表面齊平，且低壓區50的淺溝隔離66與高壓區34中源極/汲極區域56外圍的淺溝隔離66也可選擇性與高壓區34的淺溝隔離48一同製作完成。
在本實施例中，閘極結構52的製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之先閘極介電層製程為例，可先於低壓區50及高壓區34的基底32上分別形成一包含高介電常數介電層與多晶矽材料所構成的虛置閘極(圖未示)，然後於虛置閘極側壁形成側壁子54。接著於側壁子54兩側的基底32中形成一源極/汲極區域56與磊晶層(圖未示)、形成一接觸洞蝕刻停止層(圖未示)覆蓋虛置閘極，並形成一由四乙氧基矽烷(Tetraethyl orthosilicate, TEOS)所組成的層間介電層58於接觸洞蝕刻停止層上。
之後可進行一金屬閘極置換(replacement metal gate)製程，先平坦化部分之層間介電層58及接觸洞蝕刻停止層，並再將虛置閘極轉換為一金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除虛置閘極中的多晶矽材料以於層間介電層58中形成一凹槽。之後形成一至少包含U型功函數金屬層60與低阻抗金屬層62的導電層於該凹槽內，並再搭配進行一平坦化製程使U型功函數金屬層60與低阻抗金屬層62的表面與層間介電層58表面齊平，以形成閘極結構52之閘極電極。此外，上述兩實施例均是在高壓區的閘極兩側下方分別形成一淺溝隔離，但視元件特性需求的不同，亦可以只在高壓區的閘極單一側下方形成有淺溝隔離，甚至是僅在高壓區中形成一厚而平坦的閘極介電層且完全埋設於基底內。
在本實施例中，功函數金屬層60較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層60可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層60可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層60與低阻抗金屬層62之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層62則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
綜上所述，本發明主要揭露一種於高壓元件區製作閘極介電層與淺溝隔離的方法，其中依據前述兩種實施例所完成的閘極介電層可完全埋設於基底內，例如高壓區與低壓區的閘極介電層的上表面與基底上表面齊平或低於基底上表面，換句話說，較厚的高壓區的閘極介電層係向下深入基底中。由於高壓區的閘極介電層不突出於基底表面，後續整合低壓區的金屬閘極製程時，低壓區的金屬閘極以及高壓區的金屬閘極便會一起相切齊於層間介電層的頂面，而使高壓區的金屬閘極便不至因突出的閘極介電層而被CMP製程磨掉。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧高壓區
16‧‧‧氧化層
18‧‧‧圖案化遮罩
20‧‧‧閘極介電層
22‧‧‧氧化層
24‧‧‧圖案化遮罩
26‧‧‧凹槽
28‧‧‧淺溝隔離
30‧‧‧氧化層
32‧‧‧基底
34‧‧‧高壓區
36‧‧‧氧化層
38‧‧‧硬遮罩
40‧‧‧圖案化遮罩
42‧‧‧第一凹槽
44‧‧‧第二凹槽
46‧‧‧閘極介電層
48‧‧‧淺溝隔離
50‧‧‧低壓區
52‧‧‧閘極結構
54‧‧‧側壁子
56‧‧‧源極/汲極區域
58‧‧‧層間介電層
60‧‧‧功函數金屬層
62‧‧‧低阻抗金屬層
64‧‧‧氧化層
66‧‧‧淺溝隔離
第1圖至第5圖為本發明第一實施例製作一半導體元件之方法示意圖。 第6圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖。 第10圖為本發明一實施例之一半導體元件之結構示意圖。
32‧‧‧基底
34‧‧‧高壓區
46‧‧‧閘極介電層
48‧‧‧淺溝隔離
50‧‧‧低壓區
52‧‧‧閘極結構
54‧‧‧側壁子
56‧‧‧源極/汲極區域
58‧‧‧層間介電層
60‧‧‧功函數金屬層
62‧‧‧低阻抗金屬層
64‧‧‧氧化層
66‧‧‧淺溝隔離

Claims (20)

  1. 一種製作半導體元件的方法，包含：      提供一基底；      利用一第一圖案化遮罩形成一閘極介電層於該基底上；      去除該第一圖案化遮罩；      去除部分該閘極介電層；以及      形成一淺溝隔離於該閘極介電層兩側之該基底中。
  2. 如申請專利範圍第1項所述之方法，其中該第一圖案化遮罩包含氮化矽。
  3. 如申請專利範圍第1項所述之方法，其中該閘極介電層包含氧化矽。
  4. 如申請專利範圍第1項所述之方法，另包含：      形成該第一圖案化遮罩於該基底上；以及      形成該閘極介電層於該第一圖案化遮罩未覆蓋之該基底上。
  5. 如申請專利範圍第1項所述之半導體元件，其中該閘極介電層之上表面與該基底上表面齊平或低於該基底上表面。
  6. 如申請專利範圍第1項所述之方法，另包含：      進行一第一蝕刻製程去除部分該閘極介電層；      形成一第二圖案化遮罩於該基底及部分該閘極介電層上；      進行一第二蝕刻製程以形成一凹槽於該閘極介電層兩側；以及      填入一材料層於該凹槽內以形成該淺溝隔離。
  7. 如申請專利範圍第6項所述之方法，其中該第二圖案化遮罩及該閘極介電層包含不同材料。
  8. 如申請專利範圍第6項所述之方法，其中該材料層及該閘極介電層包含相同材料。
  9. 一種製作半導體元件的方法，包含：      提供一基底；      形成一硬遮罩於該基底上；      形成一圖案化遮罩於該硬遮罩旁；      去除部分該基底及該硬遮罩以形成一第一凹槽以及一第二凹槽於該第一凹槽兩側；以及      形成一材料層於該第一凹槽及該第二凹槽內以形成一閘極介電層以及一淺溝隔離於該閘極介電層兩側。
  10. 如申請專利範圍第9項所述之方法，其中該硬遮罩包含氧化矽。
  11. 如申請專利範圍第9項所述之方法，其中該硬遮罩及該圖案化遮罩包含不同材料。
  12. 如申請專利範圍第9項所述之方法，另包含去除該硬遮罩及該硬遮罩正下方之部分該基底以形成該第一凹槽及去除該硬遮罩周圍之該基底以形成該第二凹槽。
  13. 如申請專利範圍第9項所述之方法，其中該第一凹槽之底表面低於該基底之上表面且高於該第二凹槽之底表面。
  14. 如申請專利範圍第9項所述之方法，其中該材料層包含氧化矽。
  15. 一種半導體元件，包含：      一基底，該基底包含一低壓區以及一高壓區；      一閘極介電層設於該高壓區之該基底內；以及      一淺溝隔離設於該閘極介電層兩側。
  16. 如申請專利範圍第15項所述之半導體元件，其中該閘極介電層完全設於該基底內。
  17. 如申請專利範圍第15項所述之半導體元件，其中該閘極介電層包含氧化矽。
  18. 如申請專利範圍第15項所述之半導體元件，其中該閘極介電層直接接觸該淺溝隔離。
  19. 如申請專利範圍第15項所述之半導體元件，其中該閘極介電層之上表面與該基底上表面齊平或低於該基底上表面。
  20. 如申請專利範圍第15項所述之半導體元件，另包含：      一第一金屬閘極設於該低壓區；以及      一第二金屬閘極設於該高壓區，其中該第一金屬閘極之上表面與該第二金屬閘極之上表面齊平。
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CN108538725B (zh) * 2018-03-30 2021-03-16 京东方科技集团股份有限公司 薄膜晶体管及其制造方法

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